The document discusses software generation of configuration transactions for PCI local bus. It introduces PCI bus and its address spaces including configuration, I/O, and memory spaces. It then describes the main approach of using software to generate configuration transactions through programming I/O ports and accessing configuration registers. Experimental results are also mentioned.

1. Software Generation of Configuration Transactions for PCI Local Bus PCI Local Bus Specification (Peripheral Component Interconnect ) PCI 1998

3. Introduction Different level of Bus

4. Introduction PCI BUS

6. PCI Lines

7. Bus Comparisons Bus Type Bus Width Bus Speed MB/sec ISA 16 bits 8 MHz 16 MB EISA 32 bits 8 MHz 32 MB VL-bus 32 bits 25 MHz 100 MB VL-bus 32 bits 33 MHz 132 MB PCI 32 bits 33 MHz 132 MB PCI 64 bits 33 MHz 264 MB PCI 64 bits 66 MHz 512 MB PCI 64 bits 133 MHz 1 GB

8. Bus Comparisons 4GB 100MHz (Diff.) x8 PCI Express 8GB 100MHz (Diff.) X16 PCI Express 2GB 100MHz (Diff.) x4 PCI Express 1GB 100MHz (Diff.) x2 PCI Express 500MB 100MHz (Diff.) x1 PCI Express MB/sec Bus speed Bus width Bus Type

17. Software Generation of Configuration Transactions

20. Example (PCI List)

21. Example (PCI Register)

23. Setting