Digital System Design Lab Experiments

Electronics System Engineering (ESE)
B.Tech 3rd
year
2015-16
Subject: - Digital System Design (DSD) VIKASH SAMRAT
Directed By: - Mr. Maheep Diwedi 2013/B/06
National Institute of Electronics and Information Technology
Aurangabad, Maharashtra (431004)

National Institute of Electronics and Information Technology,
Aurangabad, Maharashtra
Digital System Design
Roll No:- 2013/B/06 B.tech 3rd Year
Sr No. Experiment Date Signature
0 Introduction to VHDL 12-08-2015
1 Multiplexer 14-09-2015
2 Logic Gates 16-09-2015
3 NOT Gate 16-09-2015
4 Demultiplexer 14-09-2015
5 Half Adder 23-09-2015
6 Full Adder 23-09-2015
7 Half Subtractor 23-09-2015
8 Full Subtractor 23-09-2015
9 SR Latch 30-09-2015
10 SR Clock 30-09-2015
11 JK Flip Flop 30-09-2015
12 Full Adder Mapping 06-10-2015
13 Decoder 21-10-2015

Experiment – 0
Aim-: Introduction of VHDL.
VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language that can be used to model digital system at many level of
abstraction ranging from algorithmic level to the gate level. It is integrated
amalgamation of following language-
 Sequential Language
 Concurrent Language
 Net List Language
 Timing Specification Language
 Waveform Generation Language
This language not only defines the syntax but also defines very clear simulation
semantics for each language construct. Therefore, models written in this language
can be verified using VHDL simulation.
Features-:
 This language can be used as an exchange medium between chip vendors and
CAD tool users.
 The language can also be used a communication medium between different
CAD and CAE tool.
 The language support flexible design methodologies; top-down, bottom-up or
mixed.
 It supports both synchronous and asynchronous timing models.
 The language supports hierarchy; a digital system can be modelled as set of
interconnected components.
 It is not technology specific but is capable of supporting technology specific
features.
VHDL is used to describe a model for a digital hardware device. This model specifies
the external view of the device and one or more internal views. The internal view of
the device specifies the functionality or structure, while the external view specifies
the interface of the device through which it communicates with the other model in
its environment.
Terminology-: Basic construct of design units
 Entity Declaration

 Architecture Body
 Configuration Declaration
 Package Declaration
 Package Body
Architecture Body-: The internal details of an entity are specified by an architecture
body using any of the following modelling types:
 As a set of interconnected components(to represent structure)
 As a set of concurrent assignment(to represent data flow)
 As a set of sequential assignment statements(to represent behaviour)
 As any combination of above three(mixed)
Entity Declaration-: An entity is modelled using an entity declaration and at least
one architecture body. Entity declaration describes the external view of the entity.
The entity declaration specifies the name of the entity being modelled and lists the
set of interface ports. Ports are signals through which the entity communicates with
the other models in its external environment.
Syntax:
entity entity_name is
Port declaration;
end entity_name;
An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords. Ports
are interfaces through which an entity can communicate with its environment. Each
port must have a name, direction and a type. An entity may have no port declaration
also. The direction will be input, output or in-out.
In Port can be read
Out Port can be written
In-out Port can be read and written
Buffer Port can be read and written,
it can have only one source.
Architecture Body-: Architecture body contains the internal description of the entity.
Each entity has at least one architecture and one entity can have many architecture.
Architecture can be described using structural, dataflow, behavioural or mixed style.
Architecture can be used to describe a design at different levels of abstraction like
gate level, register transfer level (RTL) or behaviour level.
Syntax:

architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;
Configuration Declaration-: A configuration declaration is used to create a
configuration for an entity. It specifies the binding of one architecture body from the
many architecture the many architecture bodies that may be associates with the
entity. It may also specify the binding of component used in the selected
architecture body to other entries.
Syntax:
configuration configuration_name of entity_name is
block_configuration;
end configuration_name;
Package Declaration-: A package declaration encapsulates a set of related
declaration such as type declaration, subtypes declaration and subprogram
declaration, which can be shared across two or more design units.
Syntax:
package package_name is
Declarations;
end package_name;
Package Body-: A package body contain the definitions of subprogram declared in
package declaration.
Syntax:
package body package_name is
Function_procedure definitions;
end package_name;
Modelling Style-:
Data Flow Style of Modelling-: In this modelling style, the data through the entity is
expressed primarily using concurrent signal assignment statements. The structure of
entity is not explicit specified in this modelling style, but it can be implicitly deduced.

Behavioural Style of Modelling-: Behavioural style of modelling specifies the
behaviour of an entity as a set of statements that are executed sequentially in the
specified order.
It contains:
 Process Statement
 Sequential Statement
 Signal Assignment Statement
 Wait Statement
Process statement is the primary mechanism used to model the behaviour of an
entity. It contains sequential statements, variable assignment (:=) statements or
signal assignment (<=) statements etc. It may or may not contain sensitivity list. If
there is an event occurs on any of the signals in the sensitivity list, the
statements within the process are executed. Inside the process the execution of
statements will be sequential and if one entity is having two processes the
execution of these processes will be concurrent. At the end it waits for another
event to occur.
Structural Modelling-: In the structural style of modelling, an entity is described as a
set of interconnected components.
It contains:
 Signal Declaration
 Component Instances
 Port Map
 Wait Statement
Component Declaration Syntax:
component component_name [is]
List_of_interface ports;
end component component_name;
Before instantiating the component it should be declared using component
declaration as shown above. Component declaration declares the name of the
entity and interface of a component.
Mixed Style of Modelling-: It is possible to mix the three modelling styles that have
seen so far in a single architecture body.

Experiment - 1
Aim-: Simulation/ Designing of Multiplexer in VHDL.
Program:-
--Simulation of Multiplexer--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer_4_1 is
port (
din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC
);
end multiplexer_4_1;
architecture multiplexer4_1_arc of multiplexer_4_1 is
begin
mux : process (din,sel) is
begin
if (sel="00") then
dout <= din(3);
elsif (sel="01") then
dout <= din(2);
dout <= din(1);
else
dout <= din(0);
end if;
end process mux;
end multiplexer4_1_arc;
Truth Table-:
Din S1 S2 Dout Min-
Terms
D3 0 0 D3 S1S0
D2 0 1 D2 S1S0
D1 1 0 D1 S1S0
D0 1 1 D0 S1S0

Result-:
Conclusion: - Hence we’ve analyzed and simulate 4:1 multiplexer.

Experiment – 2
Aim-: Simulation/ designing of Logic gates in VHDL.
Program:-
--Simulation of Logic gates--
library IEEE;
entity logic_gate_2_1 is
port(
din : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC_VECTOR(6 downto 1);
);
end logic_gate_2_1;
architecture logic_gate_2_1_arc of logic_gate_2_1 is
begin
gate : process (din) is
begin
dout(1)<=din(0)and din(1);
dout(2)<=din(0)OR din(1);
dout(3)<=din(0)xnor din(1);
dout(4)<=din(0)nOR din(1);
dout(5)<=din(0)nand din(1);
dout(6)<=din(0)xOR din(1);
end process gate;
end logic_gate_2_1_arc;
Truth Table-:
A B OR AND XOR X-NOR NAND NOR
0 0 0 0 0 1 1 1
0 1 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 1 1 1 0 1 0 0
OR AND XOR
C= AB
XNOR NAND NOR
=

Result:-
Conclusion: - Hence we have analyzed all the logic gates.

Experiment – 4
Aim-: Simulation/Designing of De-multiplexer in VHDL.
Program:-
--Simulation of De-multiplexer--
library IEEE;
entity demultiplexer_1_4 is
port(
sel : in STD_LOGIC_VECTOR(1 downto 0);
din : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0));
end demultiplexer_1_4;
architecture demultiplexer1_4_arc of demultiplexer_1_4 is
begin
demux : process (din,sel) is
begin
if (sel="00") then
dout<="000" & din;
dout<="00" & din &'0';
dout<='0' & din & "00";
else
dout<=din & "000";
end if;
end process demux;
end demultiplexer1_4_arc;
Truth Table-:
Input Line Output Line
S1 S0 D3 D2 D1 D0
0 0 0 0 0 Din
0 1 0 0 Din 0
1 0 0 Din 0 0
1 1 Din 0 0 0

Result:-
Conclusion: - We have analyzed and simulated de multiplexer.

Experiment – 5
Aim-: Designing/Simulation of Half Adder in VHDL.
Program:-
--Simulation of Half Adder--
library IEEE;
entity adder is
port(
X,Y,:in STD_LOGIC;
Cout: out STD_LOGIC
);
end adder;
architecture equation of adder is
begin
sum <= X xor Y;
Cout <= x and Y;
end equation;
Truth Table-: A logic circuit for the addition of two one bit numbers known to as
an half adder.
Inputs Outputs
A B Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Sum=
Sum
Cout =AB

Result:-
Conclusion: - We have analyzed and simulated half adder.

Experiment – 6
Aim-: Simulation/Designing of Full Adder in VHDL.
Program:-
--Simulation of Full Adder--
library IEEE;
entity full_adder is
port (
X,Y,Cin: in STD_LOGIC;
Cout,Sum: out STD_LOGIC
);
end full_adder;
architecture equation of full_adder is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or ((X xor Y) and Cin);
end equation;
Truth Table-: It performs the arithmetic sum of the three input bits i.e. addend bit
and carry bit.
Inputs Outputs
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum =
Carry = = AB+(

Result:-
Conclusion: - We have analyzed and simulated full adder.

Experiment – 7
Aim-: Simulation/Designing of Half-Subtractor in VHDL.
Program:-
--Simulation of Half Subtractor--
library IEEE;
entity subtractor is
port(X,Y: in STD_LOGIC;
Sub,Bor: out STD_LOGIC);
end subtractor;
architecture equation of subtractor is
begin
Sub <= X xor Y;
Bor <= (not X) and Y;
end equation;
Truth Table-:
Inputs Outputs
A B Diff B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Diff =
Borrow =
Result:-

Conclusion: - We have simulated and studied VHDL code of half subtractor.

Experiment – 8
Aim-: Simulation/Designing of Full-Subtractor in VHDL.
Program:-
--Simulation of Full Subtractor--
library IEEE;
entity full_subtractor is
port (X,Y,Bin: in STD_LOGIC;
Bout,Sub: out STD_LOGIC
);
end full_subtractor;
architecture equation of full_subtractor is
begin
Sum <= X xor Y xor Bin;
Cout <= (X xnor Y) or ((not X) and Y);
end equation;
Truth Table-:
Inputs Outputs
A B C Diff B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Diff =
Borrow = =

Result:-
Conclusion: - We have studied VHDL code and simulated full subtratctor.

Experiment – 9
Aim-: Simulation/Designing of SR Latch in VHDL.
Program:-
--Simulation of SR Latch--
library IEEE;
entity S_R_LATCH is
port(
S,R:in STD_LOGIC;
Q:out STD_LOGIC;
Z: STD_LOGIC;
X: STD_LOGIC
);
end S_R_LATCH;
architecture S_R_LATCH_arc of S_R_LATCH is
begin
S_R_LATCH : process(S,R) is
begin
if (S='0' and R='0')then
Q<= 'Z';
elsif (S='0' and R='1') then
Q<='0';
Q<='1';
Q<='X';
end if;
end process S_R_LATCH;
end S_R_LATCH_arc;
Truth Table-:
S R Qn Qn+1
0 0 0
Not Valid
0 0 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0
Memory
1 1 1

Result:-
Conclusion: - We have analyzed and simulated SR latch.

Experiment – 10
Aim-: Simulation/Designing of SR Clocked in VHDL.
Program:-
--Simulation of SR Clocked--
library IEEE;
entity Clock_S_R is
port(
S,R,CLK:in STD_LOGIC;
Q:out STD_LOGIC;
Z: STD_LOGIC;
W: STD_LOGIC;
X: STD_LOGIC
);
end Clock_S_R;
architecture Clock_S_R_arc of Clock_S_R is
begin
Clock_S_R : process(CLK,S,R) is
begin
if (CLK='0' and S='X' and R='X') then
Q<='W';
elsif (CLK='1' and S='0' and R='0') then
Q<='Z';
Q<='1';
Q<='0';
Q<='W';
end if;
end process;
end Clock_S_R_arc;
Truth Table-:
CLK S R Qn Qn+1
1 0 0 0
Memory
1 0 0 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0
Not Valid
1 1 1 1
0 X X X Memory

Result:-
Conclusion: - We have seen hardware module and simulate SR clock.

Experiment – 11
Aim-: Simulation/Designing of JK flip flop in VHDL.
Program:-
--Simulation of JK flip flop--
library IEEE;
entity JK_flipflop is
port(
J,K,CLK:in STD_LOGIC;
Q:out STD_LOGIC;
Z: STD_LOGIC;
X: STD_LOGIC
);
end JK_flipflop;
architecture JK_flipflop_arc of JK_flipflop is
begin
J_K_flipflop : process(CLK,J,K) is
begin
if (CLK='0' and J='X' and K='X') then
Q<='Z';
elsif (CLK='1' and J='0' and K='0')then
Q<= 'Z';
elsif (CLK='1' and J='0' and K='1') then
Q<='0';
Q<='1';
Q<= not 'Z';
end if;
end process J_K_flipflop;
end JK_flipflop_arc;
Truth Table-:
CLK J K Q Q
1 0 0 0
Q
1 0 0 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0
1 1 1 1
0 X X X Memory
Qn+1 = J n+ n

Result:-
Conclusion: - We have done VHDL program of JK flip flop.

Experiment -12
Aim-: Designing Full Adder by port mapping.
Description-: Port mapping in VHDL is one to many; it’s mean by defining
particular block we can map on other multiple blocks. Likewise for full adder, we
can design one full adder and map on other block. Similarly for n-bit full adder or
subtractor and anything can design by through logic.
Port Mapping of Full Adder and Combinational Logic on Full Adder
So in port mapping, we just have to define half one full port or block and port it
one by one on full adder blocks.
Program:-
--Simulation of Full Adder by port mapping--
library IEEE;
entity full_port is
port(
A,B : in STD_LOGIC_vector(3 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Sum : out STD_LOGIC_vector(3 downto 0)
);
end full_port;
architecture structure of full_port is
component full_adder
port (
A,B,Cin: in STD_LOGIC;
Full Adder
Full Adder 0
Full Adder 1
Full Adder 2
Full Adder 3

Cout,Sum: out STD_LOGIC
);
end component;
signal C: STD_LOGIC_vector(3 downto 1);
begin
FA0:full_adder port map (A(0),B(0),Cin,C(1),Sum(0));
FA1:full_adder port map (A(1),B(1),C(1),C(2),Sum(1));
FA2:full_adder port map (A(2),B(2),C(2),C(3),Sum(2));
FA3:full_adder port map (A(3),B(3),C(3),Cout,Sum(3));
end structure;
Result: -
Conclusion: - I have seen port mapping of one full adder on rest full adder blocks.

Experiment – 13
Aim: - Designing of Decoder in VHDL.
Program: -
--Simulation of Decoder--
library IEEE;
entity decoder_2_4 is
port(
A,B,EN: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder_2_4;
architecture decoder of decoder_2_4 is
begin
decoder : process (A,B,EN) is
variable ABAR,BBAR : STD_LOGIC;
begin
ABAR := not A;
BBAR := not B;
if (EN<='1') then
Y(3)<= not (A and B);
Y(2)<= not (A and BBAR);
Y(1)<= not (ABAR and B);
Y(0)<= not (ABAR and BBAR);
else
Y<="1111";
end if;
end process;
end decoder;
Truth Table: -
EN A B D3 D2 D1 D0
0 X X X X X X
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
D0 =
D1 =
D2 = A
D3 = AB

Result: -
Conclusion: - Thus we’ve studied designing of decoder in VHDL.

Experiment - 3
Aim-: Simulation/ Designing of NOT gate in VHDL.
Program:-
--Simulation of NOT Gate--
library IEEE;
entity not_gate is
port(A:in STD_LOGIC;
C:out STD_LOGIC
);
end not_gate;
architecture func of not_gate is
begin
C <= not A;
end func;
Truth Table-:
A Y Min-terms
0 1
1 0
Result:-

Conclusion: - I have studied NOT gate hardware in VHDL.

Digital System Design Lab Experiments

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (12)

Similar to Digital System Design Lab Experiments

Similar to Digital System Design Lab Experiments (20)

Recently uploaded

Recently uploaded (20)

Digital System Design Lab Experiments