VHDL 360©<br />by: Mohamed Samy<br />        Samer El-Saadany<br />
Copyrights<br />Copyright © 2010 to authors. All rights reserved<br />All content in this presentation, including charts, ...
Objective<br />Create your first VHDL model for simple logic circuits<br />Skills gained:<br />Know the basic structure of...
Outline<br />Entity<br />Architecture<br />Internal Signals<br /><ul><li>Expressions & Operators
With-Select
When-Else</li></ul>VHDL 360 ©<br />4<br />
VHDL Design Units<br />After understanding our first model*, let’s move forward & understand how to construct one<br />5<b...
VHDL Design Units<br />A VHDL Model (Design unit) consists of:<br />Entity<br />Define ports (inputs and outputs)<br />Arc...
Entity Description<br />entity <entity_name> is<br />port ( <br />       <port_name> : <mode>  <type>;<br />       <port_n...
Entity Description<br />8<br />VHDL 360 ©<br />Bit values:<br />‘0’    --Binary Zero<br />‘1’    -- Binary One<br />Std_lo...
Exercise 1<br />Write the entity of the following:<br />1-bit Full Adder<br />9<br />VHDL 360 ©<br />
Answer of Exercise 1 <br />10<br />VHDL 360 ©<br />LIBRARY ieee; <br />USE ieee.std_logic_1164.all;<br />ENTITYfullAdderIS...
Architecture Description<br />architecture <arch_name> of <entity_name> is<br />-- architecture declarations <br />begin<b...
Architecture Body<br /><target>  <= <expression>;<br />12<br />VHDL 360 ©<br />Architecture body can only contain concurre...
Internal signals<br />We use Internal Signals for:<br />Internal connections in structural description<br />Intermediate c...
Internal signals<br />Example:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />E...
Expressions & Operators<br />15<br />VHDL 360 ©<br />Each operator is defined for specific data type(s)<br />Arithmetic op...
Operators*<br />16<br />VHDL 360 ©<br />More operator will be presented throughout the course<br />
Operators<br />17<br />VHDL 360 ©<br />Example:<br />-- Library & package used for architecture scope<br />LIBRARY ieee; 	...
Exercise 2<br />Write the architecture of the following:<br />1-bit Full Adder<br />18<br />VHDL 360 ©<br />
Answer of Exercise 2 <br />19<br />VHDL 360 ©<br />LIBRARY ieee; <br />USE ieee.std_logic_1164.all;<br />ENTITYfullAdderIS...
20<br />VHDL 360 ©<br />a<br />b<br />F<br />c<br />d<br />Sel(1:0)<br />Architecture Body<br />With-Select<br /><select_s...
21<br />VHDL 360 ©<br />a<br />b<br />F<br />c<br />d<br />Sel(1:0)<br />Architecture Body<br />When-else<br />LHS can be ...
Exercise 3 <br />a<br />F<br />2<br />4<br />F<br />a<br />4<br />2<br />Write the entity and architecture of the followin...
Decoder 2x4(with-select)<br />a<br />F<br />2<br />4<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity decode...
Decoder 2x4 (when-else)<br />a<br />F<br />2<br />4<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity decoder...
Encoder4x2 (with-select)<br />F<br />a<br />2<br />4<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity encode...
Contacts<br />You can contact us at:<br />http://www.embedded-tips.blogspot.com/<br />VHDL 360 ©<br />26<br />
Create your first model for a simple logic circuit
Create your first model for a simple logic circuit
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Create your first model for a simple logic circuit

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Create your first VHDL model for simple logic circuits

Skills gained:
1- Know the basic structure of a VHDL model (entity, architecture)
2- Model simple combinational logic

This is part of VHDL 360 course

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Create your first model for a simple logic circuit

  1. 1. VHDL 360©<br />by: Mohamed Samy<br /> Samer El-Saadany<br />
  2. 2. Copyrights<br />Copyright © 2010 to authors. All rights reserved<br />All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.<br />Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.<br />Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. <br />Product names and trademarks mentioned in this presentation belong to their respective owners.<br />VHDL 360 ©<br />2<br />
  3. 3. Objective<br />Create your first VHDL model for simple logic circuits<br />Skills gained:<br />Know the basic structure of a VHDL model (entity, architecture)<br />Model simple combinational logic<br />VHDL 360 ©<br />3<br />
  4. 4. Outline<br />Entity<br />Architecture<br />Internal Signals<br /><ul><li>Expressions & Operators
  5. 5. With-Select
  6. 6. When-Else</li></ul>VHDL 360 ©<br />4<br />
  7. 7. VHDL Design Units<br />After understanding our first model*, let’s move forward & understand how to construct one<br />5<br />VHDL 360 ©<br />Module 0: Introduction to VHDL<br />
  8. 8. VHDL Design Units<br />A VHDL Model (Design unit) consists of:<br />Entity<br />Define ports (inputs and outputs)<br />Architecture<br />Define operation (input/output relation)<br />VHDL 360 ©<br />6<br />
  9. 9. Entity Description<br />entity <entity_name> is<br />port ( <br /> <port_name> : <mode> <type>;<br /> <port_name> : <mode> <type>;<br />…<br />-- last port has no semicolon<br /> <port_name> : <mode> <type> <br /> );<br />Endentity;<br />7<br />VHDL 360 ©<br /><mode>: port direction<br />IN: Input that can only be read<br />OUT: Output that can only be written to<br />INOUT: Input or output can be read and written to<br />Syntax:<br />Example:<br />ENTITY model1 IS--VHDL is case insensitive<br />PORT( a :INstd_logic;<br /> b :INstd_logic;<br /> c :INstd_logic;<br /> d :INstd_logic;<br /> e :OUTstd_logic);<br />END model1 ;<br />
  10. 10. Entity Description<br />8<br />VHDL 360 ©<br />Bit values:<br />‘0’ --Binary Zero<br />‘1’ -- Binary One<br />Std_logic values<br />‘U’ -- Uninitialized<br />‘X’ -- Forcing Unknown<br />‘0’ --Forcing Zero<br />‘1’ -- Forcing One<br />‘Z’ -- High Impedance<br />‘W’ -- Weak Unknown<br />‘L’ -- Weak Zero<br />‘H’ -- Weak One<br />‘-’ -- Don’t Care<br />Types:<br />VHDL offers the following standard types:<br />Integer: -231 to 231-1<br />Bit, Bit_vector<br />…<br />IEEE Packages offer more types:<br />Std_logic, std_logic_vector<br />…<br />Require use of appropriate IEEE packages<br />Example: Using Standard Types<br />Example: Using IEEE Types<br />LIBRARY ieee; <br />USE ieee.std_logic_1164.all;<br />ENTITY model1 IS<br />PORT( a :INstd_logic;<br />b :INstd_logic;<br /> c :INstd_logic;<br /> d :INstd_logic;<br /> e:OUTstd_logic_vector(7 downto 0));<br />END model1 ;<br />ENTITY model1 IS<br /> PORT( a :INbit_vector(3 downto 0);<br />b :INbit;<br /> c :INbit;<br /> d :INbit;<br /> e :OUTbit);<br />END model1 ;<br />
  11. 11. Exercise 1<br />Write the entity of the following:<br />1-bit Full Adder<br />9<br />VHDL 360 ©<br />
  12. 12. Answer of Exercise 1 <br />10<br />VHDL 360 ©<br />LIBRARY ieee; <br />USE ieee.std_logic_1164.all;<br />ENTITYfullAdderIS<br /> PORT( In1, In2, CarryIn:INstd_logic;<br />Sum :OUTstd_logic;<br />CarryOut:OUT std_logic);<br />ENDfullAdder;<br />
  13. 13. Architecture Description<br />architecture <arch_name> of <entity_name> is<br />-- architecture declarations <br />begin<br />-- architecture body<br />endarchitecture;<br />11<br />VHDL 360 ©<br />Syntax:<br />A given architecture represents one possible implementation for its associated entity<br />Architecture declaration: defines internal signals, components, types …etc to be used in architecture body<br />Architecture body: defines implementation details of input/output relationship<br />Multiple architectures can exist for each entity<br />Example:<br />Internal signals<br />ARCHITECTURErtlOF model1 IS<br />SIGNAL x :std_logic;<br />SIGNAL y :std_logic;<br />BEGIN<br /> x <= a AND b;<br /> y <= c AND d;<br /> e <= x OR y;<br />ENDrtl;<br />signal <sig_name>: <sig_type>;<br />Concurrent Assignments<br />
  14. 14. Architecture Body<br /><target> <= <expression>;<br />12<br />VHDL 360 ©<br />Architecture body can only contain concurrent statements, in this module we will only focus on<br />Concurrent assignments<br />When-else<br />With-select<br />Concurrent Assignments<br />LHS can be an internal signal or an output port<br />RHS is an expression that operates on internal signal and/or input ports<br />Syntax:<br />Example:<br />ARCHITECTUREexprOF example1 IS<br />SIGNAL u, w, x, y, z :std_logic;<br />SIGNAL a, b, c :integer;<br />BEGIN<br /> x <= y AND z;-- logical expression<br /> w <=NOT x;<br /> u <= w;-- direct assignment<br /> c <= a + b;-- arithmetic expression<br />ENDexpr;<br />Arithmetic Operators<br />+ , - , * , /<br />Logical Operators<br />NOT<br />AND, NAND<br />OR, NOR<br />XOR, XNOR<br />
  15. 15. Internal signals<br />We use Internal Signals for:<br />Internal connections in structural description<br />Intermediate calculations<br />Avoid illegal port usage situations:<br />Read Output port<br />Syntax:<br />architecture <arch_name> of <entity_name> is<br />-- architecture declarations <br />signal <sig_name>: <sig_type>;<br />begin<br />-- assign to internal signal<br /><sig_name> <= <expression>;<br />-- read the internal signal<br /><sig_name> <= <expression>;<br />endarchitecture;<br />Example:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY illegal IS<br />PORT( A :INstd_logic;<br /> B :INstd_logic;<br /> C :INstd_logic;<br /> F :OUTstd_logic;<br /> G :OUTstd_logic);<br />END illegal ;<br />ARCHITECTUREstructOF illegal IS<br /> -- Internal signal declarations<br />SIGNAL sig1 :std_logic;<br />SIGNAL sig2 :std_logic;<br />SIGNAL sig3 :std_logic;<br />BEGIN<br /> F <= sig3 AND sig1 AND C;<br /> G <= F AND sig1 AND sig2;-- Reading Out port F is illegal<br /> sig3 <=NOT(A);<br />sig1 <=NOT(B);<br /> sig2 <=NOT(C);<br />ENDstruct;<br />Illegal use of an output port<br />(used as the “and” gate input)<br />13<br />VHDL 360 ©<br />
  16. 16. Internal signals<br />Example:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY legal IS<br />PORT( A :INstd_logic;<br /> B :INstd_logic;<br /> C :INstd_logic;<br /> F :OUTstd_logic;<br /> G :OUTstd_logic);<br />END legal ;<br />ARCHITECTUREstructOF legal IS<br /> -- Internal signal declarations<br />SIGNAL sig1 :std_logic;<br />SIGNAL sig2 :std_logic;<br />SIGNAL sig3 :std_logic;<br />SIGNAL sig4 :std_logic;<br />BEGIN<br /> sig4 <= sig3 AND sig1 AND C;<br />-- using internal signal sig4<br /> G <= sig4 AND sig1 AND sig2;<br /> F <= sig4;<br /> sig3 <=NOT(A);<br />sig1 <=NOT(B);<br /> sig2 <=NOT(C);<br />ENDstruct;<br />Internal Signals used for intermediate relations<br />14<br />VHDL 360 ©<br />
  17. 17. Expressions & Operators<br />15<br />VHDL 360 ©<br />Each operator is defined for specific data type(s)<br />Arithmetic operators are defined for standard integer types<br />Logical operators are defined for the standard bit, bit_vector types<br />Logical & arithmetic operators are defined for std_logic & std_logic_vector types in IEEE std_logic_* packages  You need to use the appropriate package before applying an operator on a type<br />Example:<br />ARCHITECTUREstructOFexprIS<br /> -- Internal signal declarations<br /> SIGNAL x, y, z :integer;<br />BEGIN<br />-- Operators can be chained to form complex expressions <br /> F <= C AND (NOT(B)) AND (NOT(A));<br />-- parentheses control association of operators and operands<br />-- use parentheses for readability<br /> G <= (COR (NOT(A)))XOR(NOT(B) AND(BNORC));<br /> Z <= X + Y; -- using addition operator defined for integer type<br />ENDstruct;<br />
  18. 18. Operators*<br />16<br />VHDL 360 ©<br />More operator will be presented throughout the course<br />
  19. 19. Operators<br />17<br />VHDL 360 ©<br />Example:<br />-- Library & package used for architecture scope<br />LIBRARY ieee; <br />USE ieee.std_logic_unsigned.all; -- Need to use unsigned arithmetic operators<br />ARCHITECTUREexprOF example1 IS<br />SIGNAL u, w :std_logic_vector(3 downto 0);<br />SIGNAL a :integer;<br />BEGIN<br />-- Adding an integer to an std_logic_vector returning std_logic_vector<br /> u <= w + a;<br />ENDexpr;<br />Where’s the Carry Out?!<br />
  20. 20. Exercise 2<br />Write the architecture of the following:<br />1-bit Full Adder<br />18<br />VHDL 360 ©<br />
  21. 21. Answer of Exercise 2 <br />19<br />VHDL 360 ©<br />LIBRARY ieee; <br />USE ieee.std_logic_1164.all;<br />ENTITYfullAdderIS<br /> PORT( In1, In2, CarryIn:INstd_logic;<br />Sum :OUTstd_logic;<br />CarryOut:OUT std_logic);<br />ENDfullAdder;<br />ARCHITECTUREexprOFfullAdderIS<br /> signal temp :std_logic;<br />BEGIN<br />temp <=In1 XOR In2;<br /> Sum <= temp XORCarryIn;<br />CarryOut<= (In1 AND In2) OR (CarryInAND temp);<br />ENDexpr;<br />
  22. 22. 20<br />VHDL 360 ©<br />a<br />b<br />F<br />c<br />d<br />Sel(1:0)<br />Architecture Body<br />With-Select<br /><select_signal> can be an internal signal or an input port<br /><target> can be an internal signal or an output port<br /><value> constants representing one of possible <select_signal> values.<br />“When others” is a must if not all values of <select_signal> are covered<br />Syntax:<br />With <select_signal> select<br /> <target> <= <expression> when <value>,<br /> <expression> when <value>,<br /> …. < expression> whenothers;<br />Example:<br />Architecture behave ofmux_withis<br />Begin<br />Withselselect<br /> F <= a when"00",<br /> b when"01",<br /> c when"10",<br /> d whenothers; -- needed to cover missing “sel” values<br />EndArchitecture;<br />
  23. 23. 21<br />VHDL 360 ©<br />a<br />b<br />F<br />c<br />d<br />Sel(1:0)<br />Architecture Body<br />When-else<br />LHS can be an internal signal or an output port<br />RHS is an expression that operates on internal signal and/or input ports when the branch condition is true<br />Last “else” branch covers all missing conditions<br />Syntax:<br /><target> <= <expression> when <condition><br /> else <expression> when <condition><br /> else <expression> when <condition><br /> …<br /> else <expression> ;<br />Example:<br />Architecture behave ofmux_whenis<br />Begin<br />F <= a whensel="00"else<br /> b whensel="01"else<br /> c whensel="10"else<br /> d;-- This is one statement with semicolon at the end only<br />EndArchitecture;<br />
  24. 24. Exercise 3 <br />a<br />F<br />2<br />4<br />F<br />a<br />4<br />2<br />Write the entity and architecture of the following (using with-select then using when-else):<br />2x4 Decoder<br />4x2 Encoder<br />Encoder4x2<br />Decoder2x4<br />22<br />VHDL 360 ©<br />
  25. 25. Decoder 2x4(with-select)<br />a<br />F<br />2<br />4<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity decoder2x4 is<br />port(a:instd_logic_vector(1downto0);<br /> F:outstd_logic_vector(3downto0));<br />endentity;<br />Architecture behave of decoder2x4 is<br />Begin<br /> with A select<br /> F <="0001"when"00",<br />"0010"when"01",<br /> "0100"when"10",<br /> "1000" when others;<br />EndArchitecture;<br />23<br />VHDL 360 ©<br />
  26. 26. Decoder 2x4 (when-else)<br />a<br />F<br />2<br />4<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity decoder2x4 is<br />port(a:instd_logic_vector(1downto0);<br /> F:outstd_logic_vector(3downto0));<br />endentity;<br />Architecture behave of decoder2x4 is<br />Begin<br /> F <="0001" when a ="00"else<br /> "0010"when a ="01"else<br /> "0100" when a ="10"else<br /> "1000";<br />EndArchitecture;<br />24<br />VHDL 360 ©<br />
  27. 27. Encoder4x2 (with-select)<br />F<br />a<br />2<br />4<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity encoder4x2 is<br /> port(a:instd_logic_vector(3downto0);<br /> F:outstd_logic_vector(1downto0));<br />endentity;<br />Architecture behave of encoder4x2 is<br />Begin<br />With a select<br /> F <="00"when"0001",<br />"01"when"0010",<br /> "10"when"0100",<br /> "11"whenothers;<br />EndArchitecture;<br />25<br />VHDL 360 ©<br />
  28. 28. Contacts<br />You can contact us at:<br />http://www.embedded-tips.blogspot.com/<br />VHDL 360 ©<br />26<br />

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