2. VHDL Introduction
V- VHSIC
Very High Speed Integrated Circuit
H- Hardware
D- Description
L- Language
3. History of VHDL
In the 1970’s the initial idea for a Hardware
Description Language was discussed.
But, the VHSIC program wasn’t launched until 1980.
The goal was to create a common language that would
shorten the time from concept to implementation for
hardware design.
4. History of VHDL
In July 1983 the contract was awarded to create VHDL by
the Department of Defense
- Intermetrics
- IBM
- Texas Instruments
August 1985 Version 7.2 was released
5. History of VHDL
It was first in December of 1987 that IEEE standardized
VHDL 1076-1987
VHDL also became an ANSI standard in 1988
In September of 1993 VHDL was re-standardized to
clarify and enhance the language.
In 1998 a committee convened to update the VHDL-1993
standard.
In 2001 IEEE revised the 1993 standard and the new
standard today is 1076-2001
6. VHDL is an International IEEE Standard Specification
Language (IEEE 078-2001) for Describing Digital
Hardware Used by Industry Worldwide
VHDL stands for VHSIC (Very High Speed Integrated
Circuit) Hardware Description Language
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7. VHDL Benefits
1. Public Standard
2. Technology and Process Independent
Include technology via libraries
3. Supports a variety of design methodologies
1. Behavioral modeling
2. Dataflow or RTL (Register Transfer Language)
Modeling
3. Structural or gate level modeling
8. VHDL Benefits (cont)
4. Supports Design Exchange
VHDL Code can run on a variety of systems
5. Supports Design Reuse
Code “objects” can be used in multiple designs
6. Supports Design Hierarchy
Design can be implemented as interconnected
submodules
9. VHDL Benefits (cont)7. Supports Synchronous and Asynchronous Designs
8. Supports Design Simulation
Functional (unit delay)
Timing (“actual” delay)
9. Supports Design Synthesis
Hardware implementation of the design obtained directly from
VHDL code.
10. Supports Design Documentation
Original purpose for VHDL – Department of Defense
VHDL
CODE
a1
1
a2
2
3
a3
4
a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
GND
0
FPLD
VHDL
Synthsize
Software
10. VHDL Design Units
Entity Declaration
Describes external view of the design (e.g. I/O)
Architecture Body (AB)
Describes internal view of the design
Configuration Declaration
Package Declaration
Library Declaration
Package Body
11. VHDL Program Template
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Entity design_name is
port(signal1,signal2,…..:mode type;
signal3,signal4,…..:mode type);
End entity design_name;
Architecture name of entity_name is
internal signal and constant
declarations
Begin
Concurrent statement 1;
Concurrent statement 2;
Concurrent statement 3;
Concurrent statement 4;
End architecture name;
12. Identifiers
May contain A-Z, a-z, 0-9, _
Must start with letter
May not end with _
May not include two consecutive _
VHDL is case insensitive
Sel sel and SEL refer to same object
13. Identifier Examples
A2G
valid
8bit_counter
invalid -- starts with number
_NewValue
invalid -- starts with _
first#
invalid -- illegal character
14. Standard Libraries Include library ieee; before entity declaration.
ieee.std_logic_1164 defines a standard for designers to use in
describing interconnection data types used in VHDL
modeling.
ieee.std_logic_arith provides a set of arithmetic, conversion,
comparison functions for signed, unsigned, std_ulogic,
std_logic, std_logic_vector.
Ieee.std_logic_unsigned provides a set of unsigned
arithmetic, conversion, and comparison functions for
std_logic_vector.
See all available packages at
http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html
15. Entity - All designs are expressed in terms of
entities. An entity is the most basic building block
in a design. The uppermost level of the design is
the top-level entity. If the design is hierarchical,
then the top-level description will have lower-level
descriptions contained in it. These lower-level
descriptions will be lower-level entities contained
in the top-level entity description.
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16. VHDL Syntax – Entity Declaration
Describes I/O of the design. I/O Signals are
called ports.
The syntax is:
Entity design_name is
port(signal1,signal2,…..:mode type;
signal3,signal4,…..:mode type);
End entity design_name;
17. Entity Declaration
• An entity declaration describes the interface of the component. Avoid
using Altera’s primitive names which can be found at
c:/altera/91/quartus/common/help/webhelp/master.htm#
• PORT clause indicates input and output ports.
• An entity can be thought of as a symbol for a component.
18. Port Declaration
• PORT declaration establishes the interface of the object
to the outside world.
• Three parts of the PORT declaration
• Name
• Any identifier that is not a reserved word.
• Mode
• In, Out, Inout, Buffer
• Data type
• Any declared or predefined datatype.
• Sample PORT declaration syntax:
19. VHDL Syntax – Entity Example
Entity my_example is
port( a,b,c: in std_logic;
s: in std_logic_vector(1 downto 0);
e,f: out std_logic;
y: out std_logic_vector(4 downto 0));
end entity my_example;
Maxplus II Block Diagram
20. Architecture - All entities that can be simulated
have an architecture description. The architecture
describes the behavior of the entity. A single entity
can have multiple architectures. One architecture
might be behavioral, while another might be a
structural description of the design.
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21. Configuration - A configuration statement is used
to bind a component instance to an entity-
architecture pair. A configuration can be
considered as a parts list for a design. It describes
which behavior to use for each entity, much like a
parts list describes which part to use for each part
in the design.
P.SIVA NAGENDRA REDDY 21
22. Architecture Body (AB)
The architecture body contains the internal
description of the design entity. The VHDL
specification states that a single design entity can
contain multiple architecture bodies. Each AB can
be used to describe the design using a different level
of abstraction.
23. Architecture Body Syntax
Architecture name of entity_name is
internal signal and constant declarations
Begin
Concurrent statement 1;
Concurrent statement 2;
Concurrent statement 3;
Concurrent statement 4;
End architecture name;
24. Architecture Declaration
• Architecture declarations describe the operation of the
component.
• Many architectures may exist for one entity, but only one may be
active at a time.
• An architecture is similar to a schematic of the component.
25. Modeling Styles
• There are three modeling styles:
• Behavioral (Sequential)
• Data flow
• Structural
28. VHDL Comment Operator
To include a comment in VHDL, use the comment
operator
-- This is a comment
-- This is an example of a comment
y <= 0; -- can occur at any point
29. Signal Assignment Operator
To assign a value to a signal data object in VHDL, we use
the
signal assignment operator
<=
Example:
y <= ‘1’; -- signal y is assigned the value ONE
30. Simple Concurrent Statements
Assignment Operator
Assignment operator <=
Ex: y <= a and b; -- defines a AND gate
For simulation purposes only, you may specify a delay.
Ex: y <= a and b after 10 ns;
This is useful if you want to also use VHDL to generate a known test
waveform or vector. This is known as a “test bench.” However, we
will use Maxplus II to generate test vectors. Note, you cannot
specify a delay for synthesis purposes.
VHDL
Test Bench
VHDL
Design
Output
Vector
Test
Vector
31. Simple Concurrent Statements
Logical Operators
Logical operators
And, or, nand, nor, xor, xnor, not
Operates on std_logic or Boolean data objects
All operators (except for the not operator) require at least two
arguments
Ex: y <= a and b; -- AND gate
32. Simple Concurrent Statements
Logical Operators
Logical operators
Examples y <= a and not b;
Use parenthesis to define order of execution
Ex: y<= (a and b) or c; y <= a and (b or c);
Y
a
b
c
Y
c
b
a
33. Sequential vs Concurrent Statements
• VHDL provides two different types of
execution: sequential and concurrent.
• Different types of execution are useful for
modeling of real hardware.
• Supports various levels of abstraction.
• Sequential statements view hardware from a
“programmer” approach.
• Concurrent statements are order-independent
and asynchronous.
37. Complex Concurrent Statements
With-select-when
Example
---- library statements (not shown)
entity my_test is
port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic_vector(3 downto 0));
end entity my_test;
architecture behavior of my_test is
begin
with s select
y <= a3 when “11”,
a2 when “10”,
a1 when “01”,
a0 when others; -- default condition
end architecture behavior;
40. Sequential Statements
• {Signal, Variable} assignments
• Flow control
• if <condition> then <statments>
[elsif <condition> then <statments>]
else <statements>
end if;
• for <range> loop <statments> end loop;
• while <condition> loop <statments> end loop;
• case <condition> is
when <value> => <statements>;
when <value> => <statements>;
when others => <statements>;
• Wait on <signal> until <expression> for <time>;
41. Data Objects
• There are three types of data objects:
• Signals
• Can be considered as wires in a schematic.
• Can have current value and future values.
• Variables and Constants
• Used to model the behavior of a circuit.
• Used in processes, procedures and functions.
42. Constant Declaration
• A constant can have a single value of a given type.
• A constant’s value cannot be changed during the
simulation.
• Constants declared at the start of an architecture can be
used anywhere in the architecture.
• Constants declared in a process can only be used inside
the specific process.
CONSTANT constant_name : type_name [ : = value];
CONSTANT rise_fall_time : TIME : = 2 ns;
CONSTANT data_bus : INTEGER : = 16;
43. Variable Declaration
• Variables are used for local storage of data.
• Variables are generally not available to multiple
components or processes.
• All variable assignments take place immediately.
• Variables are more convenient than signals for the
storage of (temporary) data.
44. Signal Declaration
• Signals are used for communication between components.
• Signals are declared outside the process.
• Signals can be seen as real, physical signals.
• Some delay must be incurred in a signal assignment.
45. Signal Assignment
• A key difference between variables and signals is the
assignment delay.
48. Sequential Statements
Case -When Statement
Use a CASE-WHEN statement when priority is not needed. All FSMs will be
implemented using Case-when statements.
Syntax is:
Case expression is
when choice_1 =>
sequential statements;
when choice_2 =>
sequential statements;
………….
when choice_n =>
sequential statements;
when others => -- default condition
sequential statements;
end case;
49. FOR – vs WHILE – statement
Syntax
For is considered to be a
combinational circuit by some
synthesis tools. Thus, it cannot
have a wait statement to be
synthesized.
While is considered to be an FSM
by some synthesis tools. Thus, it
needs a wait statement to be
synthesized.
50. WAIT – statement Syntax
• The wait statement causes the suspension of a process statement or
a procedure.
• wait [sensitivity_clause] [condition_clause] [timeout_clause];
• Sensitivity_clause ::= on signal_name
wait on CLOCK;
• Condition_clause ::= until boolean_expression
wait until Clock = ‘1’;
• Timeout_clause ::= for time_expression
wait for 150 ns;
52. Concurrent Process Equivalents
• All concurrent statements correspond to a process
equivalent.
U0: q <= a xor b after 5 ns;
is short hand notation for
U0: process
begin
q <= a xor b after 5 ns;
wait on a, b;
end process;
53. Structural Style
• Circuits can be described like a netlist.
• Components can be customized.
• Large, regular circuits can be created.
54. Structural Statements
• Structural VHDL describes the arrangement
and interconnection of components.
• Behavioral descriptions, on the other hand, define
responses to signals.
• Structural descriptions can show a more
concrete relation between code and physical
hardware.
• Structural descriptions show interconnects at
any level of abstraction.
55. Structural Statements
• The component instantiation is one of the building blocks of
structural descriptions.
• The component instantiation process
requires component declarations and
component instantiation statements.
• Component instantiation declares the
interface of the components used in
the architecture.
• At instantiation, only the interface is visible.
• The internals of the component are hidden.
56. Component Declaration
• The component declaration declares the interface of the
component to the architecture.
• Necessary if the component interface is not declared
elsewhere (package, library).
57. Component Instantiation
• The instantiation statement maps the interface of the
component to other objects in the architecture.
59. Component Libraries
• Component declarations
may be made inside
packages.
• Components do not have to
be declared in the
architecture body
60. Generics
• Generics allow the component to be customized upon
instantiation.
• Generics pass information from the entity to the
architecture.
• Common uses of generics
• Customize timing
• Alter range of subtypes
• Change size of arrays
entity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vector(n-1 doentity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vector(n-1 do
ENTITY adder IS
GENERIC(n: natural :=2);
PORT(
A: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
C: OUT STD_LOGIC;
SUM: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
);
END adder;
entity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vector(n-1 do
61. Technology Modeling
• One use of generics is to alter the timing of a certain component.
• It is possible to indicate a generic timing delay and then specify the
exact delay at instantiation.
• The example above declares the interface to a component named
inv.
• The propagation time for high-to-low and low-to-high transitions
can be specified later.
62. Structural Statements
• The GENERIC MAP is similar to the PORT MAP in that
it maps specific values to generics declared in the
component.
63. Generate Statement
• Structural for-loops: The GENERATE statement
• Some structures in digital hardware are repetitive in nature.
(RAM, ROM, registers, adders, multipliers, …)
• VHDL provides the GENERATE statement to automatically
create regular hardware.
• Any VHDL concurrent statement may be included in a
GENERATE statement, including another GENERATE
statement.
64. Generate Statement Syntax
• All objects created are similar.
• The GENERATE parameter must be discrete and is
undefined outside the GENERATE statement.
66. Operators
Operators can be chained to form complex expressions, e.g. :
Can use parentheses for readability and to control the
association of operators and operands
Defined precedence levels in decreasing order :
Miscellaneous operators -- **, abs, not
Multiplication operators -- *, /, mod, rem
Sign operator -- +, -
Addition operators -- +, -, &
Shift operators -- sll, srl, sla, sra, rol, ror
Relational operators -- =, /=, <, <=, >, >=
Logical operators -- AND, OR, NAND, NOR, XOR, XNOR
res <= a AND NOT(B) OR NOT(a) AND b;
73. Physical
• Time units are the only predefined physical type in VHDL.
• Physical
• Can be user defined range
• Physical type example
74. Array
• Array
• Used to collect one or more elements of a similar type in a
single construct.
• Elements can be any VHDL data type.
75. Record
• Record
• Used to collect one or more elements of different types in a
single construct.
• Elements can be any VHDL data type.
• Elements are accessed through field name.
76. Subtype
• Subtype
• Allows for user defined constraints on a data type.
• May include entire range of base type.
• Assignments that are out of the subtype range result in error.
• Subtype example
77. Natural and Positive Integers
• Integer subtypes:
• Subtype Natural is integer range 0 to integer’high;
• Subtype Positive is integer range 1 to integer’high;
78. Boolean, Bit and Bit_vector
• type Boolean is (false, true);
• type Bit is (‘0’, ‘1’);
• type Bit_vector is array (integer range <>) of bit;
79. Char and String
• type Char is (NUL, SOH, …, DEL);
• 128 chars in VHDL’87
• 256 chars in VHDL’93
• type String is array (positive range <>) of Char;
80. IEEE Predefined data types
• type Std_ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);
• ‘U’ -- Uninitialized
• ‘X’ -- Forcing unknown
• ‘0’ -- Forcing zero
• ‘1’ -- Forcing one
• ‘Z’ -- High impedance
• ‘W’ -- Weak Unknown
• ‘L’ -- Weak Low
• ‘H’ -- Weak High
• ‘-’ -- Don’t care
• type std_logic is resolved std_ulogic;
• type std_logic_vector is array (integer range <>) of std_logic;
81. Assignments
• constant a: integer := 523;
• signal b: bit_vector(11 downto 0);
b <= “000000010010”;
b <= B”000000010010”;
b <= B”0000_0001_0010”;
b <= X”012”;
b <= O”0022”;
82. Functions
Produce a single return value
Called by expressions
Cannot modify the parameters passed to them
Require a RETURN statement
FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT IS
VARIABLE result : BIT; -- variable is local to function
BEGIN
result := (a XOR b);
RETURN result; -- the two functions are equivalent
END add_bits2;
FUNCTION add_bits (a, b : IN BIT) RETURN BIT IS
BEGIN -- functions cannot return multiple values
RETURN (a XOR b);
END add_bits;
90. Functions
Functions must be called by other statements
Parameters use positional association
ARCHITECTURE behavior OF adder IS
BEGIN
PROCESS (enable, x, y)
BEGIN
IF (enable = '1') THEN
result <= add_bits(x, y);
carry <= x AND y;
ELSE
carry, result <= '0';
END PROCESS;
END behavior;
FUNCTION add_bits
(a, b : IN BIT)
