This document discusses sequential circuits and various flip flop circuits. It defines non-clocked and clocked flip flops, and describes positive and negative edge triggering. It provides diagrams, truth tables, and excitation tables for SR, D, JK, and T flip flops. Sequential circuits have memory and their output depends on present and past inputs.

1. SEQUENTIAL CIRCUITS
• Block Diagram
• Difference between non-clocked and clocked flip flop
• Positive edge / negative edge triggered flip flop
• SR flip flop ( Diagram , Truth Table , Excitation Table )
• D flip flop ( Diagram , Truth Table , Excitation Table )
• JK flip flop ( Diagram , Truth Table , Excitation Table )
• T flip flop ( Diagram , Truth Table , Excitation Table )

2. SEQUENTIAL CIRCUITS
• Present output depends on “present and Past inputs”
• Memory is required
• Sequential circuits = combinational circuits + Memory

3. • Non-clocked flip flop :- output can be changed ,
anytime input condition are changed.
• Clocked flip flop :- Effective only when enable Pin is
High/low depends on type of triggering otherwise
Ineffective.
• Positive edge triggering flip flop:- State transition
takes place when clock signal goes from {0 to 1} or {
low to high }
• Negative edge triggering flip flop :- State transition
takes place when clock signal goes from {1 to 0} or
{high to low }

4. SR FLIP FLOP
Truth Table
Excitation Table
Qp – present state
Qn – next state

5. D FLIP FLOP
Truth Table
Excitation Table
Qp – present state
Qn – next state

6. JK FLIP FLOP
Truth Table
Excitation Table
Qp – present state
Qn – next state

7. T FLIP FLOP
Truth Table
Excitation Table
Qp – present state
Qn – next state