Useful for research

1. Gujarat Technological University
Ahmedabad
&
C-DAC, Pune
M.E (Electronics & Communication Engineering)
In
VLSI & Embedded System Design (sem-1)
En No-160930359011

2. Inter-Process Communication using
Pipes in FPGA-based Adaptive
Computing
Presented by
Mayur Shah

3. What is Inter Process Communication ?[1]
 Exchange of data between two or more separate, independent
processes/threads.
 Operating systems provide facilities/resources for inter-process
communications (IPC), such as message queues, semaphores, and
shared memory.
 Distributed computing systems make use of these facilities/resources to
provide application programming interface (API) which allows IPC to
be programmed at a higher level of abstraction. (e.g., send and
receive)
 Distributed computing requires information to be exchanged among
independent processes.

4. Figure Of Inter Process Communication
Process 1 Process 2
data
sender receiver

5. IPC Mechanisms
 Signals
 Pipes
 FIFOs
 Message Queue
 Shared memory

6. Purposes for IPC
 Data Transfer
 Sharing Data
 Event notification
 Resource Sharing and Synchronization
 Process Control

7. What is pipe?
Pipe which allow transfer data between processes in First in-
First-out manner.
A pipe is usually realized in memory.
Pipe operations are memory operations.

8. Create a Pipeline
 Sometimes useful to connect a set of processes in a pipeline.
Process
c
Process
D
PipePipe
Process A writes to pipe AB, Process B reads from AB and
writes to BC
Process C reads from BC and writes to CD …..

9. Field Programmable Gate Array
 It is primarily a semiconductor device that can be configured by the
user (customer or designer) after the manufacturing process has been
completed
 The term "field-programmable" means the device is programmed by
the customer, not the manufacturer.
 Can be programmed using a logic circuit diagram or source code in
VHDL or Verilog.
 It offers partial re-configuration of a portion of design.

10. General Figure of FPGA
 Logic blocks
 to implement combinational
and sequential logic
 Interconnect
 wires to connect inputs and
outputs to logic blocks
 I/O blocks
 special logic blocks at periphery
of device for external connections

11. Adaptive Computing
Adaptive computing refers to the capability of a computing system
to adapt one or more of its properties (e.g. performance) during
runtime.
There are diverse reasons of why it is advantageous for a computing
system to adapt during runtime and there are various enabling
techniques and paradigms that allow a computing system to perform
such an adaptation.

12. Now We starting our main topic ………….
Inter-Process Communication using Pipes in FPGA-based
Adaptive Computing

13. Abstract:-
In FPGA-based adaptive computing, Inter-Process Communications
(IPC) are required to exchange information among hardware processes
which time multiplex the resources in a same reconfigurable region.

14.  Adaptive computing based on FPGA Partial Reconfiguration (PR)
technologie tailors various computation algorithmes to ambient
conditions during system run-time. It intelligently manages on-chip
computing resources and improves their utilization efficiency .
 In contrast to conventional static configuration of FPGAs, PR
provides the technical support for changing only a particular section
of an FPGA design, while the remaining system is still in operation.
Analogous to software multiprogramming on CPUs, the PR
technology enables multitasking on limited FPGA resources by
dynamically configuring or unloading processing modules according
to computation requirements. In this context, each processing module
is treated as a hardware process for one specific algorithm.
Now Introduction

15. IPC QUEING MODEL
Static Process Model
Pipes and FIFOs (Also called named pipes. We use pipe as the general name.)
are a basic IPC mechanism provided in all flavors of Unix OSes. They are best
suited to implement producer-consumer interactions among processes.
A pipe is a unidirectional channel: All data written by a process to the pipe is
routed by the OS kernel to another process which can thus read it .In FPGA-based
designs, hardware pipes behave in an analogous manner as the software ones in
Oses.

17. (Figure 1) shows consecutive pipe communications between algorithm
modules. Conventionally all algorithm processors or algorithm steps are
statically placed on the FPGA fabric. They work in parallel to process
their respective input data streams, possibly generate output results, and
pass IPC information to the next computation stage. In this model,
intermediate pipes with buffering capability decouple and coordinate
producers and consumers, if they do not generate and consume data at the
same pace.

18. Re-configurable Process Model

19. In adaptive computing scenarios in which multiple algorithm processors or
algorithm steps timeshare the same resources in one PR Region (PRR), pipes can
be used to bridge the communication of two modules activated at different time.
In Figure 2, a reconfigurable design is demonstrated with the same dataflow as
the static algorithm placement shown in Figure 1: Algorithm modules are
sequentially loaded into the PR region for a period of time. They read and
consume data from the previous-stage pipe, and store the generated inter-module
information in the current-stage pipe for next-stage computation. For example
after activated, algorithm A1 reads IPC packets of A0 from pipe0, and
passinformation to A2 via pipe1.

20. • Pipes can be implemented with
• BRAM on Xilinx Virtex-4 FPGA
• External DDR memory
M. Liu, Z. Lu, W. Kuehn, S. Yang, and A. Jantsch,
"A Reconfigurable Design Framework for FPGA
Adaptive Computing“, ReConFig’09.
HARDWARE IMPLEMENTATION

21. DDR_pipe:
The complete system architecture
FPGA adaptive computing [1]
• Embedded microprocessor
(scheduler)
• Memory (partial bitstream storage)
• HWICAP for PR

22. Conclusion
The latency of IPC packets is expected to be reduced with
more intelligent mechanisms, and to be properly coordinated
with throughput requirements in realtime applications.

23. Reference
.1. ipc using pipe in fpga adtive computing
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2. ipc
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3. ipc using pipe
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3.2
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c2I
4. adptive computing
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