During the CXL Forum at OCP Global Summit, Intel engineer Bhushan Chitlur explains how active memory works and provides and overview of Intel's solution for disaggregated memory tiering.

1. CXL Enabled Heterogeneous Active
Memory Tiering
Bhushan Chitlur, Sr Principal Engineer

2. Exploring Heterogenous Memory Tiers
to Improve Performance and Lower
TCO
CXL Enabled Heterogeneous Active Memory
Tiering

3. Application’s use less memory than what is allocated to them
Background : The Datacenter Memory
Conundrum
Low Perf,
Low Cost,
High Capacity
Improve TCO by effective use of heterogenous Memory Tiers
Hot Pages
Cold
Pages
Warm
Pages
Best Perf,
High Cost,
Low Capacity
Credit - https://www.pdl.cmu.edu/ftp/NVM/tmo_asplos22.pdf
Cost of memory, compressed memory, and SSDs as a percentage of
compute infrastructure across hardware generations

4. Embracing Heterogeneity and Disaggregated Memory
Topologies
Centralized Disaggregated Memory
(Pooling)
Heterogenous Disaggregated Memory
(Tiering)
Pooled Memory Controller
DDR
CXL
Acclerator
Node
DDR DDR DDR
CXL
Compute
Node
CXL
Compute
Node
CXL
Compute
Node
Memory Tier1
(Local)
Memory Tier2
(Remote,
Shared)
DDR DDR DDR DDR
Compute Node
Compute Node A (CPU)
DDR
CXL Disaggregated Mem Cntlr
DDR HBM Mem
Semantic SSD
Memory
node
DDR, NVMe
CXL
GPU/Accel
PCIe/CXL
Remote
Compute node
DDR, NVMe
Memory Tier1
(Local)
Memory Tier2
(Local)
Memory Tier3
(Remote, Shared)
COTS Fabric (Eg Ethernet)

5. Disaggregated Mem Controller
DDR HBM SSD
Memory Side
Cache
Cacheline to Block
NVMe Host Controller
SSD SSD
CXL Endpoint (Type3, Type2)
Remote Memory
Access
(Block or Cacheline)
Network
(Remote requests Tx/Rx)
Low Latency
Network Protocol
Near Memory
Compute
Accelerators
Memory Side Technologies
Active Memory Tiering and
Accelerator Technologies
Hot/Cold Page Detect
Compression/
Decompression
Encryption/
Decryption
Data Deduplication
Data Replication
Host Connectivity Options
Host
VMM OS Device Driver Application
Possible Host SW
Touchpoints
CXL SW
HW
Elements of Active Memory Tiering
Shared capacity Expansion TCO optimized
capacity Expansion
Transparent to
Host SW
Visible to Host
SW

6. Intel’s Solution for Heterogeneous Disaggregated Memory
(Tiering)
Heterogenous Disaggregated Memory
Compute Node
Compute Node A (CPU)
DDR
CXL Disaggregated Mem Cntlr
DDR HBM Mem
Semantic SSD
Memory
node
DDR, NVMe
CXL
GPU/Accel
PCIe/CXL
Remote
Compute node
DDR, NVMe
Memory Tier1
(Local)
Memory Tier2
(Local)
Memory Tier3
(Remote, Shared)
COTS Fabric (Eg Ethernet)
vme SSD support is through 3rd party vendor

7. CXL-enabled Ecosystem
Solutions with Intel® Agilex® 7
Intel Agilex 7 FPGA I-Series Devkit
Bittware IA-440i
Inspur F26A
Reflexces XpressSX AGI-
FH400G
FlySlice FA927A
Terasic Mercury A2700
Database
Analytics
Memory
Tiering/
Pooling
Computationa
l Memory
Disaggregate
d Memory
Custom
Development
Fabric

8. • The time is right to explore Heterogenous memory tiering
• FPGAs are very well suited to support the varied requirements of active tiering
• Portfolio of technologies required for active tiering are available to build scalable
solutions
• Check out the Demo “Improve System Performance by Offloading Memory-Intensive
Kernel Features to CXL Type-2 Device” in Experience Center
Where to find additional information
• Intel Agilex® 7 FPGA I-Series FPGA Development Kit
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html
• Intel CXL IP
https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-
protocols/cxl-ip.html
• Intel’s CXL products and solutions, contact, Pekon Gupta (pekon.gupta@intel.com)
Call to Action

9. Thank you!

10. Open Discussion

11. [TRACK NAME]
• Sustainability
• Special Focus: Deployments
• Special Focus: Optical Connectivity
for AI Clusters
• Special Focus: Quantum
• Special Focus: Sustainable
Computational Infrastructure for AI
• TAP (Time Appliances Project)
• CE (Cooling Environments)
• Data Center Facilities (DCF) and Rack &
Power
• Edge
• Hardware Management with DC-SCM
• Networking
• Open System Firmware (OSF)
• Security
• Server
• Server: Composable Memory Systems
• Server: Open Chiplet Economy
• Storage

12. SERVER
NETWORKING STORAGE
DC FACILITIES HW MGMT
SECURITY
OPEN SYS FW
TIME
APPLIANCES
COOLING ENV
Please use the appropriate icon representing the Project Group.
SUSTAINABILI
TY
RACK &
POWER
TELCO
AI OPTICS
OPEN
CHIPLET
CMS
DEPLOYMENT
S

13. Click here to review OCP Trademark
Guidelines.
Please use the appropriate icon representing the Regional Project Group.