This document describes a study comparing the power dissipation of a 2:1 multiplexer designed using static CMOS logic versus an adiabatic logic style called 2PADCL (Two Phase Adiabatic Dynamic CMOS Logic). The 2:1 multiplexer was designed and simulated using both logic styles. Simulation results found that the multiplexer using 2PADCL adiabatic logic consumed significantly less power than the static CMOS implementation, with power savings of up to 65% observed under certain operating conditions. Adiabatic logic styles like 2PADCL achieve lower power by slowly charging and discharging circuit nodes and recycling stored charge, rather than abruptly switching nodes from 0V to the supply voltage.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that proposes a novel seven-level inverter for grid-connected photovoltaic systems. The inverter uses a hybrid cascaded configuration with a novel pulse width modulation technique to generate seven output voltage levels from the DC supply. Simulation results using MATLAB/Simulink are presented to validate the operation of the proposed inverter. The inverter is capable of improving power quality by reducing harmonic distortion compared to traditional two-level inverters.
This paper proposes a non-isolated soft-switching bidirectional dc/dc converter for interfacing energy storage in DC microgrid. The proposed converter employs a half-bridge boost converter at input port followed by a LCC resonant tank to assist in soft-switching of switches and diodes, and finally a voltage doubler circuit at the output port to enhance the voltage gain by two times. The LCC resonant circuit also adds a suitable voltage gain to the converter. Therefore, overall high voltage gain of the converter is obtained without a transformer or large number of multiplier circuit. For operation in buck mode, the high side voltage is divided by half with capacitive divider to gain higher step-down ratio. The converter is operated at high frequency to obtain low output voltage ripple, reduced magnetics and filters. Zero voltage turn-on is achieved for all switches and zero current turn-on and turn-off is achieved for all diodes in both modes i.e., buck/boost operation. Voltage stress across switches and diode is clamped naturally without external snubber circuit. An experimental prototype has been designed, built and tested in the laboratory to verify the performance of the proposed converter.
IRJET - A Zero Voltage Switching Pulse Width Modulated Multilevel Buck ConverterIRJET Journal
This document presents a new five-level zero voltage switching pulse width modulated multilevel buck converter. The proposed converter uses a multilevel topology to reduce voltage stresses on switches without adding extra voltage. It achieves zero voltage switching for all switches by utilizing active clamping and circulating reactive energy throughout the converter. Simulations in MATLAB were used to verify the performance of the proposed converter. The converter design and operating principles are explained, including modes of operation, component sizing equations, and simulation details.
This document summarizes a research paper that proposes combining a unified power quality conditioner (UPQC) with a photovoltaic (PV) array. The UPQC uses series and shunt inverters connected back-to-back to compensate for both voltage and current-related power quality issues in both grid-connected and islanding modes. By connecting the PV array to the UPQC's DC link, the system can inject active power from the PV to the grid during voltage interruptions or islanding events. Control strategies are described for operating the shunt and series inverters to compensate for harmonics, reactive power, and voltage disturbances while also injecting PV power as needed. Simulation results demonstrate the effectiveness of the
This paper proposes two new simplified cascade multiphase DC-DC boost power converters with high voltage-gain and low ripple. All simplifications reduce the number of active switching devices from 2N into N, where N is the phase number. The first simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (2N+1). The second simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (3N+1). The second simplification needs inductors with smaller current rating than the first simplification. The expressions of output voltage as a function of load current are derived by taking into account the voltage drops across the inductors and switching power devices. Simulated and experimental results are included to show the basic performance of the proposed cascade multiphase DC-DC boost power converters.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that proposes a novel seven-level inverter for grid-connected photovoltaic systems. The inverter uses a hybrid cascaded configuration with a novel pulse width modulation technique to generate seven output voltage levels from the DC supply. Simulation results using MATLAB/Simulink are presented to validate the operation of the proposed inverter. The inverter is capable of improving power quality by reducing harmonic distortion compared to traditional two-level inverters.
This paper proposes a non-isolated soft-switching bidirectional dc/dc converter for interfacing energy storage in DC microgrid. The proposed converter employs a half-bridge boost converter at input port followed by a LCC resonant tank to assist in soft-switching of switches and diodes, and finally a voltage doubler circuit at the output port to enhance the voltage gain by two times. The LCC resonant circuit also adds a suitable voltage gain to the converter. Therefore, overall high voltage gain of the converter is obtained without a transformer or large number of multiplier circuit. For operation in buck mode, the high side voltage is divided by half with capacitive divider to gain higher step-down ratio. The converter is operated at high frequency to obtain low output voltage ripple, reduced magnetics and filters. Zero voltage turn-on is achieved for all switches and zero current turn-on and turn-off is achieved for all diodes in both modes i.e., buck/boost operation. Voltage stress across switches and diode is clamped naturally without external snubber circuit. An experimental prototype has been designed, built and tested in the laboratory to verify the performance of the proposed converter.
IRJET - A Zero Voltage Switching Pulse Width Modulated Multilevel Buck ConverterIRJET Journal
This document presents a new five-level zero voltage switching pulse width modulated multilevel buck converter. The proposed converter uses a multilevel topology to reduce voltage stresses on switches without adding extra voltage. It achieves zero voltage switching for all switches by utilizing active clamping and circulating reactive energy throughout the converter. Simulations in MATLAB were used to verify the performance of the proposed converter. The converter design and operating principles are explained, including modes of operation, component sizing equations, and simulation details.
This document summarizes a research paper that proposes combining a unified power quality conditioner (UPQC) with a photovoltaic (PV) array. The UPQC uses series and shunt inverters connected back-to-back to compensate for both voltage and current-related power quality issues in both grid-connected and islanding modes. By connecting the PV array to the UPQC's DC link, the system can inject active power from the PV to the grid during voltage interruptions or islanding events. Control strategies are described for operating the shunt and series inverters to compensate for harmonics, reactive power, and voltage disturbances while also injecting PV power as needed. Simulation results demonstrate the effectiveness of the
This paper proposes two new simplified cascade multiphase DC-DC boost power converters with high voltage-gain and low ripple. All simplifications reduce the number of active switching devices from 2N into N, where N is the phase number. The first simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (2N+1). The second simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (3N+1). The second simplification needs inductors with smaller current rating than the first simplification. The expressions of output voltage as a function of load current are derived by taking into account the voltage drops across the inductors and switching power devices. Simulated and experimental results are included to show the basic performance of the proposed cascade multiphase DC-DC boost power converters.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Analysis of a bidirectional isolated dc – dc converter for hybrid systemIAEME Publication
This document summarizes a research paper that analyzes a bidirectional isolated DC-DC converter for hybrid systems. The proposed converter uses a combination of a half-bridge and full-bridge circuit with two transformers to allow bidirectional power flow between two DC buses. It can be controlled using both phase shift modulation and duty cycle modulation to regulate power flow flexibly. Simulation results show it effectively reduces losses over a wide input range. A prototype was also built to validate the design, using a solar panel, supercapacitor and DC motor.
High Voltage Gain Boost Converter for Micro source Power Conversion systemIDES Editor
The document presents a new high voltage gain boost converter design that uses a coupled inductor and voltage lift technique. Key features of the proposed converter include:
1) It can achieve a high voltage gain while operating at a duty ratio close to 0.65, allowing continuous conduction mode operation.
2) The coupled inductor design recycles energy stored in the leakage inductance, increasing efficiency by clamping voltage on the active switch.
3) A 250W prototype was built with 25V input and 240V output to demonstrate the converter's performance operating at 50kHz.
Steady-state analysis and derivations of voltage gain formulas are provided to explain the operating principles and performance advantages of the proposed
1) The document presents a half bridge converter topology for battery charging applications.
2) A single stage half bridge converter is proposed that provides DC voltage regulation and power factor correction with only one controller.
3) The converter operation depends on whether the inductor is operating in discontinuous or continuous conduction mode, with discontinuous mode avoiding high voltage stress at light loads.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes a research paper that proposes a soft-switching boost converter with an auxiliary resonant circuit (SARC) for improving the efficiency of photovoltaic (PV) energy conversion systems. The converter aims to boost the lower output voltage of solar cells to a useful voltage for loads. Simulation and experimental results confirm the converter's operational principles and soft-switching performance. Analysis shows that through SARC, all switching devices achieve zero-voltage and zero-current switching, reducing switching losses compared to conventional hard-switching converters. The converter design targets a 700W PV module, and testing with a PV simulator validates effective maximum power point tracking control.
The document summarizes a study on using a high step-up zeta converter fed by a solar PV panel for a DC drive application. Key points:
- A zeta converter with a coupled inductor and capacitor multiplier is used to achieve high step-up voltage conversion from a 15-40V solar PV panel input.
- Steady-state analysis of the converter in continuous conduction mode shows it can achieve a voltage gain of (1+n) where n is the turns ratio of the coupled inductor.
- Simulation results using Matlab/Simulink validate the converter design and show it can provide the required output voltage for a DC drive from the solar PV input with high efficiency for resist
High-Power Bidirectional Dual Active Bridge and Double Dual Active Bridge DC-...IRJET Journal
The document summarizes a high-power bidirectional dual active bridge DC-DC converter. It discusses how dual active bridge converters use two full-bridge circuits connected by a transformer and inductor to enable bidirectional power flow and control power transfer between two DC sources by phase shifting square wave voltages generated by each bridge. Zero-voltage switching is enabled through resonance of the inductor and snubber capacitor, improving efficiency. The dual active bridge converter is well-suited for applications requiring high power density and bidirectional power flow such as balancing energy storage systems in aircraft.
Design of Soft Switching Converter with Digital Signal Processor Based MPPT f...IDES Editor
This paper is based on the design of soft
switching converter (ZVS-ZCS resonant action) with
digital signal processor (DSP) based maximum power
point tracking (MPPT) algorithm for solar hybrid
applications. The converter aims to get the regulated
output voltage from several power sources like wind
turbines, photovoltaic (PV) arrays and energy from these
sources are simultaneously transferred to the load. The
input stage circuits for different energy sources are put in
parallel using a coupled inductor and the converter to
prevent power coupling effect it acts in interleaving
operating mode. As the buck/boost converter input range
is restricted interleaved ZVS-ZCS converter with low
switching loss and conduction loss and efficiency of more
than 92% can be easily achieved. DSP based MPPT
algorithm adjusts solar array voltage (equal to battery
voltage) with a digital compensator technique and
discrete PI control to track the MPP with high tracking
efficiency. Hence the proposed work gives a novel idea in
the modern hybrid energy system.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A dual active bridge dc-dc converter for application in a smart user networkAlessandro Burgio
Abstract—The paper presents a dual active bridge converter, i.e. an isolated bidirectional DC/DC converter composed of two full-bridge DC/AC converters and an isolation high frequency (HF) transformer, useful for application in a DC-powered microgrid. The dual active bridge converter connects a battery energy storage system to a DC bus so to provide a high level of reliability and resilience to grid disturbances. In particular, the proposed converter ensures a stable DC bus voltage when the microgrid is operated in islanded mode. Numerical results demonstrate the good dynamic response of the converter under transient condition of
A Two-Input Dual Active Bridge Converter for a Smart User Network Using Integ...Alessandro Burgio
The current on the low voltage side of the high
frequency transformer of a dual active bridge converter is
subject to rapid rising and falling edge; in designing the
converter, the peak current is a key factor to achieve robustness
and reliability. To limit the peak current, the adoption of a
further inductor in series with the transformer is a feasible
solution. In this paper the authors propose a novel topology for a
DAB converter useful to deeply reduce the peak current. The
authors also present a 1kW prototype of a DAB converter
implementing the proposed topology and built using integrated
power modules in place of discrete ones. The results of a
laboratory test clearly demonstrated the good dynamic response
of the DAB converter considering a deep step change in power
balancing.
Low Current Ripple, High Efficiency Boost Converter with Voltage MultiplierIJMTST Journal
An innovative high voltage-gain boost converter, which is made for home inverters contains the combination
of switched capacitors and coupled inductors made a voltage multiplier, which is used to increase the output
gain of a traditional converter abnormally without using an excessive switching frequency. The setup not only
maximizes the efficiency but also eliminates input current ripple almost, which deduces conduction losses
and current stress of switches causes to greater extension of input source lifetime. In addition, due to the
lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large voltage
spikes across the main switches are alleviated, and the efficiency is improved. Even the low voltage stress
makes the low-voltage-rated MOSFETs be embraced for reductions conduction losses and expense.
Ultimately, the prototype circuit with 24-V input voltage, 230-V output, and 1000-W output power is operated
to verify its performance. The greatest effectiveness is 97.1 %.
This document presents a high-efficiency interleaved active clamped DC-DC converter with a fuel cell for high voltage applications. Two current fed DC-DC converters are interleaved by connecting their inputs in parallel and outputs in series to reduce current ripples in the fuel cell and regulate output voltage ripples. An active clamping circuit is used to absorb switch turn-off voltage spikes, allowing low voltage devices with low resistance to be used. Voltage doubler circuits double the output voltage with a smaller transformer turns ratio and increased flexibility. Simulation in MATLAB verifies the proposed design's accuracy. The converter shows benefits including reduced current ripples, increased power handling, and improved voltage regulation for high power fuel cell systems.
Control of a Modular Multilevel DC/DC Converter for Regenerative ApplicationsIRJET Journal
This document describes and compares different converter topologies for interfacing supercapacitors to a DC bus, including for regenerative applications. It finds that a modular multilevel DC/DC converter (MMC) has advantages over cascaded buck and boost converters in terms of reduced weight and volume of inductance. When using phase shifting modulation, the MMC can balance supercapacitor voltages through control of the output current. Simulation results show the MMC achieves lower current ripples and faster response times compared to the other topologies. Control methods are presented to regulate the output current and balance the supercapacitor voltages in the MMC.
Hybrid Two Quasi Z-Source Converter for Photovoltaic ApplicationPremier Publishers
This paper presents a Hybrid Two Quasi Z-source (HTQZS) DC-DC converter for photovoltaic applications. These are mainly employed to full fill the demand of the voltage boost in photovoltaic applications from the lower value voltage. The traditional z source networks have some limitations in voltage boosting, so the modified z source means the different combination of the LC components is combined to form the hybrid quasi z source networks. This hybrid two quasi z source dc-dc converters can be applied for the dc-ac, ac-ac, and ac-dc conversions. The structure of the proposed converter is simpler. This converter adds the benefits to the traditional z source converter. This converter draws the continuous input current. The converter simulated is the combination of two different quasi z source networks. This converter uses the duty cycle less than the traditional z source network and gives the more gain than that. PV panel used as source to converter and then the output is inverted and step up.
Solar Based Stand Alone High Performance Interleaved Boost Converter with Zvs...IOSR Journals
This document summarizes a research paper on a solar-based interleaved boost converter with zero-voltage switching and zero-current switching. The converter uses two boost converters connected in parallel with a phase shift to reduce ripple and improve efficiency. Soft-switching techniques are used to reduce switching losses. Simulation results show the converter maintains a constant output voltage while the induction motor output varies with time, and PWM signals control the switches. The converter achieves a power factor of 0.93 and performs efficiently for power conversion from solar panels.
AC-AC RESONANT BOOST CONVERTER FOR INDUCTION HEATING WITH CLOSED LOOP CONTROLpaperpublications3
Abstract: Induction heating is a promising technology which requires power electronics component. It is a heating method for electrically conductive materials using the heat generated by the eddy currents, by means of a varying magnetic field. The power converter feature a half-bridge resonant converter operating with a switching frequency between 50kHz and 120kHz to improve efficiency, accurate smooth power control while assuring the safety of power devices. Power requirement of an induction heating system can be varied during the heating process. A closed loop control is required to have a smooth control over the power. This work presents the analysis of an AC-AC resonant converter with closed loop which is based on the half-bridge series resonant inverter for induction heating. Only two diodes are used in this topology to rectify the mains voltage. The converter can be operated with zero-voltage switching during both switch-on and switch-of transitions. In conventional AC-AC resonant boost converter output power varies according to input voltage. In the designed system a closed loop is implemented in order to keep output power at desired value irrespective of supply voltage. The circuit is simulated using PSIM.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper on a bidirectional DC-DC converter with a Z-source network. The proposed converter aims to increase the output voltage level and regulation range compared to traditional bidirectional converters. It uses a fully bridge symmetrical circuit configuration with voltage and current sources. Simulation results using MATLAB show the converter can reduce current stress and improve efficiency for applications in hybrid electric vehicles and renewable energy systems. Key aspects analyzed include the converter's operating principles, voltage regulation model, and simulation circuit and results demonstrating operation in forward and reverse modes.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
This document summarizes a research paper that proposes a dual-input single-stage inverter topology for standalone solar photovoltaic systems to provide electricity in rural areas without access to the electric grid. The proposed system uses a maximum power point tracking algorithm and boost converter to increase the low voltage from the solar panels. It then uses a single-stage boost inverter with sinusoidal pulse width modulation to efficiently convert the solar DC power to high-quality AC power for loads without additional filters or protections. Simulation and experimental results showed the system could boost input voltages and produce 230V AC output for rural electrification with reduced components compared to traditional two-stage inverter designs.
One person with passion can be better than many people who are just interested. The document discusses how sharing experiences with friends at Lincoln Center expanded their horizons and was a source of inspiration, showing how individuals who expand each other's horizons strengthen their community. It also talks about learning about a new culture through dance and becoming part of a dance community.
Analysis of a bidirectional isolated dc – dc converter for hybrid systemIAEME Publication
This document summarizes a research paper that analyzes a bidirectional isolated DC-DC converter for hybrid systems. The proposed converter uses a combination of a half-bridge and full-bridge circuit with two transformers to allow bidirectional power flow between two DC buses. It can be controlled using both phase shift modulation and duty cycle modulation to regulate power flow flexibly. Simulation results show it effectively reduces losses over a wide input range. A prototype was also built to validate the design, using a solar panel, supercapacitor and DC motor.
High Voltage Gain Boost Converter for Micro source Power Conversion systemIDES Editor
The document presents a new high voltage gain boost converter design that uses a coupled inductor and voltage lift technique. Key features of the proposed converter include:
1) It can achieve a high voltage gain while operating at a duty ratio close to 0.65, allowing continuous conduction mode operation.
2) The coupled inductor design recycles energy stored in the leakage inductance, increasing efficiency by clamping voltage on the active switch.
3) A 250W prototype was built with 25V input and 240V output to demonstrate the converter's performance operating at 50kHz.
Steady-state analysis and derivations of voltage gain formulas are provided to explain the operating principles and performance advantages of the proposed
1) The document presents a half bridge converter topology for battery charging applications.
2) A single stage half bridge converter is proposed that provides DC voltage regulation and power factor correction with only one controller.
3) The converter operation depends on whether the inductor is operating in discontinuous or continuous conduction mode, with discontinuous mode avoiding high voltage stress at light loads.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes a research paper that proposes a soft-switching boost converter with an auxiliary resonant circuit (SARC) for improving the efficiency of photovoltaic (PV) energy conversion systems. The converter aims to boost the lower output voltage of solar cells to a useful voltage for loads. Simulation and experimental results confirm the converter's operational principles and soft-switching performance. Analysis shows that through SARC, all switching devices achieve zero-voltage and zero-current switching, reducing switching losses compared to conventional hard-switching converters. The converter design targets a 700W PV module, and testing with a PV simulator validates effective maximum power point tracking control.
The document summarizes a study on using a high step-up zeta converter fed by a solar PV panel for a DC drive application. Key points:
- A zeta converter with a coupled inductor and capacitor multiplier is used to achieve high step-up voltage conversion from a 15-40V solar PV panel input.
- Steady-state analysis of the converter in continuous conduction mode shows it can achieve a voltage gain of (1+n) where n is the turns ratio of the coupled inductor.
- Simulation results using Matlab/Simulink validate the converter design and show it can provide the required output voltage for a DC drive from the solar PV input with high efficiency for resist
High-Power Bidirectional Dual Active Bridge and Double Dual Active Bridge DC-...IRJET Journal
The document summarizes a high-power bidirectional dual active bridge DC-DC converter. It discusses how dual active bridge converters use two full-bridge circuits connected by a transformer and inductor to enable bidirectional power flow and control power transfer between two DC sources by phase shifting square wave voltages generated by each bridge. Zero-voltage switching is enabled through resonance of the inductor and snubber capacitor, improving efficiency. The dual active bridge converter is well-suited for applications requiring high power density and bidirectional power flow such as balancing energy storage systems in aircraft.
Design of Soft Switching Converter with Digital Signal Processor Based MPPT f...IDES Editor
This paper is based on the design of soft
switching converter (ZVS-ZCS resonant action) with
digital signal processor (DSP) based maximum power
point tracking (MPPT) algorithm for solar hybrid
applications. The converter aims to get the regulated
output voltage from several power sources like wind
turbines, photovoltaic (PV) arrays and energy from these
sources are simultaneously transferred to the load. The
input stage circuits for different energy sources are put in
parallel using a coupled inductor and the converter to
prevent power coupling effect it acts in interleaving
operating mode. As the buck/boost converter input range
is restricted interleaved ZVS-ZCS converter with low
switching loss and conduction loss and efficiency of more
than 92% can be easily achieved. DSP based MPPT
algorithm adjusts solar array voltage (equal to battery
voltage) with a digital compensator technique and
discrete PI control to track the MPP with high tracking
efficiency. Hence the proposed work gives a novel idea in
the modern hybrid energy system.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A dual active bridge dc-dc converter for application in a smart user networkAlessandro Burgio
Abstract—The paper presents a dual active bridge converter, i.e. an isolated bidirectional DC/DC converter composed of two full-bridge DC/AC converters and an isolation high frequency (HF) transformer, useful for application in a DC-powered microgrid. The dual active bridge converter connects a battery energy storage system to a DC bus so to provide a high level of reliability and resilience to grid disturbances. In particular, the proposed converter ensures a stable DC bus voltage when the microgrid is operated in islanded mode. Numerical results demonstrate the good dynamic response of the converter under transient condition of
A Two-Input Dual Active Bridge Converter for a Smart User Network Using Integ...Alessandro Burgio
The current on the low voltage side of the high
frequency transformer of a dual active bridge converter is
subject to rapid rising and falling edge; in designing the
converter, the peak current is a key factor to achieve robustness
and reliability. To limit the peak current, the adoption of a
further inductor in series with the transformer is a feasible
solution. In this paper the authors propose a novel topology for a
DAB converter useful to deeply reduce the peak current. The
authors also present a 1kW prototype of a DAB converter
implementing the proposed topology and built using integrated
power modules in place of discrete ones. The results of a
laboratory test clearly demonstrated the good dynamic response
of the DAB converter considering a deep step change in power
balancing.
Low Current Ripple, High Efficiency Boost Converter with Voltage MultiplierIJMTST Journal
An innovative high voltage-gain boost converter, which is made for home inverters contains the combination
of switched capacitors and coupled inductors made a voltage multiplier, which is used to increase the output
gain of a traditional converter abnormally without using an excessive switching frequency. The setup not only
maximizes the efficiency but also eliminates input current ripple almost, which deduces conduction losses
and current stress of switches causes to greater extension of input source lifetime. In addition, due to the
lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large voltage
spikes across the main switches are alleviated, and the efficiency is improved. Even the low voltage stress
makes the low-voltage-rated MOSFETs be embraced for reductions conduction losses and expense.
Ultimately, the prototype circuit with 24-V input voltage, 230-V output, and 1000-W output power is operated
to verify its performance. The greatest effectiveness is 97.1 %.
This document presents a high-efficiency interleaved active clamped DC-DC converter with a fuel cell for high voltage applications. Two current fed DC-DC converters are interleaved by connecting their inputs in parallel and outputs in series to reduce current ripples in the fuel cell and regulate output voltage ripples. An active clamping circuit is used to absorb switch turn-off voltage spikes, allowing low voltage devices with low resistance to be used. Voltage doubler circuits double the output voltage with a smaller transformer turns ratio and increased flexibility. Simulation in MATLAB verifies the proposed design's accuracy. The converter shows benefits including reduced current ripples, increased power handling, and improved voltage regulation for high power fuel cell systems.
Control of a Modular Multilevel DC/DC Converter for Regenerative ApplicationsIRJET Journal
This document describes and compares different converter topologies for interfacing supercapacitors to a DC bus, including for regenerative applications. It finds that a modular multilevel DC/DC converter (MMC) has advantages over cascaded buck and boost converters in terms of reduced weight and volume of inductance. When using phase shifting modulation, the MMC can balance supercapacitor voltages through control of the output current. Simulation results show the MMC achieves lower current ripples and faster response times compared to the other topologies. Control methods are presented to regulate the output current and balance the supercapacitor voltages in the MMC.
Hybrid Two Quasi Z-Source Converter for Photovoltaic ApplicationPremier Publishers
This paper presents a Hybrid Two Quasi Z-source (HTQZS) DC-DC converter for photovoltaic applications. These are mainly employed to full fill the demand of the voltage boost in photovoltaic applications from the lower value voltage. The traditional z source networks have some limitations in voltage boosting, so the modified z source means the different combination of the LC components is combined to form the hybrid quasi z source networks. This hybrid two quasi z source dc-dc converters can be applied for the dc-ac, ac-ac, and ac-dc conversions. The structure of the proposed converter is simpler. This converter adds the benefits to the traditional z source converter. This converter draws the continuous input current. The converter simulated is the combination of two different quasi z source networks. This converter uses the duty cycle less than the traditional z source network and gives the more gain than that. PV panel used as source to converter and then the output is inverted and step up.
Solar Based Stand Alone High Performance Interleaved Boost Converter with Zvs...IOSR Journals
This document summarizes a research paper on a solar-based interleaved boost converter with zero-voltage switching and zero-current switching. The converter uses two boost converters connected in parallel with a phase shift to reduce ripple and improve efficiency. Soft-switching techniques are used to reduce switching losses. Simulation results show the converter maintains a constant output voltage while the induction motor output varies with time, and PWM signals control the switches. The converter achieves a power factor of 0.93 and performs efficiently for power conversion from solar panels.
AC-AC RESONANT BOOST CONVERTER FOR INDUCTION HEATING WITH CLOSED LOOP CONTROLpaperpublications3
Abstract: Induction heating is a promising technology which requires power electronics component. It is a heating method for electrically conductive materials using the heat generated by the eddy currents, by means of a varying magnetic field. The power converter feature a half-bridge resonant converter operating with a switching frequency between 50kHz and 120kHz to improve efficiency, accurate smooth power control while assuring the safety of power devices. Power requirement of an induction heating system can be varied during the heating process. A closed loop control is required to have a smooth control over the power. This work presents the analysis of an AC-AC resonant converter with closed loop which is based on the half-bridge series resonant inverter for induction heating. Only two diodes are used in this topology to rectify the mains voltage. The converter can be operated with zero-voltage switching during both switch-on and switch-of transitions. In conventional AC-AC resonant boost converter output power varies according to input voltage. In the designed system a closed loop is implemented in order to keep output power at desired value irrespective of supply voltage. The circuit is simulated using PSIM.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper on a bidirectional DC-DC converter with a Z-source network. The proposed converter aims to increase the output voltage level and regulation range compared to traditional bidirectional converters. It uses a fully bridge symmetrical circuit configuration with voltage and current sources. Simulation results using MATLAB show the converter can reduce current stress and improve efficiency for applications in hybrid electric vehicles and renewable energy systems. Key aspects analyzed include the converter's operating principles, voltage regulation model, and simulation circuit and results demonstrating operation in forward and reverse modes.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
This document summarizes a research paper that proposes a dual-input single-stage inverter topology for standalone solar photovoltaic systems to provide electricity in rural areas without access to the electric grid. The proposed system uses a maximum power point tracking algorithm and boost converter to increase the low voltage from the solar panels. It then uses a single-stage boost inverter with sinusoidal pulse width modulation to efficiently convert the solar DC power to high-quality AC power for loads without additional filters or protections. Simulation and experimental results showed the system could boost input voltages and produce 230V AC output for rural electrification with reduced components compared to traditional two-stage inverter designs.
One person with passion can be better than many people who are just interested. The document discusses how sharing experiences with friends at Lincoln Center expanded their horizons and was a source of inspiration, showing how individuals who expand each other's horizons strengthen their community. It also talks about learning about a new culture through dance and becoming part of a dance community.
A medida provisória n.º 561/2012 e as alterações ao programa "Minha Casa, Min...adrianoweller
Título do Artigo: A medida provisória n.º 561/2012 e as alterações ao programa "Minha Casa, Minha Vida"
Autor: RIBEIRO, Adriano Weller
Título do Periódico: Jornal Regional
Volume, fascículo, série: Ano 23 - Edição 5.909
Ano/mês: 2012/março
Editora: Gráfica e Editora Dracena
Cidade: Dracena/SP
Página inicial: 02
Página final: 02
Idioma: Português
"O Negócio do Varejo (Digital) Mudou!" - Palestra de Maurício Salvador - Semi...O Negócio do Varejo
O documento discute as mudanças no varejo digital no Brasil. Ele mostra que as vendas online cresceram significativamente nos últimos anos devido à conveniência, variedade, preço, prazo e segurança oferecidos. No entanto, pesquisas indicam que vendedores de lojas físicas ainda não estão totalmente preparados para integrar canais online e offline.
Este documento introduce las telecomunicaciones como el estudio y aplicación de sistemas para comunicación a larga distancia a través de señales transmitidas y recibidas. Aunque las señales se propagan típicamente a través de ondas electromagnéticas, también pueden transmitirse a través de otros medios como sonidos o imágenes. Las telecomunicaciones se han desarrollado rápidamente desde finales del siglo XIX a través de etapas como la telegrafía, radio, telefonía, televisión e Internet, y han jugado un papel
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Este documento presenta los estudios previos para contratar el suministro de frutas, legumbres y verduras para un centro de bienestar de ancianos en Cocorna, Antioquia. Detalla el marco legal, la necesidad de proveer una alimentación balanceada para los 14 adultos mayores, y especifica las cantidades y precios de los productos a contratar por $5 millones de pesos durante un plazo de 5 meses.
Mision de semana santa y Gran fiesta a las madres JMVAngel L Medrano
La Juventud Mariana Vicentina y su asesor el Padre Ángel L. Medrano Matos realizaron su misión anual de Semana Santa en siete comunidades, con la participación de 66 jóvenes. Luego celebraron la Pascua con un paseo recreativo para los misioneros. Otro evento fue la Gran Fiesta a las Madres el 25 de mayo, a la que asistieron unas 300 personas y contó con la participación de varios grupos artísticos y culturales para agasajar a las madres con premios, incluyendo una comput
This course introduces students to statistical methods used in professional careers. Students will learn to analyze, present, and interpret data sets using graphical and numerical methods. They will analyze large real-world data sets using statistical software. The course learning outcomes include analyzing and comparing data sets, using linear regression and hypothesis testing, and applying statistical concepts to modeling and inference. Students must complete a required project on simple regression analysis involving data collection, analysis, and presentation.
Este documento presenta un resumen de un trabajo de grado sobre bases de datos realizado por Daniel Steven Hernández Zarate y Andrés Felipe Infante Cardoso para el Colegio Nacional Nicolás Esguerra en Bogotá, Colombia en 2015. El trabajo incluye una introducción, objetivos, planteamiento del problema, marco teórico, materiales y metodología, desarrollo del proyecto, conclusiones, recomendaciones y bibliografía.
El Fenómeno de las Sillas Blancas: Una de las Herramientas del Narcotráfico.Criminociencia Revista
El autor diserta sobre un acontecimiento actual sobre el narcomenudeo, describe su percepción y observación de esta conducta antisocial y la percepción actual de la población.
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Low Power Energy Harvesting & Supercapacitor StorageIOSR Journals
This document describes a system for harvesting energy from human power sources like hand cranking or an exercise bicycle and storing it in a supercapacitor bank. The system includes a hand cranked generator, current limiter, voltage sensing circuit, supercapacitor bank, charge balancing circuit, DC-DC converter, and load. Small amounts of energy generated by human power are stored in the supercapacitor bank, which can then be used to power small electronic devices through the DC-DC converter. The supercapacitors allow for rapid charging and discharging of energy and help utilize intermittent bursts of energy from human power sources.
This document discusses low power high performance baud rate generators using MTCMOS voltage interface circuits. It compares feedback based and multi-VTH based voltage level converters that are used in baud rate generators to interface between circuits operating at different voltage levels. The multi-VTH level converters are found to offer significant power savings compared to feedback based converters. A baud rate generator is designed and simulated using different level converters in 90nm CMOS technology. The multi-VTH level converter LC5 provides the lowest power when used in the baud rate generator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Coupled Inductor Based High Step-Up DC-DC Converter for Multi Input PV SystemIJERA Editor
With the shortage of the energy and ever increasing of the oil price, research on the renewable and green energy
sources, especially the solar arrays and the fuel cells, becomes more and more important. How to achieve high
step-up and high efficiency DC/DC converters is the major consideration in the renewable power applications
due to the low voltage of PV arrays and fuel cells. In this paper a coupled inductor dc-dc converter for photovoltaic
system is proposed. The circuit configuration of the proposed converter is very simple. Thus, the
proposed converter has higher step-up and step-down voltage gains than the conventional bidirectional dc–dc
boost/buck converter. Under same electric specifications for the proposed converter and the conventional
bidirectional boost/buck converter, the average value of the switch current in the proposed converter is less than
the conventional bidirectional boost/buck converter. The operating principles have been applied to multi input
photovoltaic system and outputs have been observed.
PV Cell Fed High Step-up DC-DC Converter for PMSM Drive ApplicationsIJMTST Journal
In this concept novel high step-up dc–dc converter with an active coupled-inductor network is presented for
a sustainable energy system. The proposed converter contains two coupled inductors which can be
integrated into one magnetic core and two switches. The primary sides of coupled inductors are charged in
parallel by the input source, and both the coupled inductors are discharged in series with the input source to
achieve the high step-up voltage gain with appropriate duty ratio, respectively. In addition, the passive
lossless clamped circuit not only recycles leakage energies of the coupled inductor to improve efficiency but
also alleviates large voltage spike to limit the voltage stresses of the main switches. The reverse-recovery
problem of the output diode is also alleviated by the leakage inductor and the lower part count is needed;
therefore, the power conversion efficiency can be further upgraded. The voltage conversion ratios, the effect of
the leakage inductance and the parasitic parameters on the voltage gain are discussed. The voltage stress
and current stress on the power devices are illustrated and the comparisons between the proposed converter
and other converters are given. The simulation results are presented by using Mat lab/Simulink software.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
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IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
1) The document proposes techniques for reducing power consumption in VLSI circuits, including minimizing bus transitions using coding schemes, resistive feedback paths to eliminate glitches, and voltage scaling.
2) A resistive feedback method is developed to eliminate glitches in CMOS circuits which reduces power consumption and improves performance.
3) Simulation results show that the proposed resistive feedback technique is effective at minimizing glitches and reducing unnecessary power dissipation compared to a design without feedback paths.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUITAnil Yadav
This document discusses sources of power consumption in digital CMOS circuits and techniques for low power VLSI design at the circuit level. It covers the four main sources of power consumption: leakage power, short-circuit power, static power, and switching power. It then discusses various low power design techniques at the circuit level, including transistor and gate sizing, equivalent pin ordering, network restructuring, transistor network partitioning, and low power flip-flop designs. The goal is to optimize power consumption through techniques like minimizing switching activity, reducing capacitive loads, and optimizing transistor sizing.
A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICESVLSICS Design
This document summarizes and analyzes different types of charge pump circuits. It begins by introducing charge pumps and their applications. It then reviews the Dickson charge pump circuit and identifies its limitation of threshold voltage drops across diodes. The document proposes a static CTS charge pump to address this but finds it also has issues from reverse charge sharing. Finally, a dynamic CTS charge pump is presented that uses additional transistors to fully turn on and off switches to prevent reverse charge flow and improve efficiency. Simulation results show its output voltage is higher than other designs.
Power Dissipation of VLSI Circuits and Modern Techniques of Designing Low Pow...IJSRD
This paper focus on the various sources of power dissipation in modern VLSI circuits. This paper also discuss the importance of designing low power VLSI circuits along with various techniques of power reduction and its advantages and disadvantages. It is basically a comparative study between various power reduction techniques in modern VLSI circuits.
A Novel High Step-Up DC–DC Converter for Hybrid Renewable Energy System appli...IJERD Editor
Large electric drives and utility applications require advanced power electronics converter to meet
the high power demands. As a result, power converter structure has been introduced as an alternative in high
power and medium voltage situations using Renewable energy sources (RES). This paper describes a new
DC/DC converter with safety, high efficiency and high step up capabilities. This converter is best suited for
Wind/Fuel cell(FC)based Induction Motor applications for pumping systems. The safety feature of this
converter makes it friendly for the farmers to use it for irrigation and agriculture usages. The converter achieves
high step-up voltage gain with appropriate duty ratio and low voltage stress on the power switches. Also, the
energy stored in the leakage inductor of the coupled inductor can be recycled to the output. The maximum
output voltage is determined by the number of the capacitors. The capacitors are charged in parallel and are
discharged in series by the coupled inductor, stacking on the output capacitor. Thus, the proposed converter can
achieve high step-up voltage gain with appropriate duty ratio and interfaced to induction motor through 9-level
inverter and also energy fed to grid system when no load operation. The simulation results are obtained using
MATLAB/SIMULINK software.
A Novel High Step-Up DC–DC Converter for Hybrid Renewable Energy System appli...
Il3115821590
1. Varun Singh, Maan Singh, Tarun Arora, Ankit Kaushik , Praveer Saxena / International
Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.1582-1590
Design Of 2:1 Multiplexer Using Two Phase Drive Adiabatic
Dynamic CMOS Logic For Low Power Applications
Varun Singh, Maan Singh, Tarun Arora, Ankit Kaushik, Praveer Saxena
Department of ECE A.I.M.T Greater Noida, India
Department of ECE A.I.M.T Greater Noida, India
Department of ECE A.I.M.T Greater Noida, India
Department of ECE A.I.M.T Greater Noida, India
Asst. Professor, Deptt. of ECE.A.I.M.T Greater Noida, India
Abstract:
A MULTIPLEXER is an essential family is a superlative approach to reduce dynamic
electronic device which is basically used for all power dissipation [1][2][3][4][5][11] and [12].
kind of electronic switching. It is commonly The adiabatic switching technique can
called as data selector. The contemporary in achieve very low power dissipation, but at the
VLSI is demanding the need of devices which expense of circuit complexity. Adiabatic logic offers
dissipates low power. Adiabatic logic family is a way to recycle the energy stored in the load
fulfilling our demands, which dissipates low capacitor rather than the traditional way of
power through them. In this paper, we have discharging the load capacitor to the ground and
studied the various adiabatic logic styles: wasting this energy. Adiabatic circuits use the
Adiabatic dynamic CMOS logic, two phase drive following two methods to achieve low power
adiabatic dynamic logic, Glitch free and dissipation: slow charging and discharging, and
Cascadable adiabatic logic and two phase clocked charge recycling to minimize the power consumed.
adiabatic static CMOS logic. Further, we design a Different styles of adiabatic logic have been
2:1 multiplexer using Static CMOS and 2PADCL represented by different authors in their research
logic style. The 2:1 multiplexer was designed and work [2][5][6][7][8][9][10] and [13].
simulated using HSPICE with 180nm technology In this paper, we have designed a 2:1 multiplexer
parameters provided by predictive technology. using one of the adiabatic logic styles i.e. 2PADCL.
The 2:1 multiplexer designed using 2padcl is Further, we compared our adiabatic logic style with
analyzed on the basis of average power consumed static CMOS on the basis of power dissipation for
by them for various values of load capacitance, different values of load capacitance, frequency and
input frequency and temperature. The results are temperature.
then compared with static CMOS. It is observed
that, multiplexer designed using adiabatic logic II. OVERVIEW OF POWER DISSIPATION
consumes low power in comparison to The power consumed when the CMOS
multiplexer designed using static CMOS and also, circuit is in use can be decomposed into two basic
this power saving comes at the cost of increased classes: static and dynamic.
propagation delay. Under certain operating A. STATIC POWER :
conditions, 2PADCL of adiabatic logic design of The static or steady state power dissipation of a
2:1 multiplexer successfully accomplished a circuit is expressed by following relation:
power saving of upto 65% in comparison to
multiplexer designed using static CMOS logic. Pstat = IstatVDD (1)
Keywords - CMOS; adiabatic; energy restoration; Where, Istat is the current that flows through
low power; 2:1 multiplexer. the circuit when there is no switching activity.
Ideally, CMOS circuits dissipate no static(DC)
I. INTRODUCTION power since in the steady state there is no direct path
In this modern era of technology, people from VDD to ground as PMOS and NMOS transistors
need electronic device which are portable, versatile can never turn on simultaneously. Of course, this
and dissipates low power. The current static CMOS scenario can never be realized in practice since in
technology provide the basis for low power reality the MOS transistor is not a perfect switch.
dissipation with an advantage of small fabrication Thus, there will always be leakage currents and
space compared to similar technologies but still it substrate injection currents, which will give to a
dissipates enormous energy in the form of heat, static component of CMOS power dissipation.
mostly when switching. This type of power
dissipation is dynamic in nature. Adiabatic logic
1582 | P a g e
2. Varun Singh, Maan Singh, Tarun Arora, Ankit Kaushik , Praveer Saxena / International
Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.1582-1590
B. DYNAMIC POWER : totally depends on the material used, so we are left
The dynamic component of power with dynamic power dissipation, which is needed to
dissipation arises from the transient switching charge and discharge the capacitive nodes in the
behavior of the CMOS device. It can be further circuit and hence is the major factor of power
divided in two categories: Switching Power, Short dissipation in Static CMOS. To charge the capacitive
circuit Power and leakage current. node upto supply potential of VDD, an energy E =
Switching power is the power dissipated in CV2DD is needed from the power supply. When input
MOSFET resistances while charging or discharging is low, PMOS turns ON and one half of this energy
the load capacitances. (E = CV2DD) gets temporarily stored in load
At some point during the switching capacitor and other half gets dissipated as heat due
transient, both the NMOS and PMOS devices will be to the ON resistance of PMOS transistor. Now, when
turned on. This occurs for gate volatges between Vtn input gets high, NMOS turns on and discharges the
and VDD-Vtp. During this time, a short-circuit exists energy stored in load capacitor from potential of VDD
between VDD and ground and the currents are to ground and as heat. So, during a complete cycle of
allowed to flow[11]. charging and discharging, the energy equivalent E =
The dynamic or switching power CV2DD is drawn for power supply and is dissipated
dissipation of a circuit is expressed by the following as heat [9][11].
realtion:
ADIABATIC CHARGING/DISCHARGING:
Pdyn = αCV2DDf. (2) Charging in static CMOS suffers from high
potential across the switching device due to abrupt
Where, α is the switching activity which supply of power. Adiabatic logic does not abruptly
goes from 0 to 1 for every transition, C is the load switch from 0 to VDD and vice versa. They use a
capacitance, VDD is the power supplied to the circuit ramp voltage to charge the capacitor to VDD and
and f is clock frequency. recover energy from the output. The ramp voltage is
generated using a time varying source to charge a
As power dissipation due to leakage depends capacitor. This time varying source slowly rises
upon material used, so it is impossible to gain towards high potential ensuring no high potential
control over static power dissipation whereas power across the switching device. The charging of
dissipation due to switching, logic activity and adiabatic logic is shown in the figure 1[11]:
glitches is dynamic in nature and can be controlled
using suitable methods.
III. ADIABATIC LOGIC
The term “adiabatic” comes from
thermodynamics, used to describe a process in which
there is no exchange of heat with the environment.
The adiabatic logic structure supports reducing the
power dissipation across the device. Adiabatic logic
is a potential successor for static CMOS design when
it comes to ultralow power energy consumption.
Future development like the revolutionary shrinking Figure 1: Adiabatic Charging.
of the minimum feature size as well as the
revolutionary novel transistor concepts will change R is the resistance in the charging path across the
the gate level savings gained by adiabatic logic [9]. circuit, consists the ON resistance of the PMOS
Basically, adiabatic logic uses “reversible transistor in the charging path. So the current will be
logic” to conserve energy. So they conserve charge [11]:
by following key rules:
Slow charging and discharging. I = CLVDD/T (3)
Charge recycling to minimize the power
consumed. Thus energy dissipated during charging can be
IV. CHARGING/DISCHARGING PROCESS IN written as [11]:
STATIC CMOS AND ADIABATIC LOGIC
STYLE [9][11] EDiss = (RCL/T)CLV2DD (4)
CHARGING/DISCHARGING IN STATIC Whole process consists of charging and
CMOS: discharging. Discharging process will also led to
The power dissipation in Static CMOS is same amount of energy dissipation, so the overall
static and dynamic. As static power dissipation dissipation of energy across adiabatic logic can be
represented as [11]:
1583 | P a g e
3. Varun Singh, Maan Singh, Tarun Arora, Ankit Kaushik , Praveer Saxena / International
Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.1582-1590
EDISS = 2 (RCL/T)CLV2DD (5)
From equation (3), we can see that slower the circuit
is charged, less will be the energy dissipated across
the circuit. Larger the value of T, less will be the
power dissipation.
V.ADIABATIC LOGIC STYLES
In recent years, many adiabatic logic styles
have been described by different researchers in their
research works Different styles of adiabatic logic Figure 2: ADCL inverter.
have been represented by different authors in their The resulting simulations of ADCL are shown below
research work [1][2][5][6][7][8][10] and [13]. These in fig.3:
adiabatic logic styles differ in their circuit
complexity and number of power clocks. Due to the
different circuit complexity and different number of
power clocks, adiabatic logic differs in their working
process and gives different advantage over one
another for different applications. The adiabatic
logic can easily be derived from known static CMOS
without doing any much change in the configuration.
In this section we will study about following
adiabatic logic styles: adiabatic dynamic CMOS
logic, two phase drive adiabatic dynamic CMOS
logic, glitch free and cascadable adiabatic logic, two
phase clocked adiabatic static CMOS logic.
A. Adiabatic dynamic CMOS logic(ADCL)
Adiabatic dynamic CMOS logic was
proposed by K. Takahashi and Mizunuma [5]. It is a
diode based adiabatic logic which uses one power
clock and is used for low power applications. The
clock used is either sinusoidal or triangular. It uses Figure 3: Waveform after simulation.
two rectifying diodes, one each in charging and
discharging path to control the charge flow. We have B. Two phase drive adiabatic dynamic CMOS
used MOSFET as diode by shorting gate and drain logic(2PADCL)
of MOSFET together. The sources that may cause The problem associated with ADCL is its
energy dissipation in this logic family are threshold delay. To overcome this delay, Y. Takahashi et al
voltage of MOSFET, diode cut in potential and [13] introduced 2PADCL. The two phase drive
energy dissipated in resistance of MOS devices. The adiabatic dynamic CMOS logic resembles the
use of slowly varying power clock ensures the small behavior of static CMOS. It uses complementary two
energy dissipation across the ON resistance of MOS phase supply with 180o phase shift. These supplied
devices [9]. clock waveforms consists of two modes “evaluation”
and “hold” [9]. When both power supplies, Vclk and
This logic style comes with major Vclk’ are in evaluation mode, there is an conducting
drawbacks: the problem of delay associated with it path in either PMOS devices or NMOS devices.
[5]. The propagation delay in this logic family Output node may evaluate from high to low or low to
depends on period/frequency of power clock. Beside high or will remain unchanged. Output node will
the delay problem, it also requires a load capacitor to hold its value when Vclk and Vclk’ are in hold mode.
hold the output. The schematic of an inverter using Circuit nodes are not necessarily charging and
this logic family along with resulting waveforms discharging every clock cycle, reducing the switching
after simulation is shown in fig.2 [5] [9]: activity. Reducing the switching activity leads to the
faster performance of 2PADCL in comparison to
ADCL circuits [13].
The threshold voltage of MOSFET, diode
turn on voltage and dissipation across conducting
MOSFETs are the major sources of energy
dissipation in 2PADCL. The schematic of an
inverter using this logic family along with resulting
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waveforms after simulation is shown in fig. 4 [9]
[13]:
Figure 4: 2PADCL inverter
The resulting simulations of 2PADCL are shown in
fig. 5 below:
Figure 6: GFCAL inverter.
The resulting simulations of GFCAL are shown in
fig. 7 below:
Figure 5: Waveform after simulation.
C. Glitch free and cascadable adiabatic
logic(GFCAL)
This logic family was introduced by Reddy,
Satyam and Kishore et al [10]. GFCAL is simple and
Figure 7: Waveform after simulation.
does not require complimentary signals or complex
clocking. It uses single clock signal as supply and
This adiabatic logic style introduces delay.
uses rectifying diodes at both charging and
The use of single power clock is the reason for delay
discharging path, so that ripples does not occur and
in this logic family.
it becomes suitable for cascadable operations [10].
Like 2PADCL, we have used MOSFET as diode by
D. Two phase clocked adiabatic static CMOS
shorting gate and drain.
logic(2PASCL)
The logic style we have discussed so far:
Its drawback is the use of rectifying diodes
ADCL, 2PADCL and GFCAL, all suffers from the
for controlling the charging and discharging of
problem of output amplitude degradation as they use
output nodal capacitance. These rectifying diodes
diode in charging path. To overcome output
are responsible for power dissipation due to the cut
amplitude degradation, Annur et al [6][7] proposed
in voltage drop across them. The schematic of an
new logic family named 2PASCL.
inverter using this logic family along with resulting
waveforms after simulation is shown in fig.6 [9]:
The removal of diode from the charging
path, 2PASCL will lead to higher amplitude and
also, power consumption due to diode is reduced.
2PASCL uses two complementary split level
sinusoidal power supply clocks whose peak to peak
value is equal to VDD/2 [7].
Dissipation of power in 2PASCL is because
of threshold voltage of MOSFET, diode cut-in
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potential and dissipation in resistance of PMOS and
NMOS while charging or discharging the load.
The schematic of an inverter using this
logic family along with resulting waveforms after
simulation is shown in fig 8 [9]:
Figure 10: Static CMOS inverter.
Simulation of Static CMOS inverter results in
following waveform as shown in fig. 11:
Figure 8: 2PASCL inverter.
The resulting simulations of 2PASCL are shown in the fig.
9
below:
Figure 11: waveforms after simulation.
So far we have discussed about inverters
using ADCL, 2PADCL, GFCAL, 2PASCL and
Static CMOS. On discussing them, we found that
ADCL can be used as multiplexer to save power
dissipation but it suffers from the problem of
significant propagation delay problem as it uses
single power clock, GFCAL also suffers from the
problem of propagation delay as it also uses single
power clock and 2PASCL suffers from the problem
of ripples in the output. So, we used 2PADCL to
make a 2:1 multiplexer as it significantly cure the
Figure 9: waveforms after simulation.
problem of propagation delay by using two power
clocks and also, it does not suffers from the problem
E. Static CMOS logic
of ripples in the output as in the case of 2PASCL.
All the logic style we have studied so far,
Further, now we will discuss on the multiplexers
were based on basic static CMOS style. The basic
based on Static CMOS and 2PADCL.
static CMOS inverter consists of complimentary
transistors, PMOS and NMOS. Both PMOS and
VI. DESIGN AND SIMULATION OF A 2:1
NMOS are connected in series with a power supply
MULTIPLEXER
of VDD. This configuration helps increasing the
In this section, we have designed and
processing speed by reducing resistance compared to
simulated a 2:1 multiplexer using Static CMOS and
NMOS-only or PMOS-only type devices. Also, it
2PADCL. The 2:1 multiplexer is designed and
reduces the power consumption since one of the
simulated by HSPICE and we have used 180nm
transistors is always remains off in both logic states.
technology parameters provided by predictive
technology. The supply voltage VDD is 1.8v and the
The schematic of an inverter using static
body terminals of NMOS and PMOS are connected
CMOS inverter along with resulting waveforms after
to GROUND and VDD respectively. The length and
simulation is shown in fig. 10:
width of MOSFETs are L = 180nm and W = 720nm
respectively and the operating temperature is chosen
is 25oC. The power clock is kept at 100MHz, input
selected are D0=12.5Mhz, D1=8.33Mhz and
S=25Mhz. Diodes used are made from MOSFET by
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shorting gate and drain terminal of NMOS and the select(S) signal is high it outputs the signal D1,
PMOS respectively. respectively. The multiplexer based on adiabatic
2PADCL uses complementary two phase supply
A. Design and Simulation of a 2:1 Multiplxer signals as input. The power clock is 100MHz, input
using Static CMOS logic. selected are D0=12.5Mhz, D1=8.33Mhz and
S=25Mhz, and the operating temperature is 25oC.
The design of 2:1 multiplexer circuit using adiabatic
2PADCL is given below in fig. 14:
Figure 12: 2:1 multiplexer using Static CMOS.
Simulations results of waveforms for 2:1 multiplexer
using static CMOS are as shown in fig. 13: Figure 14: 2:1 multiplexer using 2PADCL.
As to avoid confusion and for better
understanding, we made a coloured power supply,
ground and select. The waveforms resulting after
Simulation of multiplexer using 2PADCL are as
shown in Fig. 15.
Figure 13: Waveforms after simulation.
The above waveforms after simulation indicates
that Static CMOS multiplexer gives a ripple free
output without any significant propagation delay
problem.
B. Design and Simulation of 2:1 Multiplexer
using Adiabatic 2PADCL:
It implements the function F = (D0)(S’) + Figure 15: Waveforms after simulation.
(D1)(S). When the select(S) signal is low, it selects
the signal D0 and steers it to the output and when
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As can be seen from the fig. 15, that because of On the basis of simulation results shown in Table I, a
the use of diodes in charging and discharging path, graph has been plotted showing the variation of
we are getting ripple free output and also, the use of power consumption by Static CMOS Multiplexer and
complementary sin waves eliminates the problem of 2PADCL Multiplexer:
delay, as associated with ADCL and GFCAL with
an advantage of low power dissipation across the
circuit.
C. COMPARISON OF MULTIPLXER ON THE
BASIS OF DIFFERENT PARAMETERS:
We have so far designed and simulated 2:1
Multiplexers based on static CMOS and adiabatic
2PADCL. But this simulation is based on constant
load capacitance, constant frequency and constant
room temperature. But in the real world, multiplexer
need to be work on varying parameters and varying
conditions. So, now we will observe the effect of
varying condition or varying parameters on Static Figure 16: Variation of Avg. Power Consumption
CMOS Multiplexer and Multiplexer based on with Load Capacitance.
adiabatic 2PADCL and observe, why multiplexer
based on adiabatic 2PADCL is better in power The average power dissipation increases
savings then Multiplexer based on Static CMOS. with the increment in load capacitance.As can be
The 2:1 static CMOS Multiplexer and 2:1 adiabatic seen from the graph I, with increase in load
2PADCL Multiplexer were compared on different capacitance, the power dissipation across Static
varying parameters on the basis of power dissipation CMOS multiplexer increases significantly but in
across them.’ multiplexer using 2PADCL, this power dissipation is
not increasing at the rate as with the case of
i) Average power consumed by 2:1 Multiplexer multiplexer using Static CMOS. With constant
designed with static CMOS family and temperature and power clock supply and varying load
2PADCL family for different values of load capacitance, the multiplexer using 2PADCL tends to
capacitence. offers upto 65% of power saving in comparison to
In this section, we have observed the effect multiplexer based of Static CMOS.
of variation in load capacitance over the average ii) Average power consumed by 2:1 Multiplexer
power consumed by 2:1 multiplexer based on Static designed with static CMOS family and 2PADCL for
CMOS and Adiabatic 2PADCL. The load different Input frequecies.
capacitance is varied from 10-190fF with a step size In this section, we have observed the effect
of 20fF and resulting power consumption is of variation in frequency over the average power
observed. The operating temperature is kept constant consumed by 2:1 multiplexer based on Static CMOS
i.e 25oC. Input selected are D0=12.5Mhz, and Adiabatic 2PADCL. We have kept power clock
D1=8.33Mhz and S=25Mhz. The effect of variation frequency to be 100MHz. While varying the
of load capacitance over power dissipation is shown frequency of inputs, we have kept temperature and
in the table below: load capacitance constant. The variation in TSON kept
Table I : Variation of Avg. Power Consumption between 20-200ns with a step size of 20ns. The
with Load Capacitance. temperature is kept 25oC.
Load Power Power Power % of
capacitan Dissipation dissipation reduction Power As, frequency is inversely proportional to
ce Of CMOS of 2padcl µw reducti the time period of the wave T = 1/f, so by varying
CL (fF) mux on the time period TON of a wave, we can observe
10 2.249 1.019 1.23 54.69 power dissipation for different values of input
frequencies, where T = TON + TOFF and the wave is
30 3.03 1.3761 1.654 54.58
square in nature with TON = TOFF. So, more the time
50 3.829 1.692 2.137 55.81 period, lower will be the frequency, and less will be
70 4.632 1.977 2.655 57.31 the power dissipation. Also, as multiplexer has two
90 5.439 2.233 3.206 58.94 inputs and a select line: D0, D1 and S, so we have
110 6.246 2.467 3.779 60.50 selected their time periods as TD0 = 2TS and TD1 =
3TS. As we have mentioned the relationship between
130 7.054 2.679 4.375 62.02 time periods of both input and select line, the time
150 7.863 2.875 4.988 63.43 period of all three will vary, as a fact frequency will
170 8.672 3.054 5.618 64.78 also vary.
190 9.481 3.216 6.265 65.07
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Table II : Variation of Avg. Power Consumption temperature is kept between 10o-90oC with a step
with Varying Time Period.. size of 10oC. The power clock used is of 100MHz
and the load capacitance is kept at a value of 10fF.
TSON of Power Power Power % power The effect of variation of temperature on power
select Dissipation dissipation reduction reduction dissipation of multiplexer using Static CMOS and
line Of CMOS Of In µw 2PADCL is shown in the table III below:
In µw 2PADCL
In µw
20 3.116 1.195 1.921 61.64 Table III : Variation of Avg. Power Consumption
40 1.355 0.6200 0.735 54.24 with Varying Temperature.
60 0.8337 0.4211 0.4126 49.49
Temperature Power Power Power %
80 0.5696 0.3036 0.266 46.69 In oC dissipation dissipation Reducti power
100 0.4681 0.2522 0.2159 46.12 Of CMOS Of -on Red-
120 0.3974 0.2136 0.1838 46.25 In µw 2PADCL In µw uction
140 0.3569 0.1986 0.1583 44.35 In µw
10 2.239 0.9921 1.2469 55.69
160 0.3072 0.1684 0.1388 45.18
180 0.2581 0.1393 0.1188 46.02 20 2.245 1.009 1.236 55.05
200 0.2307 0.1221 0.1086 47.07 30 2.255 1.029 1.226 54.36
40 2.267 1.050 1.217 53.68
On the basis of simulation results shown in Table II,
50 2.277 1.071 1.206 52.96
a graph has been plotted showing the variation of
power consumption by Static CMOS Multiplexer 60 2.292 1.095 1.197 52.22
and 2PADCL Multiplexer: 70 2.309 1.118 1.191 51.58
80 2.363 1.142 1.221 51.67
90 2.387 1.167 1.220 51.11
On the basis of simulation results shown in Table
III, a graph has been plotted showing the variation of
power consumption by Static CMOS Multiplexer
and 2PADCL Multiplexer:
Figure 17:Variation of Avg. Power Consumption
with Varying Time Period
As can be observed from the Fig. 17, with increase in
frequency, the power dissipation across multiplexer
using Static CMOS and 2 PADCL is increasing. At
low freqencies, the power dissipation is less. With
constant load capacitance and consrant temperature
and varying frequency, the multiplexer using Figure 18: Variation of Avg. Power Consumption
2PADCL gives a power saving upto 61% in with Varying Load Capacitance.
comparison to multiplexer using Static CMOS.
As can be observed from the Fig.18, with
iii) Average power consumed by 2:1 Multiplexer increase in temperature, power dissipation across
designed with static CMOS family and multiplexer using Static CMOS and 2PADCL is
2PADCL for different operating increased. The reason for increase in dissipation is
temperature. static power dissipation associated with it, which
In this section, we have observed the effect occurs due to sub threshold current and leakage
of variation in temperature over average power current. At normal temperature the power dissipation
consumed by 2:1 multiplexer based on Static CMOS due to sub threshold and leakage current can be
and Adiabatic 2PADCL. While varying the ignored. But with increase in temperature, the
temperature, we have kept constant frequency and dissipation due to sub threshold and leakage starts
constant load capacitance. The variation in
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Vol. 3, Issue 1, January -February 2013, pp.1582-1590
increasing and contributes effectively to the overall IEICE Trans. Electron., Vol. J81-CII, Issue
power dissipation of the circuit. 10, pp. 810 -817, October 1998.
The power saving in multiplexer based on 2PADCL [6]. N. ANUAR, Y. TAKAHASHI, and T.
is 55% more as compared to multiplexer based on SEKINE, “Two phase clocked adiabatic
Static CMOS. This power saving decreases with static CMOS logic”, Proc. IEEE SOCC
increase in temperature as sub threshold and leakage 2009, pp. 83-86, Oct. 2009.
current starts increasing across the circuit. [7]. N. ANUAR, Y. TAKAHASHI, and T.
SEKINE, “Two phase clocked adiabatic
VII. CONCLUSION static CMOS logic and its logic family,”
With this research paper, we have Journal of Semiconductor Technology and
successfully designed a 2:1 multiplexer based on Science, Vol. 10, No. 01, pp. 1-10, March
2PADCL adiabatic logic and Static CMOS. With 2010.
adiabatic logic switching approach, the circuit [8]. PRAVEER SAXENA, DINESH KUMAR
energy is retained rather than dissipated as heat. We and SAMPATH KUMAR V, “Design of 1-
compared the results based on average power bit full adder for low power applications”,
dissipation in both the circuit on various parameters International Journal Of Advanced
like varying load capacitance, varying temperature Engineering Sciences And Technologies,
and varying frequency. We found that under certain Vol. No. 10, Issue No. 1, pp. 019 – 025,
operating conditions, the 2:1 multiplexer based on 2011.
2PADCL adiabatic logic style can save power upto [9]. PRAVEER SAXENA, DINESH
65% as compared to 2:1 multiplexer based on Static CHANDRA and SAMPATH V, “An
CMOS. Although, multiplexer based on 2PADCL is adiabatic approach for low power full adder
having delay and circuit complexity than multiplexer design, International Journal on Computer
based on Static CMOS but with the advantage of Science and Engineering, Vol. No.3, No. 9,
high power savings, 2PADCL multiplexer is pp. 3207 -3221, September 2011.
advantageous in applications where power saving is [10]. N.S. S. Reddy, M. SATYAM and K. L.
of prime importance as in high performance portable KISHORE, “Cascadable adiabatic logic
digital systems running on batteries such as circuits for low power applications”, IET
palmtops, note book computers, smart phones etc. Circuits Devices Syst., Vol. 2, No. 06, pp.
518 – 526, 2008.
VIII. ACKNOWLEDGMENT [11]. P. TEICHMANN, “Adiabatic logic”,
The authors will like to thank Assistant Springer science + publication media B.V
Professor Mr. PRAVEER SAXENA for the 2012.
guidance and discussions that they had made with [12]. YEAP, “Practical low power digital VLSI
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perseverance, depth of knowledge and strong [13]. Y. TAKAHASHI, Y. FUKUTA, T.
dedication towards them. Thanks again for SEKINE and M. YOKOYAMA,
everything. “2PADCL: Two phase drive adiabatic
dynamic CMOS logic”, Proc. IEEE
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