This document discusses using the CORDIC algorithm to implement a pipelined FFT for fingerprint recognition on an FPGA. It proposes a hardware-efficient CORDIC FFT architecture that minimizes computational complexity. The CORDIC algorithm replaces complex multipliers with shift-add operations, providing a simpler hardware implementation than traditional multiplier-based FFT designs. The architecture includes a butterfly structure implemented with CORDIC, an angle generator for twiddle factors, and input/output blocks with registers and multiplexers to enable pipelined processing.