This document presents the design of an 8-bit processing element (PE3) for implementing a pipeline fast Fourier transform (FFT) processor. PE3 serves as a sub-module for the other processing elements in the pipeline FFT architecture. The PE3 element was designed using a 10-transistor adder and multiplexer and simulated using Mentor Graphics tools. Simulation results showed the power dissipation of a 1-bit PE3 is 0.5517 mWatts and 0.9237 mWatts for an 8-bit PE3. The PE3 successfully processed the P=3 stage of the radix-2 DIF FFT butterfly structure.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN AND VHDL IMPLEMENTATION OF 64-POINT FFT USING TWO STRUCTURE 8-POINT FF...Journal For Research
In this paper, we present a novel fixed-point 32-bit word-width Radix-2 64-point FFT processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal, image processing and FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). FFT blocks are complex to implement and it consumes more resources. So, a efficient technique used here in which FFT is implemented in such a way that it consumes very less resources. This module of 64-point FFT is designed using VHDL programming language. In this work, a pure VHDL design, integrated with some intellectual property (IP) blocks and simulation, synthesis and implementation XILINX ISE 13.2 software is used.
A Pipelined Fused Processing Unit for DSP Applicationsijiert bestjournal
This paper designs a processing element for FFT pr ocessor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throug hput. The performance of the Processing unit is increased by using the concept of fused arc hitecture on the sub modules � the dot product unit and the add sub unit. Pipelining incre ases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operation s consisting of multiplications,additions,and subtractions of complex valued data (data is sp lit into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed us ing fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 pe rcent smaller in area compared with the conventional method. The processing unit covers alm ost all the computations necessary for the processor.
High Speed Area Efficient 8-point FFT using Vedic MultiplierIJERA Editor
A high speed fast fourier transform (FFT) design by using three algorithm is presented in this paper. In algorithm 3, 4-bit Vedic multiplier based technique are used in FFT. In this technique used in three 4-bit ripple carry adder and four 2*2 Vedic multiplier. The main parameter of this paper is number of slice, 4-input LUTS and maximum combinational path delay were calculate.
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 CompressorIJERD Editor
With the appearance of new innovation in the fields of VLSI and correspondence, there is likewise a perpetually developing interest for fast transforming and low range outline. It is likewise a remarkable certainty that the multiplier unit structures a fundamental piece of processor configuration. Because of this respect, rapid multiplier architectures turn into the need of the day. In this paper, we acquaint a novel structural engineering with perform high velocity duplication utilizing old Vedic math's strategies. Another fast approach using 4:2 compressors and novel 7:2 compressors for expansion has additionally been joined in the same and has been investigated. Upon examination, the compressor based multiplier present in this paper, is just about two times quicker than the mainstream routines for augmentation. Likewise we outline a FFT utilizing compressor based multiplier. This all configuration and examinations were done on a Xilinx Spartan 3e arrangement of FPGA and the timing and zone of the outline, on the same have been ascertained.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN AND VHDL IMPLEMENTATION OF 64-POINT FFT USING TWO STRUCTURE 8-POINT FF...Journal For Research
In this paper, we present a novel fixed-point 32-bit word-width Radix-2 64-point FFT processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal, image processing and FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). FFT blocks are complex to implement and it consumes more resources. So, a efficient technique used here in which FFT is implemented in such a way that it consumes very less resources. This module of 64-point FFT is designed using VHDL programming language. In this work, a pure VHDL design, integrated with some intellectual property (IP) blocks and simulation, synthesis and implementation XILINX ISE 13.2 software is used.
A Pipelined Fused Processing Unit for DSP Applicationsijiert bestjournal
This paper designs a processing element for FFT pr ocessor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throug hput. The performance of the Processing unit is increased by using the concept of fused arc hitecture on the sub modules � the dot product unit and the add sub unit. Pipelining incre ases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operation s consisting of multiplications,additions,and subtractions of complex valued data (data is sp lit into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed us ing fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 pe rcent smaller in area compared with the conventional method. The processing unit covers alm ost all the computations necessary for the processor.
High Speed Area Efficient 8-point FFT using Vedic MultiplierIJERA Editor
A high speed fast fourier transform (FFT) design by using three algorithm is presented in this paper. In algorithm 3, 4-bit Vedic multiplier based technique are used in FFT. In this technique used in three 4-bit ripple carry adder and four 2*2 Vedic multiplier. The main parameter of this paper is number of slice, 4-input LUTS and maximum combinational path delay were calculate.
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 CompressorIJERD Editor
With the appearance of new innovation in the fields of VLSI and correspondence, there is likewise a perpetually developing interest for fast transforming and low range outline. It is likewise a remarkable certainty that the multiplier unit structures a fundamental piece of processor configuration. Because of this respect, rapid multiplier architectures turn into the need of the day. In this paper, we acquaint a novel structural engineering with perform high velocity duplication utilizing old Vedic math's strategies. Another fast approach using 4:2 compressors and novel 7:2 compressors for expansion has additionally been joined in the same and has been investigated. Upon examination, the compressor based multiplier present in this paper, is just about two times quicker than the mainstream routines for augmentation. Likewise we outline a FFT utilizing compressor based multiplier. This all configuration and examinations were done on a Xilinx Spartan 3e arrangement of FPGA and the timing and zone of the outline, on the same have been ascertained.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Compression is playing a vital role in data transfer. Hence, Digital camera uses JPEG standard to compress the captured image. Hence, it reduces data storage requirements. Here, we proposed FPGA based JPEG encoder. The processing system is coupled with DCT and then it is quantized and then it is prepared for entropy coding to form a JPEG encoder
DUAL FIELD DUAL CORE SECURE CRYPTOPROCESSOR ON FPGA PLATFORMVLSICS Design
This paper is devoted to the design of dual core crypto processor for executing both Prime field and binary field instructions. The proposed design is specifically optimized for Field programmable gate array (FPGA) platform. Combination of two different field (prime field GF(p) and Binary field GF(2m)) instructions execution is analysed.The design is implemented in Spartan 3E and virtex5. Both the performance results are compared. The implementation result shows the execution of parallelism using dual field instructions
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filteridescitation
This paper presents an Orthogonal Frequency Division Multiplexing (OFDM)
transceiver that makes use of a low power Fast Fourier Transform (FFT) along with a Least
Mean Square (LMS) filter. The folded FFT is developed via folding transformation and
register minimization techniques with real values as inputs which leads to reduction in
hardware complexity by exploiting the redundancy present in computing the FFT samples
and also the amount of power consumed. A LMS filter is also designed for the purpose of
noise removal. The OFDM transceiver with the folded FFT and LMS filter is analyzed in
terms of error performance to validate the advantages of less power consumption and
hardware utilization when compared to the traditional OFDM system with conventional
FFT. The individual components and the entire OFDM system that has been proposed are
modeled using Verilog HDL and functionally verified using Xilinx ISIM simulator.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
AN EFFICIENT AND SECURE DIGITAL MULTI-SIGNATURE PROTOCOL BASED ON ECCijcisjournal
Digital Signatures play a crucial role today as it ensures authentication, integrity and non-repudiation of a digital message. Many researches are ongoing based on elliptic curve cryptography due to its significant high performance. In this paper we propose an efficient and secure digital multi-signature protocol based on elliptic curve cryptography. The proposed protocol is efficient with reduced time complexity as compared to Chen et al.[14], Sahu and Sharma [18] and Chande and Thakur’s [20] digital multi-signature schemes. Also the proposed protocol overcomes the insider attack as specified by Liu et al. [19] in the Chen et.al’s digital multi-signature scheme.
Automatic tempest test and analysis systemijcisjournal
Today, it is clearly known that the electronic devices generate electromagnetic radiations unintentionally,
which may contain critical information called compromising emanations (CE). CE is also known as
TEMPEST radiation, which is a code name firstly used by an U.S government program. Every developed
country has a TEMPEST Test Laboratory (TTL) connected to their National Security Agency (NSA). The
main objective of these laboratories is to investigate equipment, systems, and platforms processing
cryptographic information in terms of CE. TEMPEST tests might take very long time depending on the item
under test. In this paper, a complete Automatic TEMPEST Test and Analysis System (ATTAS) developed in
TUBITAK, BILGEM TTL is introduced. The system has the following properties, which are automatic
system calibration unit, automatic test matrix generator based on the SDIP-27/1 standard, implementation
of tunable and nontunable tests, automatic CE investigations, rendering of the CE of video display units,
playing of the CE of audio signals, measurement of detection system sensitivity, zoning of TEMPEST
equipment based on SDIP-28 standard, and generation of graphical results.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Compression is playing a vital role in data transfer. Hence, Digital camera uses JPEG standard to compress the captured image. Hence, it reduces data storage requirements. Here, we proposed FPGA based JPEG encoder. The processing system is coupled with DCT and then it is quantized and then it is prepared for entropy coding to form a JPEG encoder
DUAL FIELD DUAL CORE SECURE CRYPTOPROCESSOR ON FPGA PLATFORMVLSICS Design
This paper is devoted to the design of dual core crypto processor for executing both Prime field and binary field instructions. The proposed design is specifically optimized for Field programmable gate array (FPGA) platform. Combination of two different field (prime field GF(p) and Binary field GF(2m)) instructions execution is analysed.The design is implemented in Spartan 3E and virtex5. Both the performance results are compared. The implementation result shows the execution of parallelism using dual field instructions
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filteridescitation
This paper presents an Orthogonal Frequency Division Multiplexing (OFDM)
transceiver that makes use of a low power Fast Fourier Transform (FFT) along with a Least
Mean Square (LMS) filter. The folded FFT is developed via folding transformation and
register minimization techniques with real values as inputs which leads to reduction in
hardware complexity by exploiting the redundancy present in computing the FFT samples
and also the amount of power consumed. A LMS filter is also designed for the purpose of
noise removal. The OFDM transceiver with the folded FFT and LMS filter is analyzed in
terms of error performance to validate the advantages of less power consumption and
hardware utilization when compared to the traditional OFDM system with conventional
FFT. The individual components and the entire OFDM system that has been proposed are
modeled using Verilog HDL and functionally verified using Xilinx ISIM simulator.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
AN EFFICIENT AND SECURE DIGITAL MULTI-SIGNATURE PROTOCOL BASED ON ECCijcisjournal
Digital Signatures play a crucial role today as it ensures authentication, integrity and non-repudiation of a digital message. Many researches are ongoing based on elliptic curve cryptography due to its significant high performance. In this paper we propose an efficient and secure digital multi-signature protocol based on elliptic curve cryptography. The proposed protocol is efficient with reduced time complexity as compared to Chen et al.[14], Sahu and Sharma [18] and Chande and Thakur’s [20] digital multi-signature schemes. Also the proposed protocol overcomes the insider attack as specified by Liu et al. [19] in the Chen et.al’s digital multi-signature scheme.
Automatic tempest test and analysis systemijcisjournal
Today, it is clearly known that the electronic devices generate electromagnetic radiations unintentionally,
which may contain critical information called compromising emanations (CE). CE is also known as
TEMPEST radiation, which is a code name firstly used by an U.S government program. Every developed
country has a TEMPEST Test Laboratory (TTL) connected to their National Security Agency (NSA). The
main objective of these laboratories is to investigate equipment, systems, and platforms processing
cryptographic information in terms of CE. TEMPEST tests might take very long time depending on the item
under test. In this paper, a complete Automatic TEMPEST Test and Analysis System (ATTAS) developed in
TUBITAK, BILGEM TTL is introduced. The system has the following properties, which are automatic
system calibration unit, automatic test matrix generator based on the SDIP-27/1 standard, implementation
of tunable and nontunable tests, automatic CE investigations, rendering of the CE of video display units,
playing of the CE of audio signals, measurement of detection system sensitivity, zoning of TEMPEST
equipment based on SDIP-28 standard, and generation of graphical results.
RSA ALGORITHM WITH A NEW APPROACH ENCRYPTION AND DECRYPTION MESSAGE TEXT BY A...ijcisjournal
In many research works, there has been an orientation to studying and developing many of the applications of public-key cryptography to secure the data while transmitting in the systems, In this paper we present an approach to encrypt and decrypt the message text according to the ASCII(American Standard Code for Information Interchange) and RSA algorithm by converting the message text into binary representation and dividing this representation to bytes(8s of 0s and 1s) and applying a bijective function between the group of those bytes and the group of characters of ASCII and then using this mechanism to be compatible with using RSA algorithm, finally, Java application was built to apply this approach directly.
A proposed assessment metrics for image steganographyijcisjournal
Data security has become an important problem in the communication systems. Steganography is used to
hide existence of a secret-message. In this article a modified Steganography algorithm will be proposed
depending on decomposition principle of both secret-message and cover-image. A fuzzification is
performed in the secret message to optimize the decomposed coefficients before embedding in the coverimage
to get a Stego Image. The well known metrics (Cor., MSE, PSNR, and Entropy) were used to
evaluate the modified algorithm. Also, a trade-off factor was introduced to determine an optimum value for
the embedding strength factor to get an acceptable degradation. Moreover to evaluate and assess the
modified algorithm and any Steganography algorithms, a new histogram metrics are proposed which
represents the relative frequency occurrence of the various images.
Secure routing path using trust values forijcisjournal
Traditional cryptography-based security mechanisms such as authentication and authorization are not
effective against insider attacks like wormhole, sinkhole, selective forwarding attacks, etc., Trust based
approaches have been widely used to counter insider attacks in wireless sensor networks. It provides a
quantitative way to evaluate the trustworthiness of sensor nodes. An untrustworthy node can wreak
considerable damage and adversely affect the quality and reliability of data. Therefore, analyzing the trust
level of a node is important. In this paper we focused about indirect trust mechanism, in which each node
monitors the forwarding behavior of its neighbors in order to detect any node that behaves selfishly and
does not forward the packets it receives. For this, we used a link state routing protocol based indirect
trusts which forms the shortest route and finds the best trustworthy route among them by comparing the
values of all the calculated route trusts as for each route present in the network. And finally, we compare
our work with similar routing protocols and show its advantages over them.
Global stabilization of a class of nonlinear system based on reduced order st...ijcisjournal
The problem of global stabilization for a class of nonlinear system is considered in this paper.The sufficient
condition of the global stabilization of this class of system is obtained by deducing thestabilization of itself
from the stabilization of its subsystems. This paper will come up with a designmethod of state feedback
control law to make this class of nonlinear system stable, and indicate the efficiency of the conclusion of
this paper via a series of examples and simulations at the end. Theresults presented in this paper improve
and generalize the corresponding results of recent works.
Compact Coding Using Multi-Photon Tolerant Quantum Protocols For Quantum Comm...ijcisjournal
This paper presents a new encryption scheme called Compact Coding that encodes information in time, phase, and intensity domains, simultaneously. While these approaches have previously been used one at a time, the proposed scheme brings to bear for the first time their strengths simultaneously leading to an increase in the secure information transfer rate. The proposed scheme is applicable to both optical fibers and free space optics, and can be considered as an alternative to polarization coding. This paper applies the proposed compact coding scheme to multi-photon tolerant quantum protocols in order to produce quantum-level security during information transfer. We present the structure of the proposed coding scheme in a multi-photon environment and address its operation.
Error Correction for Parallel FIR Filters Using Hamming Codesijcisjournal
In this paper ,we propose a error correction for parallel FIR filters using Hamming code in which single
parallel FIR filter is taken as a bit in ECC technique. In many complex circuits, reliability plays a crucial
role and it requires fault tolerant filter implementations. Now a days, technology grows up, the complex
system use many filters which operates simultaneously. Consider an example in which same parallel filter
is applied to different inputs. To achieve fault tolerance, an ECC technique uses the presence of parallel
filters are considered. The ECC technique provides protection where more number of parallel filters are
used by using the case study, the effectiveness in error correction and circuit design cost is evaluated.
Randomness evaluation framework of cryptographic algorithmsijcisjournal
Nowadays, computer systems are developing very rapidly and become more and more complex, which
leads to the necessity to provide security for them. This paper is intended to present software for testing
and evaluating cryptographic algorithms. When evaluating block and stream ciphers one of the most basic
property expected from them is to pass statistical randomness testing, demonstrating in this way their
suitability to be random number generators. The primary goal of this paper is to propose a new framework
to evaluate the randomness of cryptographic algorithms: based only on a .dll file which offers access to the
encryption function, the decryption function and the key schedule function of the cipher that has to be tested
(block cipher or stream cipher), the application evaluates the randomness and provides an interpretation of
the results. For this, all nine tests used for evaluation of AES candidate block ciphers and three NIST
statistical tests are applied to the algorithm being tested. In this paper, we have evaluated Tiny Encryption
Algorithm (block cipher), Camellia (block cipher) and LEX (stream cipher) to determine if they pass
statistical randomness testing.
Performance Analysis of CRT for Image Encryption ijcisjournal
With the fast advancements of information technology, the security of image data transmitted or stored over
internet is become very difficult. To hide the details, an effective method is encryption, so that only
authorized persons can decrypt the image with the keys available. Since the default features of digital
image such as high capacity data, large redundancy and large similarities among pixels, the conventional
encryption algorithms such as AES, , DES, 3DES, and Blow Fish, are not applicable for real time image
encryption. This paper presents the performance of CRT for image encryption to secure storage and
transmission of image over internet.
Shift Invarient and Eigen Feature Based Image Fusion ijcisjournal
Image fusion is a technique of fusing multiple images for better information and more accurate image
compared input images. Image fusion has applications in biomedical imaging, remote sensing, pattern
recognition, multi-focus image integration, and modern military. The proposed methodology uses benefits
of Stationary Wavelet Transform (SWT) and Principal Component Analysis (PCA) to fuse the two images.
The obtained results are compared with exiting methodologies and shows robustness in terms of entropy,
Peak Signal to Noise Ratio (PSNR) and standard deviation.
Framework for Securing Educational E-Government Serviceijcisjournal
Enhancement in technology is leading to a change in the way governments, individuals, institutions and
business entities provide quality services to the citizen. Today's education system plays crucial role for
developing cognizance in society so e-government service is obliged to integrate with educational system.
In this work we proposed a novel framework for integrating educational service within e-government
services. One of the main tasks of this paper is to explore or propose a Secure Examination Management
System (SEMS). The system has been designed using cryptographic primitives, which enables students to
take the exam from anywhere. The student is allowed to take the exam after he gives his necessary
authentication details. In SEMS, it is important to exclude false students while ensuring the privacy for the
honest students. It allows evaluators to share student examination papers for evaluation with proper
authentication. This is done using digital signatures, authentication and confidentiality provided by public
key cryptographic system.
In this paper we analyze the cryptanalysis of the simplified data encryption standard algorithm using metaheuristics
and in particular genetic algorithms. The classic fitness function when using such an algorithm
is to compare n-gram statistics of a the decrypted message with those of the target message. We show that
using such a function is irrelevant in case of Genetic Algorithm, simply because there is no correlation
between the distance to the real key (the optimum) and the value of the fitness, in other words, there is no
hidden gradient. In order to emphasize this assumption we experimentally show that a genetic algorithm
perform worse than a random search on the cryptanalysis of the simplified data encryption standard
algorithm.
Nowadays, the information processing system plays crucial part in the internet. Online information security
has become the top priority in all sectors. Failing to provide online information security may cause loss of
critical information or someone may use or distribute such information for malicious purpose. Recently QR
barcodes have been used as an effective way to securely share information. This paper presents the survey
on information hiding techniques which can share high security information over network using QR
barcode
A PAIRING-FREE IDENTITY BASED TRIPARTITE SIGNCRYPTION SCHEMEijcisjournal
The certificate-based cryptosystems is traditional way in providing the system parameters. Identity-based
cryptography is more efficient than certificate-based cryptosystems. Each user in identity-based
cryptography uses any arbitrary string that uniquely identifies him as his public key. This paper proposes
a new identity-based tripartite signcryption scheme based on the elliptic curve discrete logarithm problem.
The proposed id-based tripartite signcryption scheme does not use the bilinear pairings in both the
Signcryption and unsigncryption phases. The proposed scheme used to reduce the communication over
head when three entities wants to communicate securely as in authentication protocol in GSM and in ecommerce.
The proposed scheme satisfies various desirable security properties. Also, the performance of
the proposed scheme is tested.
PERFORMANCE ANALYSIS OF SHA-2 AND SHA-3 FINALISTSijcisjournal
National Institute of Science and Technology (NIST) published the first Secure Hash Standard SHA-0 in
1993 as Federal Information Processing Standard publication (FIPS PUBS) which two years later was
replaced by SHA-1 to improve the original design and added SHA-2 family by subsequent revisions of the
FIPS. Most of the widely used cryptographic hash functions are under attack today. With the need to
maintain a certain level of security, NIST had selected new cryptographic hash function through public
competition. The winning algorithm, Keccak will not only have to establish a strong security, but also has
to exhibit good performance and capability to run. In this context, we have analysed SHA-3 finalists along
with the used standard SHA-2. The performances of respective algorithms are evaluated by computing
cycles per byte. The empirical analysis shows that two SHA-3 finalists viz. Skein and BLAKE perform better
which are nearly same as the performance of SHA-2.
Design of Mobile Public Key Infrastructure (M-PKI) Using Elliptic Curve Crypt...ijcisjournal
Recently the demand of mobile phones and their applications are increasing rapidly and as a result, it
becomes essential to design and/or improve the existing PKI (Public Key Infrastructure) useful for mobile
phones or devices. Since a mobile phone has small screen, low computing power, small storage capacity
etc, the present paper proposes an ECC-based mobile-PKI that overcomes these limitations and supports
various mobile-based applications, because the use of ECC significantly reduces the computation cost,
message size and transmission overhead over RSA based PKI as 160-bit key-size in ECC provides
comparable security with 1024-bit key in RSA. Also the proposed method includes a Mobile Home Agent
(MHA) per user and a Registration Authority (RA) that further minimize the major work/processing loads
of mobile phone and Certificate Authority (CA), respectively. This paper addresses a secure
implementation of the proposed M-PKI, whose security analysis against different attacks shows that all
attacks are protected. Finally, a comparative study of the M-PKI with the existing PKI is done, which gives
satisfactory performance.
A Secure Color Image Steganography in Transform Domain ijcisjournal
Steganography is the art and science of covert communication. The secret information can be concealed in content such as image, audio, or video. This paper provides a novel image steganography technique to hide both image and key in color cover image using Discrete Wavelet Transform (DWT) and Integer Wavelet Transform (IWT). There is no visual difference between the stego image and the cover image. The extracted image is also similar to the secret image. This is proved by the high PSNR (Peak Signal to Noise Ratio), value for both stego and extracted secret image. The results are compared with the results of similar techniques and it is found that the proposed technique is simple and gives better PSNR values than others.
A NEW ATTACK ON RSA WITH A COMPOSED DECRYPTION EXPONENTijcisjournal
In this paper, we consider an RSA modulus N=pq, where the prime factors p, q are of the same size. We
present an attack on RSA when the decryption exponent d is in the form d=Md1+d0 where M is a given
positive integer and d1 and d0 are two suitably small unknown integers. In 1999, Boneh and Durfee
presented an attack on RSA when
0.292 d < N . When d=Md1+d0, our attack enables one to overcome
Boneh and Durfee's bound and to factor the RSA modulus
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...IOSRJECE
Now a day’s numerous wireless communication standards have raised additional stringent requirements on each throughput and flexibility for FFT computation. Advanced wireless systems support multiple standards to satisfy the demands of user application necessities. A wireless system whereas supporting multiple standards should also satisfy performance necessities of these supported standards. Meeting performance requirements of multiple standards is a challenge while designing a system. Fast Fourier transformations, a kernel processing task in communication systems, are studied intensively for efficient software and hardware implementations. To design an efficient system, it's necessary to efficiently design its performance critical component. each system must meet stringent design parameters like high speed, low power, low area, low cost, high flexibility and high scalability, designing FFT processor to support multiple wireless standards whereas meeting the above such performance necessities is a difficult task. This paper proposed a highly efficient scalable architecture, software tools design, and design implementation. The reconstruction of the FFT computation flow is design into a scalable structure. The FFT can be easily expanded for any-point FFT computation. The various parameters satisfied the conditions, gives proper and efficient outputs as compare to other platforms.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Power Measurement of 2 And 8 Point FFT Using Radix-2 Algorithm for...IOSRJVSP
In Cooley–Tukey algorithm the Radix-2 decimation-in-time Fast Fourier Transform is the easiest form. The Fast Fourier Transform is the mostly used in digital signal processing algorithms. Discrete Fourier Transform (DFT) is computing by the FFT. DFT is used to convert a time domain signal into its frequency spectrum domain. FFT algorithms uses many applications for example, OFDM, Noise reduction, Digital audio broadcasting, Digital video broadcasting. It’s used to design butterflies for different point FFT. In this paper given to design and power measurement 2 and 8 point FFT by using VHDL. Simulation and synthesis of design is done using Xilinx ISE 14.2
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Implementation of Multiplier-less CDF-5/3 Wavelet Transform for Image Pr...IOSRJVSP
Most of the digital image processing application uses various domain transformation technique to convert time domain information to transform domain which will help to simplify the mathematical modeling. Discrete Wavelet Transform is one of the best transformation techniques. The time-frequency resolution makes this transform sensitive to both time and frequency which will give very good compression and decompression. In this paper, we propose FPGA implementation of multiplier-less CDF-5/3 wavelet transform for image processing application using System-Generator tool.To maintain low area and high frequency we use multiplier-less architecture for CDF-5/3 DWT for our implementation. The VHDL code for multiplier-less structure is fed to system generator tool using standard procedure and synthesis the structure to get the area and frequency
Performance evaluations of grioryan fft and cooley tukey fft onto xilinx virt...csandit
A large family of signal processing techniques consist of Fourier-transforming a signal,
manipulating the Fourier-transformed data in a simple way, and reversing the transformation.
We widely use Fourier frequency analysis in equalization of audio recordings, X-ray
crystallography, artefact removal in Neurological signal and image processing, Voice Activity
Detection in Brain stem speech evoked potentials, speech processing spectrograms are used to
identify phonetic sounds and so on. Discrete Fourier Transform (DFT) is a principal
mathematical method for the frequency analysis. The way of splitting the DFT gives out various
fast algorithms. In this paper, we present the implementation of two fast algorithms for the DFT
for evaluating their performance. One of them is the popular radix-2 Cooley-Tukey fast Fourier
transform algorithm (FFT) [1] and the other one is the Grigoryan FFT based on the splitting by
the paired transform [2]. We evaluate the performance of these algorithms by implementing
them on the Xilinx Virtex-II pro [3] and Virtex-5 [4] FPGAs, by developing our own FFT
processor architectures. Finally we show that the Grigoryan FFT is working fatser than
Cooley-Tukey FFT, consequently it is useful for higher sampling rates. Operating at higher
sampling rates is a challenge in DSP applications.
PERFORMANCE EVALUATIONS OF GRIORYAN FFT AND COOLEY-TUKEY FFT ONTO XILINX VIRT...cscpconf
A large family of signal processing techniques consist of Fourier-transforming a signal,manipulating the Fourier-transformed data in a simple way, and reversing the transformation.We widely use Fourier frequency analysis in equalization of audio recordings, X-ray crystallography, artefact removal in Neurological signal and image processing, Voice Activity Detection in Brain stem speech evoked potentials, speech processing spectrograms are used to identify phonetic sounds and so on. Discrete Fourier Transform (DFT) is a principal mathematical method for the frequency analysis. The way of splitting the DFT gives out various fast algorithms. In this paper, we present the implementation of two fast algorithms for the DFT for evaluating their performance. One of them is the popular radix-2 Cooley-Tukey fast Fourier transform algorithm (FFT) [1] and the other one is the Grigoryan FFT based on the splitting by the paired transform [2]. We evaluate the performance of these algorithms by implementing
them on the Xilinx Virtex-II pro [3] and Virtex-5 [4] FPGAs, by developing our own FFT processor architectures. Finally we show that the Grigoryan FFT is working fatser than
Cooley-Tukey FFT, consequently it is useful for higher sampling rates. Operating at higher
sampling rates is a challenge in DSP applications
Efficient FPGA implementation of high speed digital delay for wideband beamfor...journalBEEI
In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
When stars align: studies in data quality, knowledge graphs, and machine lear...
Design of Processing Element (PE3) for Implementing Pipeline FFT Processor
1. International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
DOI: 10.5121/ijci.2016.5435 323
DESIGN OF PROCESSING ELEMENT (PE3) FOR
IMPLEMENTING PIPELINE FFT PROCESSOR
Mary RoselineThota,MounikaDandamudi and R.Ramana Reddy
Department of ECE, MVGR College of Engineering(A),Vizianagaram.
ABSTRACT
Multiplexing is a method by which multiple analog message signals or digital data streams are combined
into one signal over a shared medium. In communication, different multiplexing schemes are used. To
achieve higher data rates, Orthogonal Frequency Division Multiplexing (OFDM) is used due to its high
spectral efficiency. OFDM became a serious alternative for modern digital signal processing methods
based on the Fast Fourier Transform (FFT).The problems with Orthogonal subcarriers can be addressed
with FFT in communication applications. An 8-bit processing element (PE3), used in the execution of a
pipeline FFT processoris designed and presented in this paper. Simulations are carried out using Mentor
Graphics tools in 130nm technology.
KEYWORDS:
Multiplexing, OFDM, FFT processor, Mentor Graphics tools.
1. INTRODUCTION
InDiscrete Signal Processing and telecommunications, Discrete Fourier Transform (DFT) is
essential. Cooley and Tukey [1] proposed FFT to overcome the intensive computation, which has
applications involving OFDM, such as WiMAX, LTE, DSL, DAB/DVB systems, and efficiently
reduced the time complexity from O(N2
) to O (Nlog 2N), where N denotes the FFT size. Different
FFT processors developed for hardware implementation are classified as memory based and
pipeline based architectures [2-4]. Memory-based architecture (single Processing Element (PE)
approach), consists of a principal Processing Element and multiple memory units resulting in
reduced power consumption and less hardware than the pipeline architecture, but have
disadvantages like low throughput, long latency, and cannot be parallelized. Besides, the pipeline
architecture can overcome the disadvantages of the memory based architecture style, with an
acceptable hardware overhead.
Single-path Delay Feedback ( SDF )pipeline and Multiple-path Delay Commutator (MDC)
pipeline architectures are the two widely used design styles in pipeline FFT processors. SDF
pipeline FFT [2-5] requires less memory, easy to design, utilizes less than 50% of the
multiplication computation, and its control unit is used in portable devices In view of the
advantages, the Radix-2 SDF pipeline architecture is considered in implementing the FFT
2. International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
324
processor. Three processing elements are used in the architecture of the proposed design of FFT
processor [1]. In this paper, design of 8-bit processing element (PE3) is implemented.
2.FFT ALGORITHM
The DFTXkof an N-point discrete-time signal xnis defined by:
∑
−
=
=
1
0
,
N
n
nk
Nnk WxX , 10 −≤≤ Nk (1)
where N
nkj
eW nk
N
π2−
= is twiddle factor.
The direct implementation of DFT is difficult to realize due to the requirement of more hardware.
Therefore, to reduce its hardware cost and speed up the computation time, FFT was developed.
By using Decimation-in-Time (DIT) or decomposition or Decimation-in-Frequency (DIF), FFT
analyzes an input signal sequence to construct a Signal-Flow Graph (SFG) that can be computed
efficiently. DIF decomposition is employed as it meets the operation of SDF pipeline architecture.
A radix-2 DIF FFT SFG for N=8 is presented in Figure1.
Figure1. Radix-2 Decimation-In-Frequency Fast Fourier Transform Signal Flow Graph for N=8.
To perform FFT computing, complex multiplication scheme [6-11] is used, as a result hardware
cost is increased due to the use of ROM and complex multipliers.
DIF FFT is suitable for hardware implementation as it has a regular SFG and requires less
complex multipliers resulting in smaller area of the chip. For example, an input signal multiplied
by W1
8 in Figure. 1 can be expressed as:
( ) ( ) ( )[ ] 221
8 yxjyxWjyx −++=+ , (2)
Where(x+ jy) denotes a complex discrete-time signal.
3. International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
325
Similarly, the complex multiplication of W3
8 is given by
( ) ( ) ( )[ ] 223
8 yxjyxWjyx +−−=+ (3)
Both the equations (2) and (3) will ease hardware implementation.
From symmetric property of the twiddle factors, the complex multiplications can be one of the
following three operation types:
Type 1: ( ) ( )
( )jxyWjyxW
Nk
N
k
N −=+
−
4
24
N
k
N
<<
(4)
Type 2: ( ) ( )
( )jyxWjyxW
Nk
N
k
N +−=+
−
2
4
3
2
N
k
N
<<
(5)
Type 3: ( ) ( )jxyWjyxW
Nk
N
k
N −−=+
− 4
3
Nk
N
<<
4
3
(6)
Any twiddle factor can be obtained by combining the twiddle-factor primary elements (equations
(4-6)). The three operation types are used to find the twiddle factor required to reduce the size of
the ROM. Additional operation types are given below:
Type 4: ( ) ( )
( )
*
4
+=+
−
jxyWjyxW
kN
N
k
N
4
1
N
k <≤
(7)
Type 5: ( ) ( )
( )
*
2
+−=+
−
jxyWjjyxW
kN
N
k
N
24
N
k
N
<<
(8)
Where * indicates conjugate value. A significant shrinkage of twiddle- factor ROM table can be
obtained, after the third butterfly stage as the complex multiplications will be reduced by using
the five operation types.
3.ARCHITECTURE OF FFT:
A radix-2 8point pipeline FFT processor is presented in Figure 2.The architecture of the pipeline FFT
processor contains three processing elements namely,PE3, PE2 and PE1, a complex constant multiplier and
delay-line buffers. To remove the twiddle-factor ROM, a reconfigurable complex constant multiplier is
used which reduces chip area required and power consumption of FFT processor.
4. International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
N
NW
8N
NW
PROCESSING ELEMENTS
The three processing elements PE1, PE2, and PE3
presented in Figures.3 to 5, respectively. The Processing Elements processes each stage of the
butterfly presented in Figure.1. PE3 stage implements a simple
the sub module for PE2 and PE1 stages.
In Figure 3, Iinand Iout denote
input and output data, respectively. Similarly,
DL_Qinand DL_Qoutare for the imaginary part
respectively. The multiplication by
the input value, multiplication by
Compared to PE2 stage, calculation
multiplications by –j, and
multiplication by followed by
calculation can be done. The cascaded calculations along with multiplexers are used in
calculations and forms a low -cost hardware by saving a bit
computing
.
Figure 3. Architecture of PE3
Figure 2
International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
8 8N
NW 3N
NW
processing elements PE1, PE2, and PE3 of the radix-2 pipeline FFT processor are
presented in Figures.3 to 5, respectively. The Processing Elements processes each stage of the
butterfly presented in Figure.1. PE3 stage implements a simple radix-2 butterfly, and
PE2 and PE1 stages.
the real parts, and Qin and Qoutare the imaginary parts of the
input and output data, respectively. Similarly, DL_Iinand DL_Iout stand for the real parts and
are for the imaginary parts of input and output of the DL buffers,
respectively. The multiplication by –j or 1 is required for PE2 stage. By taking 2’s complement of
the input value, multiplication by -1 in Figure.4 can be done practically.
calculations in PE1 stage are more complex, as it computes the
j, and respectively. Since =- j,
followed by multiplication with –j or the reverse of the previous
calculation can be done. The cascaded calculations along with multiplexers are used in
cost hardware by saving a bit-parallel multiplier for
Figure 3. Architecture of PE3 Figure 4. Architecture of PE2
Figure 2. Radix-2 8 point pipeline FFT processor.
83N
NW
83N
NW
International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
326
8N
2 pipeline FFT processor are
presented in Figures.3 to 5, respectively. The Processing Elements processes each stage of the
, and functions as
the imaginary parts of the
stand for the real parts and
s of input and output of the DL buffers,
or 1 is required for PE2 stage. By taking 2’s complement of
more complex, as it computes the
either the
or the reverse of the previous
calculation can be done. The cascaded calculations along with multiplexers are used in PE1 stage
multiplier for
5. International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
4. PROCESSING ELEMENT
PE3 is the main component in FFT processor as it serves as the sub module for PE2 and PE1
stages. It processes the stage P=3 of the
Hardware implementation of PE3 employs a ten transistor adder and a multiplexer.1
PE3 elements are presented in Figure. 6 and 7 respectively.
Figure 6.Schematic of 1-bit PE3
Figure 5
International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
LEMENT(PE3)
PE3 is the main component in FFT processor as it serves as the sub module for PE2 and PE1
stages. It processes the stage P=3 of the radix-2 8 point DIF FFT butterfly structure in Figure1.
Hardware implementation of PE3 employs a ten transistor adder and a multiplexer.1
PE3 elements are presented in Figure. 6 and 7 respectively.
bit PE3. Figure 7.Schematic of 8
Figure 5.Architecture of PE1.
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PE3 is the main component in FFT processor as it serves as the sub module for PE2 and PE1
2 8 point DIF FFT butterfly structure in Figure1.
Hardware implementation of PE3 employs a ten transistor adder and a multiplexer.1-bit and 8-bit
Figure 7.Schematic of 8-bit PE3.
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5. RESULTS
PE3 element is simulated with ELDO software in Mentor Graphics. The simulated waveforms of
1-bit and 8-bit PE3 are shown in figure 8 and figure 9-10 respectively.
Figure 8. 1-bit PE3 simulated waveforms.
PE3 element processes the stage P=3 of theradix-2 DIF-FFT . It takes Input data (Iin) and Delay
Output(DL_Iout) as the inputs and gives the Output data(Iout) and Input Delay to the next
buffer(DL_Iin) based on the selection line of the multiplexer.
When S0=0 DL_Iin = Iin (9)
Iout = DL_Iout (10)
S0=1 DL_Iin = DL_Iout – Iin (11)
Iout = = DL_Iout + Iin. (12)
From Figure 8,
When So=0, Inputs are Iin= 1010 ; Dl_Iout=0001 then outputs are Dl_Iin=1010 ; Iout = 0001
When So=1, Inputs are Iin=1000 ; Dl_Iout=1011 then outputs are Dl_Iin=0011; Iout=0011
Figure 9Input waveforms of 8-bit PE3.
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Figure 10 Output waveforms of 8-bit PE3.
The power dissipation (from the E-Z wave)of 1-bit PE3 is 0.5517 mwatts and for 8-bit PE3 it is
0.9237mwatts.
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6. CONCLUSIONS
The pipelined FFT architecture contains three processing elements PE1, PE2, PE3. PE3 is the
important element as it serves as a sub module to the other two processing elements PE2 and
PE1.PE3 (1- bit and 8-bit) is implemented using Mentor Graphics tools and the power dissipation
is observed. To implement the proposed pipelined architecture of FFT, PE2 and PE1 are to be
further designed.
REFERENCES
[1] J. W. Cooley and J. W. Tukey, “An algorithm for the machine calculation of complex Fourier series,”
Math. Comput., Vol. 19, pp. 297- 301, Apr. 1965.
[2] S.-Y. Peng, K.-T. Shr, C.-M. Chen, and Y.-H. Huang,“Energy-efficient128∼2048/1536-point
FFTprocessor with resource block mapping for 3 GPP-LTE system,” in Proc. Int. Conf. Green
Circuits Syst.,Jun. 2010.
[3] Nilesh Chide, ShreyasDeshmukh, Prof. P.B. Borole ,” Implementation of OFDM System using IFFT
and FFT”, International Journal of Engineering Research and Applications (IJERA), Vol. 3, Issue 1,
January -February 2013, pp.2009-2014
[4] Taewon Hwang, Chenyang Yang, Gang Wu, Shaoqian Li, and Geoffrey Ye Li,” OFDM and Its
Wireless Applications: A Survey”, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY,
VOL. 58, NO. 4, MAY 2009.
[5] Lokesh C, Dr. Nataraj K. .,” Implementation of an OFDM FFT Kernel for WiMAX”, International
Journal Of Computational Engineering Research, Vol. 2 Issue. 8, Dec. 2012.
[6] Chua-Chin Wang, Jian-Ming Huang, and Hsian-Chang Cheng, “A 2K/8K mode small-area FFT
processor for OFDM demodulation of DVB-T receivers,” IEEE Transactions on Consumer
Electronics, Vol. 51, no. 1, pp. 28-32, Feb. 2005.
[7] C. P. Hung, S. G. Chen, and K. L. Chen, “Design of an efficient variable-length FFT processor,”
Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 2, pp. 23–26, May
2004.
[8] KoushikMaharatna, Eckhard Grass, and Ulrich Jagdhold, “A 64-Point Fourier transform chip for
high-speed wireless LAN application using OFDM,” IEEE Journal of Solid-State Circuits, Vol. 39,
no. 3, pp. 484- 493, Mar. 2004.
[9] Yu-Wei Lin and Chen-Yi Lee,” Design of an FFT/IFFT Processor for MIMO OFDM Systems”, IEEE
Transactions on circuits and systems—I, VOL. 54, NO. 4, APRIL 2007.
[10] Hsii-Fu Lo; Ming-Der Shieh; Chien-Ming Wu, “Design of an efficient FIT processor for DAB
system”, IEEE International Symposium on CircuiB and Systems, Volume: 4, May 2001.
[11] P. DivakaraVarma, Dr. R. Ramana Reddy, “A novel 1-bit full adder design using DCVSL XOR /
XNOR gate and Pass transistor Multiplexers” in International Journal of Innovative Technology and
Exploring Engineering (IJITEE) ISSN: 2278-3075,Volume-2, Issue-4, March 2013 pp: 142-146
9. International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
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AUTHORS
Mary RoselineThota received B.Tech. degreein ECE from GVP College of Engineering
for Women in 2014. Pursing M.Tech(VLSI) in MVGR College of Engineering. Research
interest includes VLSI design methodologies.and Low power VLSI design
MounikaDandamudireceived B.Tech. degree in ECE from Chirala Engineering College in
2014. Pursing M.Tech(VLSI) in MVGR College of Engineering. Research interest
includes VLSI design methodologies and Low power VLSI design.
Dr. R. Ramana Reddydid AMIE in ECE from The Institution of Engineers(India) in 2000,
M.Tech (I&CS) from JNTU College of Engineering, Kakinadain 2002, MBA (HRM &
Marketing) from Andhra University in 2007 and Ph.Din Antennas in 2008 from Andhra
University. He is presently working asProfessor & Head, Dept. of ECE in MVGR College
of Engineering,Vizianagaram. Coordinator, Center of Excellence – Embedded Systems,
Head,National Instruments Lab VIEW academy established in Department of ECE, MVGR College
ofEngineering. Convener of several national level conferences and workshops.Published about 70 technical
papers in National/International Journals / Conferences. He is a member of IETE,IEEE, ISTE, SEMCE (I),
IE, and ISOI. His research interests include Phased Array Antennas,Slotted Waveguide Junctions,
EMI/EMC, VLSI and Embedded Systems.
![International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
DOI: 10.5121/ijci.2016.5435 323
DESIGN OF PROCESSING ELEMENT (PE3) FOR
IMPLEMENTING PIPELINE FFT PROCESSOR
Mary RoselineThota,MounikaDandamudi and R.Ramana Reddy
Department of ECE, MVGR College of Engineering(A),Vizianagaram.
ABSTRACT
Multiplexing is a method by which multiple analog message signals or digital data streams are combined
into one signal over a shared medium. In communication, different multiplexing schemes are used. To
achieve higher data rates, Orthogonal Frequency Division Multiplexing (OFDM) is used due to its high
spectral efficiency. OFDM became a serious alternative for modern digital signal processing methods
based on the Fast Fourier Transform (FFT).The problems with Orthogonal subcarriers can be addressed
with FFT in communication applications. An 8-bit processing element (PE3), used in the execution of a
pipeline FFT processoris designed and presented in this paper. Simulations are carried out using Mentor
Graphics tools in 130nm technology.
KEYWORDS:
Multiplexing, OFDM, FFT processor, Mentor Graphics tools.
1. INTRODUCTION
InDiscrete Signal Processing and telecommunications, Discrete Fourier Transform (DFT) is
essential. Cooley and Tukey [1] proposed FFT to overcome the intensive computation, which has
applications involving OFDM, such as WiMAX, LTE, DSL, DAB/DVB systems, and efficiently
reduced the time complexity from O(N2
) to O (Nlog 2N), where N denotes the FFT size. Different
FFT processors developed for hardware implementation are classified as memory based and
pipeline based architectures [2-4]. Memory-based architecture (single Processing Element (PE)
approach), consists of a principal Processing Element and multiple memory units resulting in
reduced power consumption and less hardware than the pipeline architecture, but have
disadvantages like low throughput, long latency, and cannot be parallelized. Besides, the pipeline
architecture can overcome the disadvantages of the memory based architecture style, with an
acceptable hardware overhead.
Single-path Delay Feedback ( SDF )pipeline and Multiple-path Delay Commutator (MDC)
pipeline architectures are the two widely used design styles in pipeline FFT processors. SDF
pipeline FFT [2-5] requires less memory, easy to design, utilizes less than 50% of the
multiplication computation, and its control unit is used in portable devices In view of the
advantages, the Radix-2 SDF pipeline architecture is considered in implementing the FFT](https://image.slidesharecdn.com/5416ijci35-160907070946/85/Design-of-Processing-Element-PE3-for-Implementing-Pipeline-FFT-Processor-1-320.jpg)
![International Journal on Cybernetics & Informatics (IJCI) Vol. 5, No. 4, August 2016
324
processor. Three processing elements are used in the architecture of the proposed design of FFT
processor [1]. In this paper, design of 8-bit processing element (PE3) is implemented.
2.FFT ALGORITHM
The DFTXkof an N-point discrete-time signal xnis defined by:
∑
−
=
=
1
0
,
N
n
nk
Nnk WxX , 10 −≤≤ Nk (1)
where N
nkj
eW nk
N
π2−
= is twiddle factor.
The direct implementation of DFT is difficult to realize due to the requirement of more hardware.
Therefore, to reduce its hardware cost and speed up the computation time, FFT was developed.
By using Decimation-in-Time (DIT) or decomposition or Decimation-in-Frequency (DIF), FFT
analyzes an input signal sequence to construct a Signal-Flow Graph (SFG) that can be computed
efficiently. DIF decomposition is employed as it meets the operation of SDF pipeline architecture.
A radix-2 DIF FFT SFG for N=8 is presented in Figure1.
Figure1. Radix-2 Decimation-In-Frequency Fast Fourier Transform Signal Flow Graph for N=8.
To perform FFT computing, complex multiplication scheme [6-11] is used, as a result hardware
cost is increased due to the use of ROM and complex multipliers.
DIF FFT is suitable for hardware implementation as it has a regular SFG and requires less
complex multipliers resulting in smaller area of the chip. For example, an input signal multiplied
by W1
8 in Figure. 1 can be expressed as:
( ) ( ) ( )[ ] 221
8 yxjyxWjyx −++=+ , (2)
Where(x+ jy) denotes a complex discrete-time signal.](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)