IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document discusses interrupts and the Intel 8259 interrupt controller chip. It defines interrupt terminology like interrupt service routines and vectors. It describes the basic interrupt processing procedure in CPUs. It provides details on the 8259 chip including its registers, priority modes, initialization sequence and command words. It also gives examples of setting up initialization command words for different 8259 configurations.
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
The document summarizes the proposed design of a power efficient channelizer for software defined radio using VLSI. It discusses the basic architecture of the channelizer which uses a cascaded integrator-comb (CIC) filter block followed by an 8-point fast Fourier transform (FFT). The CIC filter block contains 5 stages of integrators and 5 stages of comb filters with 1 decimator, totaling 8 complete stages. Simulation results and synthesis results showing the internal blocks and 8-point FFT are also presented. The designed channelizer is concluded to have promising decreases in noise and be suitable for real-time software defined radio channels.
The document discusses various addressing modes of the 8051 microcontroller including immediate, register, direct, register indirect, indexed, and bit addressing modes. It describes how each mode accesses memory and provides examples. It also covers special function registers, use of RAM as scratchpad memory, and bit addressing of ports, memory, and registers.
This document discusses the CS14 406: Microprocessor Based Design course taught at Aryanet Institute of Technology. It covers the architecture of the 8086 microprocessor, including its memory segmentation, addressing modes, and hardware specifications. The course objectives are to familiarize students with microprocessor internals and interfacing methods. The course is divided into modules that cover topics such as the 8086 architecture, memory segmentation, instruction sets, and the hardware specifications of the 8086 pinout. Homework assignments include drawing the internal block diagram and pin diagram of the 8086 microprocessor.
The document discusses the addressing modes and instruction set of the 8085 microprocessor. It describes the different addressing modes used in 8085 like immediate, register, memory direct, indirect and implied addressing. It also explains the classification of the 8085 instruction set based on functionality into data transfer, arithmetic, logical, branching, stack/IO and machine control instructions. Furthermore, it provides details about the one-byte, two-byte and three-byte instructions and gives examples of instructions from different categories.
The document provides an overview of the 8085 microprocessor programming model. It describes the hardware model including the ALU, accumulator, registers, buses, and flags. It also discusses the programming model, instruction set classification including data transfer, arithmetic, logical, and branching operations. Finally, it covers instruction word sizes, opcode format, and data formats like ASCII, BCD, signed and unsigned integers.
This document contains details of a student's microcontroller lab tasks, including the student's name, registration number, course code, and instructor details. It also includes 8 questions involving assembly language programs to perform tasks like arithmetic operations, data transfers, and conversions. The programs are written in assembly language for the 8051 microcontroller and include steps to test the programs using a simulator.
The document discusses interrupts and the Intel 8259 interrupt controller chip. It defines interrupt terminology like interrupt service routines and vectors. It describes the basic interrupt processing procedure in CPUs. It provides details on the 8259 chip including its registers, priority modes, initialization sequence and command words. It also gives examples of setting up initialization command words for different 8259 configurations.
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
The document summarizes the proposed design of a power efficient channelizer for software defined radio using VLSI. It discusses the basic architecture of the channelizer which uses a cascaded integrator-comb (CIC) filter block followed by an 8-point fast Fourier transform (FFT). The CIC filter block contains 5 stages of integrators and 5 stages of comb filters with 1 decimator, totaling 8 complete stages. Simulation results and synthesis results showing the internal blocks and 8-point FFT are also presented. The designed channelizer is concluded to have promising decreases in noise and be suitable for real-time software defined radio channels.
The document discusses various addressing modes of the 8051 microcontroller including immediate, register, direct, register indirect, indexed, and bit addressing modes. It describes how each mode accesses memory and provides examples. It also covers special function registers, use of RAM as scratchpad memory, and bit addressing of ports, memory, and registers.
This document discusses the CS14 406: Microprocessor Based Design course taught at Aryanet Institute of Technology. It covers the architecture of the 8086 microprocessor, including its memory segmentation, addressing modes, and hardware specifications. The course objectives are to familiarize students with microprocessor internals and interfacing methods. The course is divided into modules that cover topics such as the 8086 architecture, memory segmentation, instruction sets, and the hardware specifications of the 8086 pinout. Homework assignments include drawing the internal block diagram and pin diagram of the 8086 microprocessor.
The document discusses the addressing modes and instruction set of the 8085 microprocessor. It describes the different addressing modes used in 8085 like immediate, register, memory direct, indirect and implied addressing. It also explains the classification of the 8085 instruction set based on functionality into data transfer, arithmetic, logical, branching, stack/IO and machine control instructions. Furthermore, it provides details about the one-byte, two-byte and three-byte instructions and gives examples of instructions from different categories.
The document provides an overview of the 8085 microprocessor programming model. It describes the hardware model including the ALU, accumulator, registers, buses, and flags. It also discusses the programming model, instruction set classification including data transfer, arithmetic, logical, and branching operations. Finally, it covers instruction word sizes, opcode format, and data formats like ASCII, BCD, signed and unsigned integers.
This document contains details of a student's microcontroller lab tasks, including the student's name, registration number, course code, and instructor details. It also includes 8 questions involving assembly language programs to perform tasks like arithmetic operations, data transfers, and conversions. The programs are written in assembly language for the 8051 microcontroller and include steps to test the programs using a simulator.
The document provides an overview of assembly language programming for the 8085 microprocessor. It discusses the 8085 programming model including registers, flags, and addressing modes. It also describes the instruction set categories and provides examples of common instruction types like data transfer, arithmetic, logical, and branching instructions. Sample assembly language programs are shown to add two numbers and handle results larger than 8 bits.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
Logical instruction of 8085
Instruction Set of 8085
Classification of Instruction Set
Logical Instructions
AND, OR, XOR
Logical Instructions
Summary Logical Group
The document provides information about the 8085 instruction set including:
1. The different addressing modes used by 8085 such as direct, register, indirect, immediate, and implied addressing.
2. Descriptions of common instruction types for data transfer, arithmetic, logical operations, branching and machine control.
3. Summaries of instructions for moving data, performing arithmetic, logical operations, comparing values, rotating bits, branching conditionally, using the stack, input/output and enabling interrupts.
Experiment C.1 tests examples C.1 to C.11 by:
1. Moving a 23-bit constant to the extended data-page pointer register using direct addressing mode.
2. Loading the accumulator register with data from an address pointed to by an auxiliary register using indirect addressing mode.
3. Loading the accumulator register with two words from addresses pointed to by two auxiliary registers using dual indirect addressing mode.
The document discusses the different addressing modes of the 8085 microprocessor. It defines addressing modes as the ways that an instruction's operands can be accessed. The 5 addressing modes of the 8085 are: 1) Immediate, where data is included in the instruction, 2) Register, where operands are in registers, 3) Direct, where the operand's address is in the instruction, 4) Register Indirect, where the operand's address is stored in a register pair, and 5) Implied, where the opcode specifies the operand without an explicit address. Examples are provided for each addressing mode.
The document discusses instruction set and addressing modes of the 8085 microprocessor. It defines an instruction as a binary pattern that performs a specific function. The 8085 has 246 instructions represented by 8-bit opcodes. There are 5 addressing modes - immediate, register, direct, indirect and implicit. Instructions are also classified by size and operation. The document outlines different types of instructions like data transfer, arithmetic, logical, branching and control instructions.
This document discusses different addressing modes used in the 8051 microcontroller architecture, including immediate, direct, register, and indirect addressing modes. Immediate addressing encodes the data as part of the instruction itself. Direct addressing retrieves data directly from another memory location. Register addressing uses register names as part of the opcode. Indirect addressing provides flexibility by allowing the contents of a register to specify the memory location of the operand.
The document provides information about the Intel 8085 microprocessor. Some key details include:
- It is an 8-bit processor that operates on a 5V power supply with a maximum clock frequency of 3MHz.
- It has 40 pins and uses a multiplexed address/data bus. It can access 64KB of memory space and 256 I/O ports.
- It has one accumulator, flag, and six general purpose registers. It supports various addressing modes and 74 instructions.
- Interrupts include TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR. Serial I/O is also supported directly.
-
The document discusses input/output (I/O) mapping schemes and the Intel 8255 Programmable Peripheral Interface (PPI) chip. It describes two I/O mapping schemes - memory mapped I/O and I/O mapped I/O. It then discusses the Intel 8255 PPI chip, its features, operating modes (I/O and BSR modes), and how to program it. Examples are provided of writing control words to configure the ports and a program to read from two ports and write the result to the third port.
This document provides instructions for advanced operations in the 8085 microprocessor, including instructions for 16-bit data transfers using the HL register pair, instructions related to 16-bit registers, and advanced arithmetic instructions. It describes instructions like LHLD, SHLD, XCHG for 16-bit transfers, SPHL and XTHL for the stack pointer, PCHL for the program counter, and arithmetic instructions like ACI, ADC, SBB, SBI, and DAD for 16-bit addition and subtraction. An example program is provided to add two 16-bit numbers using DAD.
Assembler directives and basic steps ALP of 8086Urvashi Singh
The document discusses various assembler directives used in assembly language programming. It describes directives like DB, DW, DD, DQ, DT for data declaration; ASSUME to define logical segments; END, ENDP, ENDS to mark ends; EQU to define constants; PROC and ENDP to define procedures; ORG to set the location counter; SEGMENT to define logical segments; GROUP, INCLUDE, EVEN, and ALIGN for segment organization; EXTRN and PUBLIC for external references; and TYPE and PTR for defining variable types. The directives provide necessary information to the assembler to understand assembly language programs and generate machine code.
Data transfer instruction set of 8085 micro processorvishalgohel12195
Data transfer instruction set of 8085 micro processor
WHAT IS INSTRUCTION?
CLASSIFICATION OF INSTRUCTION.
DATA TRANSFER INSTRUCTION.
EXAMPLES
PROGRAMME OF DATA TRANFER INSTRUCTION
This document summarizes the instruction set of the 8085 microprocessor. It is divided into 5 categories: data transfer operations, arithmetic operations, logical operations, branching operations, and machine control operations. The data transfer operations include instructions to move data between registers and memory locations. The arithmetic operations allow adding, subtracting, incrementing and decrementing values. The logical operations perform AND, OR, XOR and other logical functions. Branching operations allow unconditional and conditional jumps to alter the program flow. Machine control instructions control execution flow.
The document summarizes the branch group instructions of the 8085 microprocessor. It describes jump instructions like JMP, conditional jump instructions, and the PCHL instruction. It also covers CALL and return instructions like CALL, RET, and conditional call and return instructions. Finally, it discusses restart instructions like RST that can be used as software interrupts to transfer program execution to specific restart locations.
This document discusses microprocessor instructions and data formats used by the 8085 microprocessor. It describes the different types of instructions based on byte size - 1-byte, 2-byte, and 3-byte instructions. It explains the opcode and operand parts of instructions. It also discusses various data formats used like ASCII, BCD, hexadecimal, signed and unsigned integers.
This document summarizes the flags register in 8086 processors. It has two main sections. The first section explains that the flags register is 16 bits wide and contains status and control flags that indicate the current state of the processor. The second section details the different types of flags, including status flags like carry, parity, zero, and overflow flags, and control flags like trap, interrupt, and direction flags. It provides details on the purpose and location of each individual flag in the 16-bit register.
The document discusses stack operations in the 8085 microprocessor. It contains the following key points:
1. The 8085 uses a last-in, first-out (LIFO) stack implemented in RAM. It has two stack instructions: PUSH pushes data onto the stack, and POP pops data off the stack into registers.
2. The stack pointer (SP) register points to the top of the stack. It is decremented by PUSH and incremented by POP.
3. Subroutines use the stack to store the return address by pushing the program counter before branching to the subroutine. The return instruction POPs the address back to resume the main program.
4. T
This document provides information about programming models and assembly language programming for the 8085 microprocessor. It discusses the various addressing modes, instruction set, data transfer instructions, arithmetic instructions, logical instructions, branching instructions, and stack and subroutine concepts for the 8085. Several examples of assembly language programs for tasks like addition, subtraction, multiplication, and data transfer are also included.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document provides an overview of assembly language programming for the 8085 microprocessor. It discusses the 8085 programming model including registers, flags, and addressing modes. It also describes the instruction set categories and provides examples of common instruction types like data transfer, arithmetic, logical, and branching instructions. Sample assembly language programs are shown to add two numbers and handle results larger than 8 bits.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
Logical instruction of 8085
Instruction Set of 8085
Classification of Instruction Set
Logical Instructions
AND, OR, XOR
Logical Instructions
Summary Logical Group
The document provides information about the 8085 instruction set including:
1. The different addressing modes used by 8085 such as direct, register, indirect, immediate, and implied addressing.
2. Descriptions of common instruction types for data transfer, arithmetic, logical operations, branching and machine control.
3. Summaries of instructions for moving data, performing arithmetic, logical operations, comparing values, rotating bits, branching conditionally, using the stack, input/output and enabling interrupts.
Experiment C.1 tests examples C.1 to C.11 by:
1. Moving a 23-bit constant to the extended data-page pointer register using direct addressing mode.
2. Loading the accumulator register with data from an address pointed to by an auxiliary register using indirect addressing mode.
3. Loading the accumulator register with two words from addresses pointed to by two auxiliary registers using dual indirect addressing mode.
The document discusses the different addressing modes of the 8085 microprocessor. It defines addressing modes as the ways that an instruction's operands can be accessed. The 5 addressing modes of the 8085 are: 1) Immediate, where data is included in the instruction, 2) Register, where operands are in registers, 3) Direct, where the operand's address is in the instruction, 4) Register Indirect, where the operand's address is stored in a register pair, and 5) Implied, where the opcode specifies the operand without an explicit address. Examples are provided for each addressing mode.
The document discusses instruction set and addressing modes of the 8085 microprocessor. It defines an instruction as a binary pattern that performs a specific function. The 8085 has 246 instructions represented by 8-bit opcodes. There are 5 addressing modes - immediate, register, direct, indirect and implicit. Instructions are also classified by size and operation. The document outlines different types of instructions like data transfer, arithmetic, logical, branching and control instructions.
This document discusses different addressing modes used in the 8051 microcontroller architecture, including immediate, direct, register, and indirect addressing modes. Immediate addressing encodes the data as part of the instruction itself. Direct addressing retrieves data directly from another memory location. Register addressing uses register names as part of the opcode. Indirect addressing provides flexibility by allowing the contents of a register to specify the memory location of the operand.
The document provides information about the Intel 8085 microprocessor. Some key details include:
- It is an 8-bit processor that operates on a 5V power supply with a maximum clock frequency of 3MHz.
- It has 40 pins and uses a multiplexed address/data bus. It can access 64KB of memory space and 256 I/O ports.
- It has one accumulator, flag, and six general purpose registers. It supports various addressing modes and 74 instructions.
- Interrupts include TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR. Serial I/O is also supported directly.
-
The document discusses input/output (I/O) mapping schemes and the Intel 8255 Programmable Peripheral Interface (PPI) chip. It describes two I/O mapping schemes - memory mapped I/O and I/O mapped I/O. It then discusses the Intel 8255 PPI chip, its features, operating modes (I/O and BSR modes), and how to program it. Examples are provided of writing control words to configure the ports and a program to read from two ports and write the result to the third port.
This document provides instructions for advanced operations in the 8085 microprocessor, including instructions for 16-bit data transfers using the HL register pair, instructions related to 16-bit registers, and advanced arithmetic instructions. It describes instructions like LHLD, SHLD, XCHG for 16-bit transfers, SPHL and XTHL for the stack pointer, PCHL for the program counter, and arithmetic instructions like ACI, ADC, SBB, SBI, and DAD for 16-bit addition and subtraction. An example program is provided to add two 16-bit numbers using DAD.
Assembler directives and basic steps ALP of 8086Urvashi Singh
The document discusses various assembler directives used in assembly language programming. It describes directives like DB, DW, DD, DQ, DT for data declaration; ASSUME to define logical segments; END, ENDP, ENDS to mark ends; EQU to define constants; PROC and ENDP to define procedures; ORG to set the location counter; SEGMENT to define logical segments; GROUP, INCLUDE, EVEN, and ALIGN for segment organization; EXTRN and PUBLIC for external references; and TYPE and PTR for defining variable types. The directives provide necessary information to the assembler to understand assembly language programs and generate machine code.
Data transfer instruction set of 8085 micro processorvishalgohel12195
Data transfer instruction set of 8085 micro processor
WHAT IS INSTRUCTION?
CLASSIFICATION OF INSTRUCTION.
DATA TRANSFER INSTRUCTION.
EXAMPLES
PROGRAMME OF DATA TRANFER INSTRUCTION
This document summarizes the instruction set of the 8085 microprocessor. It is divided into 5 categories: data transfer operations, arithmetic operations, logical operations, branching operations, and machine control operations. The data transfer operations include instructions to move data between registers and memory locations. The arithmetic operations allow adding, subtracting, incrementing and decrementing values. The logical operations perform AND, OR, XOR and other logical functions. Branching operations allow unconditional and conditional jumps to alter the program flow. Machine control instructions control execution flow.
The document summarizes the branch group instructions of the 8085 microprocessor. It describes jump instructions like JMP, conditional jump instructions, and the PCHL instruction. It also covers CALL and return instructions like CALL, RET, and conditional call and return instructions. Finally, it discusses restart instructions like RST that can be used as software interrupts to transfer program execution to specific restart locations.
This document discusses microprocessor instructions and data formats used by the 8085 microprocessor. It describes the different types of instructions based on byte size - 1-byte, 2-byte, and 3-byte instructions. It explains the opcode and operand parts of instructions. It also discusses various data formats used like ASCII, BCD, hexadecimal, signed and unsigned integers.
This document summarizes the flags register in 8086 processors. It has two main sections. The first section explains that the flags register is 16 bits wide and contains status and control flags that indicate the current state of the processor. The second section details the different types of flags, including status flags like carry, parity, zero, and overflow flags, and control flags like trap, interrupt, and direction flags. It provides details on the purpose and location of each individual flag in the 16-bit register.
The document discusses stack operations in the 8085 microprocessor. It contains the following key points:
1. The 8085 uses a last-in, first-out (LIFO) stack implemented in RAM. It has two stack instructions: PUSH pushes data onto the stack, and POP pops data off the stack into registers.
2. The stack pointer (SP) register points to the top of the stack. It is decremented by PUSH and incremented by POP.
3. Subroutines use the stack to store the return address by pushing the program counter before branching to the subroutine. The return instruction POPs the address back to resume the main program.
4. T
This document provides information about programming models and assembly language programming for the 8085 microprocessor. It discusses the various addressing modes, instruction set, data transfer instructions, arithmetic instructions, logical instructions, branching instructions, and stack and subroutine concepts for the 8085. Several examples of assembly language programs for tasks like addition, subtraction, multiplication, and data transfer are also included.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document summarizes an iris recognition system that uses phase-based matching. The system first acquires iris images, then performs preprocessing including localization of the iris and pupil boundaries and normalization. It then performs phase-based image matching using techniques like phase-only correlation to calculate a matching score and determine if two iris images match. The system is evaluated using a database of iris images, demonstrating efficient matching performance of the proposed algorithm.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
El documento habla sobre navegadores y buscadores. Explica que los navegadores como Google Chrome, Mozilla Firefox e Internet Explorer nos permiten acceder a Internet y navegar entre páginas web. Los buscadores como Google son páginas que permiten realizar búsquedas en la red. También discute los usos educativos de los blogs como estimular la expresión libre de estudiantes y facilitar el intercambio de ideas.
Este documento presenta información sobre varios temas relacionados con la búsqueda de información en Internet. Explica los tipos de buscadores como los motores de búsqueda principales como Google y Bing, los metabuscadores que permiten buscar en varios motores a la vez, y los directorios que organizan sitios web por categorías. También resume brevemente la historia de los libros digitales y electrónicos, y define diferentes tipos de obras de consulta como diccionarios, enciclopedias y atlas.
La placa madre es el componente principal de la unidad de procesamiento que mantiene la configuración del PC y conecta los diferentes componentes como la memoria RAM, tarjeta de video, puertos USB, ranuras de expansión PCI, entre otros. Algunos de los puertos y conectores comunes en una placa madre incluyen PS/2, IDE, fuente de alimentación, AGP, VGA y tarjeta de red.
El documento describe las fórmulas para calcular el área de varias figuras planas comunes como cuadrados, rectángulos, rombos, romboides, triángulos, polígonos regulares y círculos. También incluye ejercicios para practicar hallando el área de estas figuras usando las fórmulas correspondientes.
Este documento presenta 10 preguntas de opción múltiple sobre temas como los derechos humanos fundamentales, la dignidad, la búsqueda de soluciones conciliadoras y la construcción de la paz y la verdad a través del diálogo respetuoso. Las preguntas cubren conceptos como vivir con dignidad, los derechos a un nivel de vida adecuado y saludable, la importancia de la actitud conciliadora y el diálogo con serenidad, respeto y amor.
La constelación de Escorpio se originó en la antigua Grecia, donde se reconocían 24 estrellas que formaban la figura de un escorpión. En la mitología griega, la diosa Artemis colocó un escorpión en el cielo para recompensarlo por haber picado y matado al gigante Orión después de que intentó violarla. La constelación actual de Escorpio contiene varias estrellas brillantes y fue establecida formalmente por la Unión Astronómica Internacional.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
DESIGN AND VHDL IMPLEMENTATION OF 64-POINT FFT USING TWO STRUCTURE 8-POINT FF...Journal For Research
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
ISSN 2347-2251
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Iaetsd computational performances of ofdm usingIaetsd Iaetsd
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High Speed Area Efficient 8-point FFT using Vedic MultiplierIJERA Editor
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Bm33388392
1. Amos H Jeeva Oli, R Rani Hemamalini / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.388-392
388 | P a g e
Part-by-Part-Evaluation-on-Arrival approach involving modified
eight point radix-2 FFT/IFFT for an OFDM transceiver to reduce
latency
Amos H Jeeva Oli1
, R Rani Hemamalini2
1
Research Scholar, St. Peter‟s University, Chennai. India
2
Professor & Head, Department of ECE, St. Peter‟s College of Engineering & Technology, Chennai, India
Abstract
An OFDM transceiver which will have
the FFT/IFFT as an integral part will suffer
latency due to the latter. This paper reduces the
latency for a OFDM transceiver involving a 512
point FFT/IFFT function by using a modified 8
point radix2 FFT/IFFT. It performs Part-by-
Part-Evaluation-on-Arrival instead of evaluating
FFT after the arrival of a full set of 512 input
samples. This approach significantly reduces the
latency in the OFDM transceiver and usage of a
modified 8 point radix 2 FFT/IFFT as the basic
unit to evaluate the large 512 point FFT/IFFT
also reduces the computational requirements.
The same has been implemented in a Spartan 3
FPGA.
Keyword: FFT, IFFT, PPEA, Symbol Combiner,
latency, OFDM transceiver
1. Introduction
FFT and IFFT functions are the central and
integral part of any OFDM system. FFT and IFFT
functions are used to multiplex low data rate signals
over orthogonal carriers to mitigate ISI which is
severe when the data rate is high in multipath
propagation environ. But the functions can be
performed only after the arrival of all the inputs. So
the FFT and IFFT is modified to accommodate Part-
by-part-evaluation-on-arrival to reduce the initial
waiting time. The FFT or IFFT functions for a large
value of N can become very complex if the PPEA
approach is applied. So the large FFT or IFFT is
performed by involving smaller FFT or IFFTs.
Among the smaller FFTs 4 point or 8 point FFTs or
IFFTs are preferred, since they use very less number
of or no twiddle factor multiplications. It should be
noted that the a 4 point FFT will involve only
complex additions while 8 point FFT will involve
only complex one multiplication.
A N2
point FFT can be realized by
decomposing it into a 2 dimensional structure of N
point FFTs [1], shift and add multiplier can be used
to avoid using a RAM or ROM, for example a
64point FFT can be realised by decomposing it into
a 2 dimensional structure of 8 point FFTs. Two
cascaded parallel/pipelined radix 4 Butterfly Unit
can form a R-16 butterfly processing element, this
facilitates low complexity realization of radix 16
butterfly operation and high operation speed.[2]
FFT processor for OFDM systems can be made
efficient by using Parallel Butterfly algorithm, for
example using a Dual Butterfly algorithm gives
high throughput and requires relatively small
areas[3]. FFT computations can be reconstructed
into a scalable array structure based on an 8 point
Butterfly Unit – the array structure can easily
expand along both the horizontal and vertical
dimensions for any point FFT computation [4].
There are applications when a non power of two
FFT would need to be performed, the corresponding
algorithm is complex, a power of two algorithms
can be used to perform it [5]. Normally zero valued
inputs outnumber the non-zero valued input in the
FFT block; there are pruning algorithms that are
available, especially dynamically partial
reconfigurable transform decompositions FFT
which is architecturally efficient for FPGA
implementation [6].
A fixed point 16 bit word width 64 point
FFT/IFFT processor, that is a OFDM based
IEEE802.11a wireless LAN baseband processor
realised by decomposing it into a 2 dimensional
structure of 8 point FFT is realised using a shift and
add multiplier without any RAM or ROM[7]. Hence
from an 8 point FFT a higher input FFT can be
easily developed. OFDM can also occur in 2 MIMO
OFDM modes namely, space frequency block coded
OFDM and space division multiplexed OFDM [8].
A frequency hopping OFDM was developed
allowing more flexibility, lower complexity, better
acquisition and synchronization performance [9]
where the FH was based on sampling rate
conversion. OFDM, FFT and symbol processing
need high frequency clock rates hence needing high
electrical power but minimizing electrical power is
more critical that the number of implemented logic
gates [10]. Demodulation of the OFDM signal can
also be performed in the discrete time signalling
domain before ADC after FFT operation, since it
significantly reduces the required number of bits in
the ADC while increasing receiver linearity [11] &
[12]. Usage of low power register files and resource
sharing techniques reduce the power consumed
[13].A flexible adaptivity of internal bit vector
2. Amos H Jeeva Oli, R Rani Hemamalini / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.388-392
389 | P a g e
widths when a IFFT/FFT is performed was analysed
[14].
2. Symbol Combiner
Conventionally, if FFT/IFFT needs to be
performed on the incoming symbols they are
received and are either shuffled or not shuffled
depending on whether decimation is done in the
time domain or frequency domain. In this paper
decimation in the time domain is preferred, hence
incoming symbols are operated upon and 8 different
real and imaginary outputs are generated & stored
only to be retrieved after a given time delay to be
added with the 8 real and imaginary outputs
generated then. The real and imaginary values
which are accumulated at 8 different equi-spaced
instants of time are normally stored and retrieved in
& from a memory with negligible retrieval and re-
storage time. The tables given below define how
symbol combiner operates on a given input symbol.
If the input to the symbol combiner of a FFT
function at a given instant of time is given by xr+jxi,
then the 8 outputs of the symbol combiner will be
xr:(0), xi:(1), -xr:(2), -xi:(3), 0.707*(xr+xi):(4),
0.707*(xr-xi):(5), -0.707(xr+xi):(6) and -0.707(xr-
xi):(7). If the inputs are denoted as a, b, c, d, e, f, g
and h and the outputs as A, B, C, D, E, F and H the
below table describes how every input goes to the
symbol combiner and produces values that are
routed to the corresponding output, that is which
output of the symbol combiner is assigned and
accumulated location, both for real and imaginary.
FFT Real Input
O/P a b c d e f g h
A 0 0 0 0 0 0 0 0
B 0 4 1 7 2 6 3 5
C 0 1 2 3 0 1 2 3
D 0 7 3 4 2 5 1 6
E 0 2 0 2 0 2 0 2
F 0 6 1 5 2 4 3 7
G 0 3 2 1 0 3 2 1
H 0 5 3 6 2 7 1 4
FFT Imaginary Input
O/P a b c d e f g h
A 1 1 1 1 1 1 1 1
B 1 7 2 6 3 5 0 4
C 1 2 3 0 1 2 3 0
D 1 6 0 7 3 4 2 5
E 1 3 1 3 1 3 1 3
F 1 5 2 4 3 7 0 6
G 1 0 3 2 1 0 3 2
H 1 4 0 5 3 6 2 7
Similarly the inputs for a IFFT function is given by
A, B, C, D, E, F and H and the outputs by a, b, c, d,
e, f, g and h.
IFFT Real Input
O/P A B C D E F G H
a 0 0 0 0 0 0 0 0
b 0 5 3 6 2 7 1 4
c 0 3 2 1 0 3 2 1
d 0 6 1 5 2 4 3 7
e 0 2 0 2 0 2 0 2
f 0 7 3 4 2 5 1 6
g 0 1 2 3 0 1 2 3
h 0 4 1 7 2 6 3 5
3. Amos H Jeeva Oli, R Rani Hemamalini / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.388-392
390 | P a g e
The relationship between the inputs of symbol
combiner with the outputs are given by the tables
above and below for the real and imaginary parts
separately respectively.
IFFT Imaginary Input
O/P A B C D E F G H
a 1 1 1 1 1 1 1 1
b 1 4 0 5 3 6 2 7
c 1 0 3 2 1 0 3 2
d 1 5 2 4 3 7 0 6
e 1 3 1 3 1 3 1 3
f 1 6 0 7 3 4 2 5
g 1 2 3 0 1 2 3 0
h 1 7 2 6 3 5 0 4
When the inputs of a FFT/IFFT function arrive with
a time gap, the values generated by the symbol
combiner will be stored, retrieved from a fast access
memory and accumulated with the current set of
symbol combiner outputs and restored.
3. Part-by-part evaluation on arrival
approach.
The DFT operation which is given below is
normally performed using FFT algorithm. But one
of the features of the algorithm is that the inputs or
outputs are shuffled and hence for the function to
start, all the inputs should have arrived hence there
is latency involved. In order to overcome this, the
FFT and IFFT can be modified. Radix-2 FFT can
be modified to adapt to Part-by-Part Evaluation-on-
Arrival approach in order to overcome this latency.
Using Radix -2 FFT for N=4 as the basic operation
in the divide and conquer approach will alleviate the
4 point operation from multiplication, whereas while
using Radix-2 FFT for N=8 as the basic operation
will cause the 8 point operation to perform one
multiplication. Then 4 point operations or 8 point
operations can be used to perform a FFT for large
value of N. The reason and the motivation for
changing the FFT algorithm is to accommodate
evaluation of FFT on arrival, so the calculations
need to take place quickly hence the need for
reducing the multiplications. That is why the FFT
was modified to both reduce multiplication and
evaluate FFT on arrival.
Using a 4 point modified FFT as the basic FFT unit
to perform a large N FFT has it advantage that it
involves no multiplication. But to realize a large
valued FFT the number of stages will increase. If
the number of stages increases the number of on-
chip RAM accesses to fetch the twiddle factors
increases. To reduce the number of RAM accesses
(though relatively fast as it is on-chip) 8 point
modified FFT is chosen as the basic FFT function.
One inherent disadvantage is that a multiplier should
be part of the symbol combiner which is in turn a
part of the PPEA unit.
The PPEA unit involves a RAM which stores
outputs of the symbol combiner as the inputs arrive.
The stored data is periodically retrieved to be added
to the symbol combiner outputs and stored back.
For a 512 point FFT the input stage that is the PPEA
unit will endeavour to perform 8 point FFT between
inputs that arrive at 0,64, 128,192, 256, 320, 384,
448 instants of time. Since this is evaluation on
arrival every input is operated on and they are stored
in the memory locations that correspond to the input
numbered above. This is done in order to perform
64 8 point FFTs. As any one of the above inputs
arrive, the data stored in the locations numbered as
above will be retrieved to perform one more step in
the 8 point FFT. Since evaluation is done on arrival
before one 8 point FFT is performed it will involve
RAM read and write at least 7 times. But this does
not cause a delay since they are done as the input is
arriving and symbols are being assigned.
4. Divide and Conquer approach
In order to realize a 512 point FFT, by
„divide and conquer‟ approach, it can be factored as
8x8x8. The input samples as they arrive undergo an
8 point FFT. The approach is similar to performing
radix-8 but the difference lies in the fact that FFT or
IFFT function is not started after the arrival of all
the inputs but the function starts even as the first
input arrives. The input samples as they arrive
PPEA Unit
Symbol
Combiner
16 adders
(8-real,
8-imag)
2
R
A
M
(1-real,
1- imag)
Input
4. Amos H Jeeva Oli, R Rani Hemamalini / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.388-392
391 | P a g e
undergo 8 point FFT operations, but the 8 points
they correspond with will be 64 (512/8) input
samples away, hence the symbol combining is
performed and the results are stored temporarily to
be retrieved and added to the symbol combiner
outputs at the instants of arrival of consecutive
inputs samples that are 64 samples away.
0 1 2 … 511
0 8 16 …. 504
1 9 17 …. 505
2 10 18 …. 506
3 11 19 …. 507
4 12 20 …. 508
5 13 21 …. 509
6 14 22 ….. 510
7 15 23 …. 511
0 64 128 … 448
8 72 136 … 456
16 80 144 … 464
24 88 152 … 472
32 96 160 … 480
40 104 168 … 488
48 112 176 … 496
56 120 184 … 504
1 65 129 … 449
9 73 137 … 457
17 81 145 … 465
25 89 153 …. 473
33 97 161 … 481
41 105 169 … 489
49 113 177 … 497
57 121 185 … 505
.
.
.
7 71 135 … 455
15 79 143 …. 463
23 87 151 ….. 471
31 95 159 ….. 479
39 103 167 ….. 487
47 111 175 ….. 495
55 119 183 ….. 503
63 127 191 ….. 511
The above tables clearly show that a 512 point FFT
is first divided to form eight 64 point FFTs. Every
64 point FFT can be further divided into eight 8
point FFTs. A eight point FFT will have to be
performed row wise in a 8 x 8 matrix, followed by
multiplication of every element in the matrix by
WN
r1c1
, where N=8 and r1=0 to 7 and c1=0 to 7.
This is in turn followed by performing a column
wise 8 point FFT. This, though it appears like any
„divide and conquer‟ approach is done with the help
of the modified 8 point radix 2 FFT, hence can be
performed as and when the final entries in the 8
locations of interest is made. This in turn will
reduce the latency in waiting for a stage to complete
and a partial PPEA is being used.
When this 3 step procedure of performing
8 row wise 8 point FFTs, followed by multiplication
by twiddle factors and 8 column wise 8 point FFTs
is completed a 64 point FFT has been performed.
When this 3 step procedure is repeated eight 64
point FFT are performed. The results of these FFTs
are stored in a 64 x 8 matrix for further
manipulation. Conversion of eight 64 point FFTs in
a 512 point FFT can be done with a help of a 2 step
procedure namely, multiplying every entry in the 8 x
64 matrix is multiplied by a twiddle factor WN
r1c1
,
where N=64 and r1=0 to 7 and c1=0 to 63 and
following it by eight column wise 8 point FFTs. In
the 3 step procedure to evaluate the 64 point FFTs
and 2 step procedure to convert eight 64 point FFTs
into 512 point FFT wherever 8 point FFTs are
performed it is done with the help of the PPEA unit.
5. Conclusion
The 512 point FFT/IFFT using the PPEA
unit was realized in a Xilinx Spartan 3 FPGA. The
usage of the smaller-sized eight-point FFTs for
calculating the large 512-point FFT reduced the
complexity of the FFT/IFFT function. The usage of
the Part-by-Part-Evaluation-on-Arrival approach
reduced the difference between time of arrival of the
last of the input samples and the time at which the
first output is calculated. This reduces the latency in
the calculation of FFT/IFFT. This reduction in
computational complexity and latency is evidenced
in the device utilization details and the timing
summary observed during synthesis based on the
Spartan 3 target device chosen.
References
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5. Amos H Jeeva Oli, R Rani Hemamalini / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.388-392
392 | P a g e
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Authors’ Information
Amos H Jeeva Oli is a research scholar of St. Peter‟s
University, who completed Bachelor‟s in
Electronics and Communication Engineering in
1995 and Masters in Microwave and Optical
Engineering in 2003. He is currently working in R
M D Engineering College as Associate
Professor/ECE. He has published papers in refereed
International journals.
R Rani Hemamalini, is Professor and Head of
Electronics and Communication Engineering
department in St. Peter‟s College of Engineering
and Technology. She completed Bachelors in
Electrical and Electronics Engineering in 1990,
Masters in Process Controls in 1997 and
Instrumentation and Doctorate in Control
Engineering in 2003. She has published over 30
papers in refereed International journals, involved in
research in foreign universities. She has been
involved in sponsored research over the last 10
years.