Embedded Server Based Remote Industrial Automation Control
This document describes an embedded server project for remote industrial automation and control using a dsPIC33FJ64GP802 microcontroller. Key aspects include:
- The microcontroller runs a web server from an SD card to allow remote monitoring and control of up to 4 digital outputs via a web browser.
- An Ethernet interface connects the system to the internet to enable remote access and file transfer capabilities.
- Relays are controlled through a ULN2803 driver circuit connected to digital ports on the microcontroller.
- The system provides capabilities for remote monitoring, control, data logging and updating via a built-in web server without requiring a separate computer.
A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC...IDES Editor
Modern embedded systems are built around the soft
core processors implemented on FPGA. The FPGAs being
capable of implementing custom hardware blocks giving the
advantage of ASICs, and allowing the implementation of
processor platform are resulting in powerful Configurablesystem
on chip(C-SoC)platforms. The Microchip’s PIC
microcontroller is very widely used microcontroller
architecture across various embedded systems. The
implementation of such core on FPGA is very much useful in
CSOC based embedded systems. This type of designs can be
widely used in those controlling fields demanding low power
consumption and high ratio of performance to price. In this
project a reduced instruction set computer (RISC) CPU IP
core whose instructions are compatible with the Microchip
PIC16C6Xseries of microcontrollers is implemented in VHDL.
The core is based on 8-bit RISC architecture and top-Down
design methodology is used in developing the core. The RISC
CPU core is based on Harvard architecture with 14-bit
instruction length and 8-bit data length and two-stage
instruction pipeline. The architecture will be designed aiming
at single cycle execution of the instructions, except those
related to program branches. Since this type of CPU based on
RISC architecture, there are only 35 reduced instructions in
its instruction set, which are easy to be learned and used. The
performance of the 8-bit RISC CPU is better than those of
CPUs which are based on CISC architecture. Modelsim Xilinx
Edition (MXE) will be used simulation and functional
verification. The Xilinx Spartan-3E FPGAs will be used
synthesis and timing analysis. The results will be verified on
chip with chipscope tool.
A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC...IDES Editor
Modern embedded systems are built around the soft
core processors implemented on FPGA. The FPGAs being
capable of implementing custom hardware blocks giving the
advantage of ASICs, and allowing the implementation of
processor platform are resulting in powerful Configurablesystem
on chip(C-SoC)platforms. The Microchip’s PIC
microcontroller is very widely used microcontroller
architecture across various embedded systems. The
implementation of such core on FPGA is very much useful in
CSOC based embedded systems. This type of designs can be
widely used in those controlling fields demanding low power
consumption and high ratio of performance to price. In this
project a reduced instruction set computer (RISC) CPU IP
core whose instructions are compatible with the Microchip
PIC16C6Xseries of microcontrollers is implemented in VHDL.
The core is based on 8-bit RISC architecture and top-Down
design methodology is used in developing the core. The RISC
CPU core is based on Harvard architecture with 14-bit
instruction length and 8-bit data length and two-stage
instruction pipeline. The architecture will be designed aiming
at single cycle execution of the instructions, except those
related to program branches. Since this type of CPU based on
RISC architecture, there are only 35 reduced instructions in
its instruction set, which are easy to be learned and used. The
performance of the 8-bit RISC CPU is better than those of
CPUs which are based on CISC architecture. Modelsim Xilinx
Edition (MXE) will be used simulation and functional
verification. The Xilinx Spartan-3E FPGAs will be used
synthesis and timing analysis. The results will be verified on
chip with chipscope tool.
Workload Transformation and Innovations in POWER Architecture Ganesan Narayanasamy
IT Industry is going through two major transformations. One is adaption of AI and tight integration of the same in the commercial applications and enterprise workflow. Two the transformation in software architecture through the concepts like microservices and the cloud native architecture. These transformation alongside the aggressive adaption of IoT/mobile and 5G in all our day today activities is making the world operate in more real time manner which opens-up a new challenge to improve the hardware architecture to adapt to these requirements. These above two major transformation pushes the boundary of the entire systems stack making the designer rethink hardware. This talk presents you a picture of how the enterprise Industry leading POWER architecture is transforming to fulfill the performance demands of these newer generation workloads with primary focus on the AI acceleration on the chip.
14:00
12/11/2021
After the initial years of wireless IoT devices basing their networking on
proprietary protocols, home-grown by one vendor and in-compatibly to anything else, there is a shift to consolidate on IPv6.
In this talk, we will go briefly over 6lowpan as a technology that enabled a lot of these use-cases by providing compression techniques for low-power radio links with limited frame sizes. While its initial development was for IEEE 802.15.4 based networks it was quickly adopted for Bluetooth, NFC, PLC, and others.
This shift allowed the re-use of existing knowledge and concepts of TCP/IPv6 to be adopted into the IoT world, most notably the end-to-end concept, or rather the device-to-cloud concept for IoT. It also resulted in a reduced need for proxies translating between various proprietary networks and your home IP network.
In the future, this hopefully will result in a reduction of product-specific IoT
hubs in a network. An open source blueprint for such a gateway based on All Scenarios OS will be described, together with OpenThread and Matter (former CHIP) as example IPv6 based IoT turnkey solutions.
The portfolio of our Ethernet switch boards and devices has been designed for mission-critical applications in harsh and mobile environments. Being offered as CompactPCI or CompactPCI Serial board, as modular 19“ system or compact box switch – the scope of these components lies in the completion of our solution-oriented offering of rugged embedded computers for the rail and public transport, avionics, heavy vehicles, marine, medical, industrial automation, and power and energy markets.
5 Things to Know about Virtualization on Compact PCI SerialMEN Micro
The modular architecture of the well-known CompactPCI Serial industry platform (PICMG CPCI-S) is an ideal prerequisite for the configuration of flexible open standard virtualization solutions. One of the most powerful server hardware components for virtualization systems is the 3U CompactPCI Serial embedded single-board computer G25A, featuring the Intel XEON D-1500 family (Broadwell DE) with up to 16 processor cores.
OSN Bay Area Feb 2019 Meetup: Intel, Dynamic Device Personalization - Journey...Lumina Networks
Profiles for Intel® Ethernet 700 Series enables run-time updating and configuration of parse graph to expand or modify protocol support allowing early adoption of new technologies.
Cache Consistency – Requirements and its packet processing Performance implic...Michelle Holley
The audio starts at 9:00 due to a glitch while recording.
The topic can be as well stated as “All Processor Accesses are not created equally” – H/W and S/W Synergy – Methods and Mechanism:
- The developers in the audience, throughout the class, will wear different hats – first as a hard design engineer and look at platform design choices.
- Then they will wear the hat of driver developer and see the requirements and assumptions of driver on the hardware behavior.
- Then they will wear the hat of system architect and venture out to find out choices as how s/w and h/w can be in synergy and communicate – thereby potential optimum implementation can be made.
About the presenter: M Jay (Muthurajan Jayakumar) has worked with the DPDK team since 2009. He joined Intel in 1991 and has been in various roles and divisions: 64-bit CPU front side bus architect, 64 bit HAL developer, among others, before he joined the DPDK team. M Jay holds 21 US patents, both individually and jointly, all issued while working at Intel. M Jay was awarded the Intel Achievement Award in 2016, Intel's highest honor based on innovation and results.
A SURVEY OF NEURAL NETWORK HARDWARE ACCELERATORS IN MACHINE LEARNING mlaij
The use of Machine Learning in Artificial Intelligence is the inspiration that shaped technology as it is today. Machine Learning has the power to greatly simplify our lives. Improvement in speech recognition and language understanding help the community interact more naturally with technology. The popularity of machine learning opens up the opportunities for optimizing the design of computing platforms using welldefined hardware accelerators. In the upcoming few years, cameras will be utilised as sensors for several applications. For ease of use and privacy restrictions, the requested image processing should be limited to a local embedded computer platform and with a high accuracy. Furthermore, less energy should be consumed. Dedicated acceleration of Convolutional Neural Networks can achieve these targets with high flexibility to perform multiple vision tasks. However, due to the exponential growth in technology constraints (especially in terms of energy) which could lead to heterogeneous multicores, and increasing number of defects, the strategy of defect-tolerant accelerators for heterogeneous multi-cores may become a main micro-architecture research issue. The up to date accelerators used still face some performance issues such as memory limitations, bandwidth, speed etc. This literature summarizes (in terms of a survey) recent work of accelerators including their advantages and disadvantages to make it easier for developers with neural network interests to further improve what has already been established.
Workload Transformation and Innovations in POWER Architecture Ganesan Narayanasamy
IT Industry is going through two major transformations. One is adaption of AI and tight integration of the same in the commercial applications and enterprise workflow. Two the transformation in software architecture through the concepts like microservices and the cloud native architecture. These transformation alongside the aggressive adaption of IoT/mobile and 5G in all our day today activities is making the world operate in more real time manner which opens-up a new challenge to improve the hardware architecture to adapt to these requirements. These above two major transformation pushes the boundary of the entire systems stack making the designer rethink hardware. This talk presents you a picture of how the enterprise Industry leading POWER architecture is transforming to fulfill the performance demands of these newer generation workloads with primary focus on the AI acceleration on the chip.
14:00
12/11/2021
After the initial years of wireless IoT devices basing their networking on
proprietary protocols, home-grown by one vendor and in-compatibly to anything else, there is a shift to consolidate on IPv6.
In this talk, we will go briefly over 6lowpan as a technology that enabled a lot of these use-cases by providing compression techniques for low-power radio links with limited frame sizes. While its initial development was for IEEE 802.15.4 based networks it was quickly adopted for Bluetooth, NFC, PLC, and others.
This shift allowed the re-use of existing knowledge and concepts of TCP/IPv6 to be adopted into the IoT world, most notably the end-to-end concept, or rather the device-to-cloud concept for IoT. It also resulted in a reduced need for proxies translating between various proprietary networks and your home IP network.
In the future, this hopefully will result in a reduction of product-specific IoT
hubs in a network. An open source blueprint for such a gateway based on All Scenarios OS will be described, together with OpenThread and Matter (former CHIP) as example IPv6 based IoT turnkey solutions.
The portfolio of our Ethernet switch boards and devices has been designed for mission-critical applications in harsh and mobile environments. Being offered as CompactPCI or CompactPCI Serial board, as modular 19“ system or compact box switch – the scope of these components lies in the completion of our solution-oriented offering of rugged embedded computers for the rail and public transport, avionics, heavy vehicles, marine, medical, industrial automation, and power and energy markets.
5 Things to Know about Virtualization on Compact PCI SerialMEN Micro
The modular architecture of the well-known CompactPCI Serial industry platform (PICMG CPCI-S) is an ideal prerequisite for the configuration of flexible open standard virtualization solutions. One of the most powerful server hardware components for virtualization systems is the 3U CompactPCI Serial embedded single-board computer G25A, featuring the Intel XEON D-1500 family (Broadwell DE) with up to 16 processor cores.
OSN Bay Area Feb 2019 Meetup: Intel, Dynamic Device Personalization - Journey...Lumina Networks
Profiles for Intel® Ethernet 700 Series enables run-time updating and configuration of parse graph to expand or modify protocol support allowing early adoption of new technologies.
Cache Consistency – Requirements and its packet processing Performance implic...Michelle Holley
The audio starts at 9:00 due to a glitch while recording.
The topic can be as well stated as “All Processor Accesses are not created equally” – H/W and S/W Synergy – Methods and Mechanism:
- The developers in the audience, throughout the class, will wear different hats – first as a hard design engineer and look at platform design choices.
- Then they will wear the hat of driver developer and see the requirements and assumptions of driver on the hardware behavior.
- Then they will wear the hat of system architect and venture out to find out choices as how s/w and h/w can be in synergy and communicate – thereby potential optimum implementation can be made.
About the presenter: M Jay (Muthurajan Jayakumar) has worked with the DPDK team since 2009. He joined Intel in 1991 and has been in various roles and divisions: 64-bit CPU front side bus architect, 64 bit HAL developer, among others, before he joined the DPDK team. M Jay holds 21 US patents, both individually and jointly, all issued while working at Intel. M Jay was awarded the Intel Achievement Award in 2016, Intel's highest honor based on innovation and results.
A SURVEY OF NEURAL NETWORK HARDWARE ACCELERATORS IN MACHINE LEARNING mlaij
The use of Machine Learning in Artificial Intelligence is the inspiration that shaped technology as it is today. Machine Learning has the power to greatly simplify our lives. Improvement in speech recognition and language understanding help the community interact more naturally with technology. The popularity of machine learning opens up the opportunities for optimizing the design of computing platforms using welldefined hardware accelerators. In the upcoming few years, cameras will be utilised as sensors for several applications. For ease of use and privacy restrictions, the requested image processing should be limited to a local embedded computer platform and with a high accuracy. Furthermore, less energy should be consumed. Dedicated acceleration of Convolutional Neural Networks can achieve these targets with high flexibility to perform multiple vision tasks. However, due to the exponential growth in technology constraints (especially in terms of energy) which could lead to heterogeneous multicores, and increasing number of defects, the strategy of defect-tolerant accelerators for heterogeneous multi-cores may become a main micro-architecture research issue. The up to date accelerators used still face some performance issues such as memory limitations, bandwidth, speed etc. This literature summarizes (in terms of a survey) recent work of accelerators including their advantages and disadvantages to make it easier for developers with neural network interests to further improve what has already been established.
Moving Beyond Mobile: Delivering a Seamless Digital Experience from Online to...Mozu
Learn how to deliver a seamless digital experience with this presentation from Jason Wallis, CTO of Mozu, featuring Adam Silverman, Principal Analyst at Forrester Research.
Watch the webinar replay here: http://info.mozu.com/ecommerce-responsive-design-considerations-webinar.html
United PAC would to implore all Saint Lucians to read carefully this piece of legislation as it may have adverse effects on our lives as a free nation. This may prove very dangerous and an attack on our freedom as a democratic nation.
Like a Server Operating System (SOS) and a Cloud Operating System (COS) are responsible for computing resources. In a server the OS is responsible for managing the various hardware resources inside a server’s frame. A Web Operating System serves the same purpose like traditional server does. Instead of managing a single machine’s resources, a cloud Operating System is responsible for managing the cloud infrastructure. But unlike a traditional Operating System, a Web Operating System has to do everything at scale. In present paper we would discuss and study Web OS.
1. Software-Defined Networks (SDN) is a new paradigm in network ma.docxjackiewalcutt
1. Software-Defined Networks (SDN) is a new paradigm in network management that adds another layer (i.e., Network Operating System) to the architecture. Answer the following questions in the context of SDN with your reasoning.
(a) Is it scalable? Why?
(b) Is it less responsive? Why?
(c) Does it create a single point of failure? Why?
(d) Is it inherently less secure? Why?
(e) Is it incrementally deployable? Why?
2.RED randomly drops packets when it experience congestion. The probability of drop increases as the average queue size increases.
(a) Does it do a better job for uniform or bursty traffic? and why?
(b) Does it drop packets from the head of the queue or from the tail of the queue? and why?
(c) Does it make any difference; head/tail drop? and why?
3. Carefully read the short article OpenFlow: A Radical New Idea in Networking (http://queue.acm.org/detail.cfm?id=2305856), and answer the following questions.
The author argues that the deployment of SDN in general and OpenFlow in specific towards network democratization is a crazy idea. Do you agree? If yes, how come SDN has been supported and being deployed by many networking vendors. If not, give one scenario that SDN could cause disruptions.
NET WORKS
1
OpenFlow:
A Radical New Idea in Networking
An open standard that enables software-defined networking
Thomas A. Limoncelli
Computer networks have historically evolved box by box, with individual network elements
occupying specific ecological niches as routers, switches, load balancers, NATs (network address
translations), or firewalls. Software-defined networking proposes to overturn that ecology, turning
the network as a whole into a platform and the individual network elements into programmable
entities. The apps running on the network platform can optimize traffic flows to take the shortest
path, just as the current distributed protocols do, but they can also optimize the network to
maximize link utilization, create different reachability domains for different users, or make device
mobility seamless.
OpenFlow, an open standard that enables software-defined networking in IP networks, is a new
network technology that will enable many new applications and new ways of managing networks.
Here are three real, though somewhat fictionalized, applications:
EXAMPLE 1: BANDWIDTH MANAGEMENT. A typical wide area network has 30 percent utilization;
it must “reserve” bandwidth for “burst” times. Using OpenFlow, however, a system was developed
in which internal application systems (consumers) that need bulk data transfer could use the
spare bandwidth. Typical uses include daily replication of datasets, database backups, and the
bulk transmission of logs. Consumers register the source, destination, and quantity of data to
be transferred with a central service. The service does various calculations and sends the results
to the routers so they know how to forward this bulk data when links are otherwise unused.
Communication ...
In this research paper presents an design model for file sharing system for ubiquitos mobile
devices using both cloud and text computing. File sharing is one of the rationales for computer
networks with increasing demand for file sharing applications and technologies in small and
large enterprise networks and on the Internet. File transfer is an important process in any form
of computing as we need to really share the data across. The Wireless Network changed the way
we were sharing the files. Infra-Red and Bluetooth are the technology we use to share files in
mobile phones and Bluetooth is the successful one. In exisiting system there is no immediate
predecessor for the proposed system. Bluetooth file transfer is the already existing system.
Drawbacks of Existing System are Short Range , Slow transfer rate and Unsecure .But in our
research paper the idea is to use Both cloud and text computing network to transfer files.A
wireless network is created and the devices connected in this network can share files between
them. Benefits over the Existing System are more Secure , Range – upto 300 mts and Data rate
is 50-140 mbps. In future without internet connection we can transfer our information very
easily.Key words : cloud and text computing, Bluetooth, network, internet, system , file transfer.
THE IMPROVEMENT AND PERFORMANCE OF MOBILE ENVIRONMENT USING BOTH CLOUD AND TE...cscpconf
In this research paper presents an design model for file sharing system for ubiquitos mobile devices using both cloud and text computing. File sharing is one of the rationales for computer
networks with increasing demand for file sharing applications and technologies in small and large enterprise networks and on the Internet. File transfer is an important process in any form
of computing as we need to really share the data across. The Wireless Network changed the way we were sharing the files. Infra-Red and Bluetooth are the technology we use to share files in mobile phones and Bluetooth is the successful one. In exisiting system there is no immediate predecessor for the proposed system. Bluetooth file transfer is the already existing system.Drawbacks of Existing System are Short Range , Slow transfer rate and Unsecure .But in ourresearch paper the idea is to use Both cloud and text computing network to transfer files.A
wireless network is created and the devices connected in this network can share files betweenthem. Benefits over the Existing System are more Secure , Range – upto 300 mts and Data rate
is 50-140 mbps. In future without internet connection we can transfer our information veryeasily.Key words : cloud and text computing, Bluetooth, network, internet, system , file transfer.
Cloud traditionally depicts the internet, hence, it is also referred to as “the
cloud”. In simple terms, it means saving or accessing your data and programs
over the internet. Read to know more.
Ethnobotany and Ethnopharmacology:
Ethnobotany in herbal drug evaluation,
Impact of Ethnobotany in traditional medicine,
New development in herbals,
Bio-prospecting tools for drug discovery,
Role of Ethnopharmacology in drug evaluation,
Reverse Pharmacology.
The French Revolution, which began in 1789, was a period of radical social and political upheaval in France. It marked the decline of absolute monarchies, the rise of secular and democratic republics, and the eventual rise of Napoleon Bonaparte. This revolutionary period is crucial in understanding the transition from feudalism to modernity in Europe.
For more information, visit-www.vavaclasses.com
Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
The Roman Empire A Historical Colossus.pdfkaushalkr1407
The Roman Empire, a vast and enduring power, stands as one of history's most remarkable civilizations, leaving an indelible imprint on the world. It emerged from the Roman Republic, transitioning into an imperial powerhouse under the leadership of Augustus Caesar in 27 BCE. This transformation marked the beginning of an era defined by unprecedented territorial expansion, architectural marvels, and profound cultural influence.
The empire's roots lie in the city of Rome, founded, according to legend, by Romulus in 753 BCE. Over centuries, Rome evolved from a small settlement to a formidable republic, characterized by a complex political system with elected officials and checks on power. However, internal strife, class conflicts, and military ambitions paved the way for the end of the Republic. Julius Caesar’s dictatorship and subsequent assassination in 44 BCE created a power vacuum, leading to a civil war. Octavian, later Augustus, emerged victorious, heralding the Roman Empire’s birth.
Under Augustus, the empire experienced the Pax Romana, a 200-year period of relative peace and stability. Augustus reformed the military, established efficient administrative systems, and initiated grand construction projects. The empire's borders expanded, encompassing territories from Britain to Egypt and from Spain to the Euphrates. Roman legions, renowned for their discipline and engineering prowess, secured and maintained these vast territories, building roads, fortifications, and cities that facilitated control and integration.
The Roman Empire’s society was hierarchical, with a rigid class system. At the top were the patricians, wealthy elites who held significant political power. Below them were the plebeians, free citizens with limited political influence, and the vast numbers of slaves who formed the backbone of the economy. The family unit was central, governed by the paterfamilias, the male head who held absolute authority.
Culturally, the Romans were eclectic, absorbing and adapting elements from the civilizations they encountered, particularly the Greeks. Roman art, literature, and philosophy reflected this synthesis, creating a rich cultural tapestry. Latin, the Roman language, became the lingua franca of the Western world, influencing numerous modern languages.
Roman architecture and engineering achievements were monumental. They perfected the arch, vault, and dome, constructing enduring structures like the Colosseum, Pantheon, and aqueducts. These engineering marvels not only showcased Roman ingenuity but also served practical purposes, from public entertainment to water supply.
This is a presentation by Dada Robert in a Your Skill Boost masterclass organised by the Excellence Foundation for South Sudan (EFSS) on Saturday, the 25th and Sunday, the 26th of May 2024.
He discussed the concept of quality improvement, emphasizing its applicability to various aspects of life, including personal, project, and program improvements. He defined quality as doing the right thing at the right time in the right way to achieve the best possible results and discussed the concept of the "gap" between what we know and what we do, and how this gap represents the areas we need to improve. He explained the scientific approach to quality improvement, which involves systematic performance analysis, testing and learning, and implementing change ideas. He also highlighted the importance of client focus and a team approach to quality improvement.
How to Create Map Views in the Odoo 17 ERPCeline George
The map views are useful for providing a geographical representation of data. They allow users to visualize and analyze the data in a more intuitive manner.
Model Attribute Check Company Auto PropertyCeline George
In Odoo, the multi-company feature allows you to manage multiple companies within a single Odoo database instance. Each company can have its own configurations while still sharing common resources such as products, customers, and suppliers.
1. Embedded Server Based Remote Industrial Automation Control
Worked By: Bhushan, Amit, Manoj, Shrikishor & Payal
Abstract
"Science is the study of the world as it is.
Engineering is the creation of the world tomorrow".
Science is basically "passive" observation of the universe, as it exists to generate
knowledge. Engineering is making use of that knowledge to meet human needs by
creating machine, systems, process and technologies that have not previously existed.
Design and manufacturing are the synthetic part of engineering practice.
Manufacturer has received a lot of attention recently for very good economic reasons.
In today’s fast paced world, life has become so luxurious to the present man that
he has all the comfort right at his fingertips. Man wants to control everything while
being at any place. This has been made possible through Embedded Systems in
Communication.
Ethernet has traditionally been a quite complex interface. All Ethernet chips until
today had 100 pins or more, where difficult to find in small quantities and difficult to use
from a small micro controller with little memory. Microchip has changed the world with
their new Ethernet chip! A small chip with 28 pins only and has a SPI interface, which is
easy to use from any micro controller.
This opens a whole world of completely new applications. You can easily build
small devices, which can be spread all over the house and simply connected to Ethernet.
You don't need anymore a separate serial connection or other bus. Everything can be
easily connected via Ethernet. Distance is no longer a limiting factor.
Even WIFI connectivity is possible because you can connect the devices to a
wireless bridge.
2. Introduction
After the “everybody-in-the-Internet-wave” now obviously follows the
“everything-in-the- Internet-wave”. The most coffee, vending and washing machines are
still not available about the worldwide net. However the embedded Internet integration
for remote maintenance and diagnostic as well as the so-called M2M communication is
growing with a considerable speed rate.
Just the remote maintenance and diagnostic of components and systems by Web
browsers via the Internet, or a local Intranet has a very high weight for many
development projects. In numerous development departments people work on
completely Web based configurations and services for embedded systems. The
remaining days of the classic user interface made by a small LC-display with front panel
and a few function keys are over. Through future evolutions in the field of the mobile
Internet, Bluetooth-based PANs (Personal Area Network's) and the rapidly growing
M2M communication (M2M=Machine-to-Machine) a further innovating advance is to
be expected.
The central function unit to get access on an embedded system via Web browser
is the Web server. Such Web servers bring the desired HTML pages (HTML=Hyper
Text Markup Language) and pictures over the worldwide Internet or a local network to
the Web browser.
This happens HTTP-based (Hyper Text Transfer Protocol). A TCP/IP protocol
stack –that means it is based on sophisticated and established standards– manages the
entire communication. Web server (HTTP server) and browser (HTTP client) build
TCP/IP- applications. HTTP achieved a phenomenal distribution in the last years.
Meanwhile millions of user around the world surf HTTP-based in the World Wide Web.
Today almost every personal computer offers the necessary assistance for this protocol.
This status is valid more and more for embedded systems also. The HTTP spreads up
with a fast rate too.
4. Literature serve
An embedded HTTP server is a component of a software system that implements the
HTTP protocol. Examples of usage within an application might be:
• To provide a thin-client interface for a traditional application..
• To provide indexing, reporting, and debugging tools during the development
stage.
• To implement a protocol for the distribution and acquisition of information to be
displayed in the regular interface — possibly a web service, and possibly using
XML as the data format.
• To develop a web application
There are a few advantages to using HTTP to perform the above:
• HTTP is a well studied cross-platform protocol and there are mature
implementations freely available.
• HTTP is seldom blocked by firewalls and intranet routers.
• HTTP clients (e.g. web browsers) are readily available with all modern
computers.
• There is a growing tendency of using embedded HTTP servers in applications that
parallels the rising trends of home-networking and ubiquitous computing.
Typical requirements
Natural limitations of the platforms where an embedded HTTP server runs contribute to
the list of the functional requirements of the embedded, or more precise, embeddable
HTTP server. Some of these requirements in random order:
• "Small" RAM and ROM footprint. The exact size depends on the system, but in
many cases anything over several megabytes is not embeddable.
• Minimal CPU utilization.
• Cross compilation support for multiple CPU and operating system combinations.
• Easy integration with an existing application, including static linking with the
operating system and application.
• Serving pages from application memory if there is no file system.
• Modularity.
• Single thread and multi-thread support.
For every specific project requirements can vary significantly. For example, ROM and
RAM footprints can be very serious constraint and limit the choices of the system
designer. C++ or JVM availability for the system can be another constraint. Frequently
performance is an issue, because typical embedded systems run multiple simultaneous
5. tasks and an HTTP server is only one of them and may be configured as a low priority
task.
In the July 2010 survey we received responses from 205,714,253 sites.
This month's results show that three of the six major web servers have gained hostnames
in the last month, while the other three suffered losses.
The largest of these gains came from Apache, which saw an increase of over 1.1M
hostnames.
Google's share has continued to increase, albeit at a slower rate than last month with just
under 500k additional hostnames. This is due to increased activity on Blogger.
lighttpd suffered the largest overall loss this month, falling by 446k hostnames. This was
caused by the loss of 690k hostnames at Savvis in Australia. Microsoft also experienced a
loss this month, serving 648k fewer hostnames worldwide and also losing 265k active
sites. A big contributor to this was a loss of 388k hostnames due to lower activity on
Microsoft Live Spaces.
Total Sites Across All Domains
August 1995 - July 2010
Market Share for Top Servers Across All Domains
August 1995 - July 2010
6. Developer June 2010 Percent July 2010 Percent Change
Apache 111,792,321 54.02% 112,945,968 54.90% 0.89
Microsoft 53,865,345 26.03% 53,217,620 25.87% -0.16
Google 15,375,950 7.43% 15,849,853 7.70% 0.28
nginx 11,264,229 5.44% 11,474,696 5.58% 0.14
lighttpd 1,704,797 0.82% 1,258,800 0.61% -0.21
9. Working Of Circuit
It will let you house your own web site with possibly hundreds or even
thousands of pages, all in a little box connected to the internet via your modem/router.
You don't need a computer to operate and house a website - this little box does it for you
and it can be accessed from anywhere around the world, at any time, even from a mobile
phone which has a web browser. In fact, it is a complete web server - so we've called it
WEB SERVERS EVERYONE KNOWS THAT web servers normally involve
big, expensive, powerful computers with large memory, large hard disks and exotic
software, don't they? Well, that is the normal approach but now it doesn't have to
be. In fact, you don't even need a computer! WEB SERVERS can do it all. Even
better, it does not have a hard disk, uses practically no power and costs not much at
all. WEB SERVERS is just a small PC board (single- sided, no less) with a micro
controller, an SD/MMC card reader and not much else. In fact, it involves a total of
just three ICs and a 3-terminal regulator. Why have a memory card? This is the
"Eureka!" feature: SD/MMC cards are used in the majority of digital cam- eras and
they can pack a huge amount of memory for very little cash; we've an SD/MMC
memory card to store the data and website. And it just grew from there. Having thought
of the memory card as the bulk memory for the project and realising just how cheap it
was, the potential uses seemed to grow enormously. We are sure readers will come up
with a host of different uses Let's also be realistic. We need to describe how this WEB
SERVERS project works, how it connects to the intern et and all the necessary
know-how that this requires . There is a lot of jargon to be digested and understood but
when we have finished describing WEB SERVERS in considerable detail, we are
sure that you will see the potential. WEB SERVERS presents a great learning
opportunity for anyone interested in creating a personal website - it will be great for
schools, too. project it lacks some features like server side scripting and encryption, for
example, although for most applications, this won't be a problem. Its main advantage
is that it is considerably simpler, cheaper and easier to set-up than a more powerful
web server. In fact, if you have already gone through the set-up procedure for
connecting a broadband modem to your computer, this project should not be any
more challenging. Remote monitoring In most basic applications, control up to four
digital outputs, The FTP (file transfer protocol) server allows you to store and retrieve
files from a remote location and also allows you to manage your website remotely. In
addition, you can use it to back-up files off-site or transfer files (both text and images)
to a remote location The memory card can actually be an MMC, SD'or SDHC card (up
to 32GB). The website can include dynamic content that's constantly updated - you
will get emails from WEB SERVERS -Protocol) client within the WEB SERVERS .
In practice, the "Toggle" buttons Network time service if this address
changes. By using this service, you can log into the web server using a domain name
rather than its IP address (an IP address is numerical and all devices connected to
the internet, such as your modem, have an IP address}. This is necessary as the
public IP address can change if your modem is turned off for some time, so you might
not always know what it is. Earlier design and a PlC micro controller. It came as a pre-
built module and stored its web pages in an onboard EEPROM chip. Because the data
was stored in an EEPROM, the website was limited to 64 kilobytes. Even so, it
10. did allow remotely using dynamic web pages and had configurable I/O pins, )
output. By contrast, our new design can store much more complex web pages.
Another advantage of the new deign is that it implements simple file permissions
through HTTP (Hypertext Transfer Protocol) authentication. This means that you can
set a user name and password to access the whole website or just certain pages. You can
also retrict access to certain files, based on the file extensions. The earlier design
lacked a method of restricting access to its web pages and so its onboard website
was completely open to the public. Finally, the WEB SERVERS is highly
configurable and can be set up to work with almost any Ethernet network. connectors on
the back of your modem. Ethernet is a standard which is used .to transmit data
over a local network (eg, in an office) or to the internet via a modem. We will also be
providing the source "ode for a website so that you can easily modify the web server's
settings if necessary, to suit your requirements
Relay Driver Circuit
1B
1
2B
2
3B
3
4B
4
5B
5
6B
6
7B
7
8B
8
1C
18
2C
17
3C
16
4C
15
5C
14
6C
13
7C
12
8C
11
COM
10
U1
ULN2803
RL1
NTE-R46-24
RL2
NTE-R46-24
RL3
NTE-R46-24
RL4
NTE-R46-24
1
2
3
4
5
J1
CONN-SIL5
+12 V
From Dspic Port
+12V
+12 V
+12 V
+12 V
The ULN2803 consists of 8-bit TTL-input NPN darlington sink drivers. Each
darlington driver can handle a maximum of 500mA continuous (when using a single
channel only) and can withstand a maximum 50V in its off state. This makes the
ULN2803 well suited to provide an interface between the low logic level interfaces and
higher current/voltage devices such as relays, solenoids, motors and lamps.
11. Hardware Description
dsPIC33FJ64GP802
Features:-
Operating Range:
•Up to 40 MIPS operation (at 3.0-3.6V):
-Industrial temperature range (-40°C to +85°C)
-Extended temperature range (-40°C to +125°C
•Up to 20 MIPS operation (at 3.0-3.6V):
-High temperature range (-40°C to +140°C)
High-Performance DSC CPU:
•Modified Harvard architecture
•C compiler optimized instruction set
•16-bit wide data path
•24-bit wide instructions
•Linear program memory addressing up to 4M instruction words
•Linear data memory addressing up to 64 Kbytes
•83 base instructions: mostly 1 word/1 cycle
•Two 40-bit accumulators with rounding and saturation options
•Flexible and powerful addressing modes:
-Indirect
-Modulo
-Bit-Reversed
•Software stack
•16 x 16 fractional/integer multiply operations
•32/16 and 16/16 divide operations
•Single-cycle multiply and accumulate:
-Accumulator write back for DSP operations
-Dual data fetch
•Up to ±16-bit shifts for up to 40-bit data Direct Memory Access (DMA):
•8-channel hardware DMA
•Up to 2 Kbytes dual ported DMA buffer area (DM RAM) to store data
transferred via DMA:
- Allows data transfer between RAM and a peripheral while CPU is executing
code (no cycle stealing)
Timers/Capture/Compare/PWM:
•Timer/Counters, up to five 16-bit timers:
-Can pair up to make two 32-bit timers
-One timer runs as a Real-Time Clock with an
external 32.768 kHz oscillator
-Programmable prescaler
•Input Capture (up to four channels):
12. -Capture on up, down or both edges
-16-bit capture input functions
-4-deep FIFO on each capture
•Output Compare (up to four channels):
-Single or Dual 16-bit Compare mode
-16-bit Glitchless PWM mode
•Hardware Real-Time Clock/Calendar (RTCC):
-Provides clock, calendar and alarm functions
Interrupt Controller:
•5-cycle latency
•Up to 49 available interrupt sources
•Up to three external interrupts
•Seven programmable priority levels
•Five processor exceptions
Digital I/O:
•Peripheral pin Select functionality
•Up to 35 programmable digital I/O pins
•Wake-up/Interrupt-on-Change for up to 31 pins
•Output pins can drive from 3.0V to 3.6V
•Up to 5V output with open drain configuration
•All digital input pins are 5V tolerant
•4 mA sink on all I/O pins
On-Chip Flash and SRAM:
•Flash program memory (up to 128 Kbytes)
•Data SRAM (up to 16 Kbytes)
•Boot, Secure and General Security for program
Flash
System Management:
•Flexible clock options:
-External, crystal, resonator, internal RC
-Fully integrated Phase-Locked Loop (PLL)
-Extremely low jitter PLL
•Power-up Timer
•Oscillator Start-up Timer/Stabilizer
•Watchdog Timer with its own RC oscillator
•Fail-Safe Clock Monitor
•Reset by multiple sourcesPower Management:
•On-chip 2.5V voltage regulator
•Switch between clock sources in real time
•Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
•10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
-Two and four simultaneous samples (10-bit ADC)
-Up to 13 input channels with auto-scanning
-Conversion start can be manual or
13. synchronized with one of four trigger sources
-Conversion possible in Sleep mode
-±2 LSb max integral nonlinearity
-±1 LSb max differential nonlinearity
Audio Digital-to-Analog Converter (DAC):
•16-bit Dual Channel DAC module
•100 ksps maximum sampling rate
•Second-Order Digital Delta-Sigma Modulator Data Converter Interface (DCI)
module:
•Codec interface
•Supports I2S and AC’97 protocols
•Up to 16-bit data words, up to 16 words per frame
•4-word deep TX and RX buffers Comparator Module:
•Two analog comparators with programmable input/output configuration CMOS
Flash Technology:
•Low-power, high-speed Flash technology
•Fully static design
•3.3V (±10%) operating voltage
•Industrial and Extended temperature
•Low power consumption
Communication Modules:
•4-wire SPI (up to two modules):
-Framing supports I/O interface to simple codes
-Supports 8-bit and 16-bit data
-Supports all serial clock formats and sampling modes
•I2C™:
-Full Multi-Master Slave mode support
-7-bit and 10-bit addressing
-Bus collision detection and arbitration
-Integrated signal conditioning
-Slave address masking
•UART (up to two modules):
-Interrupt on address bit detect
-Interrupt on UART error
-Wake-up on Start bit from Sleep mode
-4-character TX and RX FIFO buffers
-LIN bus support
-IrDA® encoding and decoding in hardware
-High-Speed Baud mode
-Hardware Flow Control with CTS and RTS
•Enhanced CAN (ECAN™ module) 2.0B active:
-Up to eight transmit and up to 32 receive buffers
-16 receive filters and three masks
-Loopback, Listen Only and Listen All
14. -Messages modes for diagnostics and bus monitoring
-Wake-up on CAN message
-Automatic processing of Remote Transmission Requests
-FIFO mode using DMA
-DeviceNet™ addressing support
•Parallel Master Slave Port (PMP/EPSP):
-Supports 8-bit or 16-bit data
-Supports 16 address lines
•Programmable Cyclic Redundancy Check (CRC):
-Programmable bit length for the CRC generator polynomial (up to 16-bit length)
-8-deep, 16-bit or 16-deep, 8-bit FIFO for data input
17. Overview
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and
dsPIC33FJ128GPX02/X04 CPU module has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, including significant support for DSP. The
CPU has a 24-bit instruction word with a variable length opcode field. The Program
Counter (PC) is 23bits wide and addresses up to 4M x 24 bits of user program memory
space. The actual amount of program memory implemented varies by device. A single-
cycle instruction prefetch mechanism is used to help maintain throughput and provides
predictable execution. All instructions execute in a single cycle, with the exception of
instructions that change the program flow, the double-word move (MOV.D) instruction
and the table instructions. Overhead-free program loop constructs are supported using the
DO and REPEAT instructions, both of which are interruptible at any time. The
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04
devices have six- teen, 16-bit working registers in the programmer’s model. Each of the
working registers can serve as a data, address or address offset register. The 16th work-
ing register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.
There are two classes of instruction in the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices: MCU and DSP.
These two instruction classes are seamlessly integrated into a single CPU. The instruction
set includes many addressing modes and is designed for optimum C compiler efficiency.
For most instructions, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and
dsPIC33FJ128GPX02/X04 is capable of exe- cuting a data (or program data) memory
read, a work- ing register (data) read, a data memory write and a program (instruction)
memory read per instruction.
cycle. As a result, three parameter instructions can be supported, allowing A + B
= C operations to be executed in a single cycle. A block diagram of the CPU is shown in
Figure3-1, and the programmer’s model for the dsPIC33FJ32GP302/ 304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04
18. Data Addressing Overview
The data space can be addressed as 32K words or 64Kbytes and is split into two
blocks, referred to as X and Y data memory. Each memory block has its own independent
Address Generation Unit (AGU). The MCU class of instructions operates solely through
the X memory AGU, which accesses the entire memory map as one linear data space.
Certain DSP instructions operate through the X and Y AGUs to support dual operand
reads, which splits the data address space into two parts. The X and Y data space
boundary is device-specific. Overhead-free circular buffers (Modulo Addressing mode)
are supported in both X and Y address spaces. The Modulo Addressing removes the
software boundary checking overhead for DSP algorithms. Furthermore, the X AGU
circular addressing can be used with any of the MCU class of instructions. The X AGU
also supports Bit-Reversed Addressing to greatly simplify input or output data reordering
for radix-2 FFT algorithms. The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K program word boundary defined by
the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data-space
mapping feature lets any instruction access program space as if it were data space.
DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU,
two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. The
DSP instructions operate seamlessly with all other instructions and have been designed
for optimal real- time performance. The MAC instruction and otherassociated
instructions can concurrently fetch two data operands from memory while multiplying
two W registers and accumulating and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM data space be split for these
instructions and linear for all others. Data space partitioning is achieved in a transparent
and flexible manner through dedicating certain working registers to each address space.
Special MCU Features
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 features a 17-bit by 17-bit single-cycle multiplier that is
shared by both the MCU ALU and DSP engine. The multiplier can per- form signed,
unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by
16-bit multiplication not only allows you to perform mixed-sign multiplication, it also
achieves accurate results for
special operations, such as (-1.0) x (-1.0). The dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 supports 16/16 and 32/16
divide operations, both fractional and integer. All divide instructions are iterative
operations. They must be executed within a REPEAT loop, resulting in a total execution
time of 19 instruction cycles. The divideoperation can be interrupted during any of those
19. 19cycles without loss of data. A 40-bit barrel shifter is used to perform up to a 16-bit left
or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP
instructions.
PROGRAMMER’S MODEL:-
20. Arithmetic Logic Unit (ALU)
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and
dsPIC33FJ128GPX02/X04 ALU is 16 bits wide and is capable of addition, subtraction,
bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are
two’s complement in nature. Depending on the operation, the ALU can affect the values
of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits
in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits,
respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used. Data for the ALU operation can
come from the W register array or data memory, depending on the addressing mode of
the instruction. Likewise, output data from the ALU can be written to the W register
array or a data memory location. Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the SR bits affected by each
instruction. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and
dsPIC33FJ128GPX02/X04 CPU incorporates hardware support for both multiplication
and division. This includes a dedicated hardware multiplier and support hardware for 16-
bit-divisor division.
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU
supports unsigned, signed or mixed-sign operation in several MCU multiplication modes:
•16-bit x 16-bit signed
•16-bit x 16-bit unsigned
•16-bit signed x 5-bit (literal) unsigned
•16-bit unsigned x 16-bit unsigned
•16-bit unsigned x 5-bit (literal) unsigned
•16-bit unsigned x 16-bit signed
•8-bit unsigned x 8-bit unsigned
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned
integer divide operations with the following data sizes:
1.32-bit signed/16-bit signed divide
2.32-bit unsigned/16-bit unsigned divide
3.16-bit signed/16-bit signed divide
4.16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and the remainder in W1.
16-bit signed and unsigned DIV instructions can specify any W register for both the 16-
bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit
dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit
and 16-bit/16-bit instructions take the same number of cycles to execute.
21. DSP Engine
The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter
and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04
is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP
engine with MCU instruction flow is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumulator-to-accumulator
operations that require no additional data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits inthe CPU Core Control register
(CORCON), as listed
below:
•Fractional or integer DSP multiply (IF)
•Signed or unsigned DSP multiply (US)
•Conventional or convergent rounding (RND)
•Automatic saturation on/off for ACCA (SATA)
•Automatic saturation on/off for ACCB (SATB)
•Automatic saturation on/off for writes to data memory (SATDW)
•Accumulator Saturation mode selection (ACCSAT)
Data Space Write Saturation.
In addition to adder/subtracter saturation, writes to data space can also be
saturated, but without affecting the contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic
block as its input, together with overflow status from the original source (accumulator)
and the 16-bit round adder. These inputs are combined and used to select the appropriate
1.15 fractional value as output to write to data space memory. If the SATDW bit in the
CORCON register is set, data (after rounding or truncation) is tested for overflow and
adjusted accordingly:
•For input data greater than 0x007FFF, data written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
•For input data less than 0xFF8000, data written to memory is forced to the maximum
negative 1.15 value, 0x8000.
The Most Significant bit of the source (bit 39) is used to determine the sign of the
operand being tested. If the SATDW bit in the CORCON register is not set, the input data
is always passed through unmodified under all condition
22.
23. FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field (f) to directly address data
present in the first 8192 bytes of data memory (near data space). Most file register
instructions employ a working register, W0, which is denoted as WREG in these
instructions. The destination is typically either the same file register or WREG (with the
exception of the MUL instruction), which writes the result to a register or register pair.
The MOV instruction allows additional flexibility and can access the entire data space.
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form: Operand 3 = Operand 1
<function> Operand 2 where Operand 1 is always a working register (that is, the
addressing mode can only be register direct), which is referred to as Wb. Operand 2 can
be a W register, fetched from data memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The following addressing modes are
supported by MCU instructions:
•Register Direct
•Register Indirect
•Register Indirect Post-Modified
•Register Indirect Pre-Modified
•5-bit or 10-bit Literal
24. MMC CARD
Block Diagram of SD Card:
Why only MMC Card/SD Card is used:
A MultiMedia Card (MMC) is an IC (Integrated Circuit) which is stored in a
compact and rouged plastic enclosure. MultiMedia Card (MMC) are designed to store
data and to enable the transfer of data between devices equipped with MultiMedia Card
Slot. MMC standard was introduced in November, 1997 by SanDisk and Siemens
AG/Infineon Technologies AG. Current MultiMedia Card capacities range upto 2GB
however here we are using only 128 MB MMC Card.
A MMC is about the size of Postage Stamp 32mm long, 24 mm wide, and 1.4 mm
thick. MMC can be used in SD (Secure Digital) Card reader and writers. The theoretical
25. transfer speed of a MMC is 2.5 MB/sec. MMC originally used a one bit Serial Interface,
but newer versions of the specification allow transfer of 4 or sometimes even 8 bit at a
time. They have been more or less suppressed by Secure Digital (SD) Card, but still see
significant use because MMCs can be used in most devices which supports SD card.
What is SD Card?
A SD Card (Secure Digital Card) is an IC (Integrated Circuit) which is stored in a
compact and rugged plastic enclosure. SD Cards are designed to store data and to enable
the transfer of data between devices equipped with SD Card slots. Current SD Card
capacities range upto 4 GB, however here we are using only 128 MB Card. SD Card is 32
mm long, 24 mm wide and 2.1 mm thick. An even more compact format, the Mini SD
Card, is 20mm long, 21.5 mm wide and 1.4 mm thick. The theoretical transfer speed of
SD 1.0 Card is 12.5 MB/sec. SD 1.1 is expected to raise this to 50 MB/sec. The SD Card
Standard was introduced by Toshiba Matsushita Electric and SanDisk in 1999. Below
drawn Fig.3 show the Block Diagram of MMC/SD Card.
Fig. shows Internal Architecture of MMC/SD Card. It is a Flash Memory. Here
four Control signal is shown as CS, CMD/DI, DAT/DO and CLK/SCLK which used for
the read/write operations. Also four register sets are shown: OSR: Operational Card
Register, CID: Card Identification Register, CSD: Card Specific Data Register and RCA:
Relative Card Address Register. In the above Fig.3: All the units in the MultiMedia Card
are clocked by an internal clock generator. The interface driver unit synchronize the DAT
and CMD signals from external clock to the internal used clock signal the Card is
controlled by the three line MMC interface containing the signal CMD, CLK, DAT. For
the identification of the MMC in a stack of MMCs, a Card Identification Register (CID)
and a relative Card address register (RCA) is foreseen. An additional register contains
different types of operation parameters. This register is called Card Specific Data
Register (CSD). The communication using the MMC lines to access either the memory
field or the registers is defined by the MMC Standard. The Card has its own Power on the
detection unit. No additional Master reset signal is required to setup Card System is
powered up. No external programming voltage supply is required. The programming
voltage generated on Card. These MultiMedia Card supports a second interface mode the
SPI interface mode i.e. Serial Peripheral Interface Mode. The SPI mode is activated if CS
signal is assorted (negative) during the reception of the reset command (CMD0). These
MultiMedia Cards' Interface can operate in two different modes MultiMedia Card Mode
and SPI(Serial Peripheral Interface) Mode. Both modes are using the same pins. The
default mode the MMC Mode. The SPI Mode is selected by activating (=0) the CS signal
(Pin 1) and sending the CMD0.
LM35
In our project we are using LM 35A IC for temperature measurement.
LM 35A is precision type IC temperature sensor whose output voltage is
linearly proportional to the Celsius temperature. The LM 35A thus has an advantage over
linear temperature sensors calibrated in Kelvin as the user is not required to subtract large
constant voltage from its output to obtain convenient centigrade scaling. The LM35A
does not require any external calibration to provide typical accuracy as 1/4 degree Celsius
26. at room temperature & 3/4 degree Celsius over a full -55 to +150degree Celsius
temperature range. The LM35A has low output impedance, linear o/p & precise inherent
calibration make interfacing to read out or control circuitry in especially easy.
It can be used with single power supply or with +& - supplies. As it draws 60 ampere
from its supply, it has a very low self heating less than 0.1 degree Celsius in still air.
Features:
• CALIBRATED DIRECTLY IN CELSIUS
• Linear +10.0mV/c scale factor.
• 0.5Cel accuracy guarantee able (at +25 c).
• Suitable for remote application.
• Low cost due to water level trimming.
• Operated from 4 to 30 volt.
• Less then 60 micro A current drain.
TEMPERATURE MEASUREMENT BY USING LM 35A SENSOR
27. Graph of voltage vs. temperature of LM35
Ethernet Controller Chip ENC28j60
Features
• IEEE 802.3 compatible Ethernet controller
28. • Integrated MAC and 10BASE-T PHY
• Receiver and collision squelch circuit
• Supports one 10BASE-T port with automatic polarity detection and correction
• Supports Full and Half-Duplex modes
• Programmable automatic retransmit on collision
• Programmable padding and CRC generation
• Programmable automatic rejection of erroneous packets
• SPI™ Interface with speeds up to 10 Mb/s
Buffer
• 8-Kbyte transmit/receive packet dual port SRAM
• Configurable transmit/receive buffer size
• Hardware-managed circular receive FIFO
• Byte-wide random and sequential access with auto-increment
• Internal DMA for fast data movement
• Hardware assisted IP checksum calculation
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast packets
• Programmable receive packet filtering and wake-up host on logical AND or OR of the following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by 64-bit hash table
- Programmable pattern matching of up to 64 bytes at user-defined offset
• Loopback mode
Physical Layer (PHY) Features
• Wave shaping output filter
• Loopback mode
Operational
• Two programmable LED outputs for LINK, TX,RX, collision and full/half-duplex status
• Seven interrupt sources with two interrupt pins
• 25MHz clock
• Clock out pin with programmable prescaler
• Operating voltage range of 3.14V to 3.45V
• TTL level inputs
• Temperature range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• 28-pin SPDIP, SSOP, SOIC, QFN packages
29. MEMORY ORGANIZATION
All memory in the ENC28J60 is implemented as static RAM. There are three
types of memory in the ENC28J60: Control Registers Ethernet Buffer PHY Registers The
Control registers memory contains the registers that are used for configuration, control
and status retrieval of the ENC28J60. The Control registers are directly read and written
to by the SPI interface. The Ethernet buffer contains transmit and receive memory used
by the Ethernet controller in a single memory space. The sizes of the memory areas are
programmable by the host controller using the SPI interface. The Ethernet buffer memory
can only be accessed via the read buffer memory and write buffer memory SPI
commands (see Section4.2.2 Read Buffer Memory Command and Section4.2.4 Write
Buffer Memory Command). The PHY registers are used for configuration, control and
status retrieval of the PHY module. The registers are not directly accessible through the
SPI interface; they can only be accessed through Media Independent Interface
Management (MIIM) implemented in the MAC.
30.
31. Magnetics, Termination and Other External Components
To complete the Ethernet interface, the ENC28J60 requires several standard components to be
installed externally. These components should be connected as shown in Figure. The internal analog
circuitry in the PHY module requires that an external 2.32 kΩ, 1% resistor be attached from RBIAS to
ground. The resistor influences the TPOUT+/- signal amplitude. The resistor should be placed as close as
possible to the chip with no immediately adjacent signal traces to prevent noise capacitively coupling into
the pin and affecting the transmit behavior. It is recommended that the resistor be a surface mount type.
Some of the deviceís digital logic operates at a nominal 2.5V. An on-chip voltage regulator is incorporated
to generate this voltage. The only external component required is an external filter capacitor, connected
from VCAP to ground. The capacitor must have low equiva- lent series resistance (ESR), with a typical
value of 10 μF, and a minimum value of 1 μF. The internal regulator is not designed to drive external loads.
On the TPIN+/TPIN- and TPOUT+/TPOUT- pins, 1:1center taped pulse transformers, rated for Ethernet
operations, are required. When the Ethernet module is enabled, current is continually sunk through both
TPOUT pins. When the PHY is actively transmitting, a differential voltage is created on the Ethernet cable
by varying the relative current sunk by TPOUT+ compared to TPOUT-. A common-mode choke on the
TPOUT interface, placed between the TPOUT pins and the Ethernet transformer (not shown), is not
recommended. If a common-mode choke is used to reduce EMI emissions, it should be placed between the
Ethernet transformer and pins 1 and 2 of the RJ-45 connector. Many Ethernet transformer modules include
common-mode chokes inside the same device package. The transformers should have at least the isolation
rating specified in Table16-5 to protect against static voltages and meet IEEE 802.3 isolation requirements
(see Section16.0 ìElectrical Characteristics for specific transformer requirements). Both transmit and
receive interfaces additionally require two resistors and a capacitor to properly terminate the transmission
line, minimizing signal reflections. All power supply pins must be externally connected to the same power
source. Similarly, all ground references must be externally connected to the same ground node. Each VDD
and VSS pin pair should have a 0.1 μF ceramic bypass capacitor (not shown in the schematic) placed as
close to the pins as possible. Since relatively high currents are necessary to operate the twisted-pair
interface, all wires should be kept as short as possible. Reasonable wire widths should be used on power
wires to reduce resistive loss. If the differential data lines cannot be kept short, they should be routed in
such a way as to have a 100Ω characteristic impedance.
32.
33. Relay Driver (ULN 2803D)
It is 18 pin relay driver 1C as shown in figure 3.3 (a). We can switch ON/OFF
eight relays with this 1C. Also more than one LEDs can be made ON/OFF with this
1C.The free-wheeling diode required for the relay operation is inbuilt. It generally
operates on -+ 5V.
Figure 3.4 (a) Pin structure of ULN 2803
The internal structure of the 1C is as shown in figure 3.3 (b). Darlington pair is
used for switching the relay or LED. In such way here 1C requires inbuilt 8 darlington
pairs. When +5V supply is given to transistor Tl it act as switch i.e.it get ON and the
output current of transistor Tl drives another transistor T2 from the darlington pair and
therefore relays get de-energized. The common free-wheeling diode is connected to pin
no 10 and the common ground is at pin no 9.
Fig 3.4 (b) Internal Structure of ULN2803D.
37. NEXT
IFItis
EPress
IFItis
FPress
IFItis
GPRESS
IF
HPRESS
NEXT
A
ONRelay3rd
OFFRelay3rd
ONRelay4th
OFFRelay4th
About Internet:-
The Internet is a global system of interconnected computer networks that use the
standardized Internet Protocol Suite (TCP/IP). It is a network of networks that consists of
millions of private and public, academic, business, and government networks of local to
global scope that are linked by copper wires, fiber-optic cables, wireless connections, and
other technologies.
The Internet carries a vast array of information resources and services, most
notably the inter-linked hypertext documents of the World Wide Web (WWW) and the
infrastructure to support electronic mail, in addition to popular services such as online
chat, file transfer and file sharing, online gaming, and Voice over Internet Protocol
(VoIP) person-to-person communication via voice and video.
The origins of the Internet reach back to the 1960s when the United States funded
research projects of its military agencies to build robust, fault-tolerant and distributed
computer networks. This research and a period of civilian funding of a new U.S.
backbone by the National Science Foundation spawned worldwide participation in the
development of new networking technologies and led to the commercialization of an
38. international network in the mid 1990s, and resulted in the following popularization of
countless applications in virtually every aspect of modern human life. By 2009, an
estimated quarter of Earth's population uses the services of the Internet.
ABOUT HTML :-
HTML, which stands for HyperText Markup Language, is the predominant markup
language for web pages. It provides a means to create structured documents by denoting
structural semantics for text such as headings, paragraphs, lists, links, quotes and other items. It
allows images and objects to be embedded and can be used to create interactive forms. It is
written in the form of HTML elements consisting of "tags" surrounded by angle brackets within
the web page content. It can embed scripts in languages such as JavaScript which affect the
behavior of HTML webpages. HTML can also be used to include Cascading Style Sheets (CSS)
to define the appearance and layout of text and other material. The W3C, maintainer of both
HTML and CSS standards, encourages the use of CSS over explicit presentational markup.[1]
TCP/IP-based HTTP as Communication Platform :-
HTTP [1] is a simple protocol that is based on a TCP/IP protocol stack (picture
1.A). HTTP uses TCP (Transmission Control Protocol). TCP is a relative complex and
high-quality protocol to transfer data by the subordinate IP protocol. TCP itself always
guarantees a safeguarded connection between two communication partners based on an
extensive three- way-handshake procedure. As a result the data transfer via HTTP is
always protected. Due to the extensive TCP protocol mechanisms HTTP offers only a
low-grade performance.
39. Picture 1: TCP/IP stack and HTTP programming model
HTTP is based on a simple client/server-concept. HTTP server and client communicate
via a TCP connection. As default TCP port value the port number 80 will be used. The
server works completely passive. He waits for a request (order) of a client. This request
normally refers to the transmition of specific HTML documents. This HTML documents
possibly have to be generated dynamically by CGI [2]. As result of the requests, the
server will answer with a response that usually contains the desired HTML documents
among others (picture 1.B).
GET /test.htm HTTP/1.1
Accept]: image/gif, image/jpeg, */*
User selling agent: Mozilla/4.0
Host: 192.168.0.1
Listing 1.A: HTTP GET-request
HTTP/1.1 200 OK
Date: Mon, 06 Dec 1999 20:55:12 GMT
Server: Apache/1.3.6 (Linux)
Content-length: 82
Content-type: text/html
40. <html>
<head>
<title>Test-Seite</title>
</head>
<body>
Test-Seite
</body>
</html>
Listing 1.B: HTTP response as result of the GET-request from listing 1.A
HTTP requests normally consist of several text lines, which are transmitted to the server
by TCP. The listing 1.A shows an example. The first line characterizes the request type
(GET), the requested object (/test1.htm) and the used HTTP version (HTTP/1.1). In the
second request line the client tells the server, which kind of files it is able to evaluate.
The third line includes information about the client-software. The fourth and last line of
the request from listing 1.A is used to inform the server about the IP address of the
client. In according to the type of request and the used client software there could follow
some further lines. As an end of the request a blank line is expected. The HTTP
responses as request answer mostly consist of two parts. At first there is a header of
individual lines of text. Then follows a content object (optional). This content object
maybe consists of some text lines –in case of a HTML file– or a binary file when a GIF
or JPEG image should be transferred. The first line of the header is especially important.
It works as status or error message. If an error occurs, only the header or a part of it will
be transmitted as answer
43. ADVANTAGES
1) By allowing the operation on home appliance from anywhere through Website.
2) The component used for the assembling of this circuit are very cheap and are
easily available in the market. Hence the initial cost of setting up the circuit is
minimal.
3) If fitted in a residence, it becomes a safer and secure place to live in, As stated in
it’s applications a mock switching ON and switching OFF of different appliances
at different parts of the house in once absence can make anyone feel that owner
and the members of the family are around. This helps in the reduction of the
thefts.
5) In our country Energy saving is great problem. So one can save tremendous
amount of energy by switching OFF the electrical application by this project.
44. References:-
1] Online electronics circuits experimental system with embedded server
Zheying Li Wenson Pan
Inf. Sch., Beijing Union Univ., China;
This paper appears in: Advanced Learning Technologies, 2005. ICALT 2005. Fifth
IEEE International Conference on
Publication Date: 5-8 July 2005
On page(s): 644- 646
ISBN: 0-7695-2338-2
INSPEC Accession Number: 8641996
Digital Object Identifier: 10.1109/ICALT.2005.214
Current Version Published: 2005-09-19
With the embedded instrument server (Elserver), an online electronic circuit experiment
system, ESNetlab, was designed in this paper. To meet the need of electronic engineering
education, the ESNetlab supplied an online experimental platform. The user can construct
circuit and do some instrument operation according to their requirement. An embedded
instrument server has been used in the ESNetlab.
2] http://www.nabble.com/Embedded-Server-*and*-client-td24435225.html
3] http://www.microsoft.com/windowsembedded/en-us/products/server/faq.mspx
4] http://sun.systemnews.com/articles/32/1/ja/2709
5] http://www.tuxgraphics.org/electronics/200606/article06061.shtml
Books:-
1] Design with PIC Micro controllers By Jonh b. Peatman
2] Micro-controller By ajay deshmukh
3] Easy Microcontrol'n A Beginner's Guide to Using the PIC Microcontroller, by
David Benson
4] Microcontrol'n Apps , PIC Microcontroller Applications Guide by David
Benson
5] Interested in moving up to the 18 Series PIC® Microcontroller? See our
latest book
Mov'n Up, Migrating from the PIC® Microcontroller
16 Series to the 18 Series , by David Benson,
45. Tools to be use :-
1) PIC Microchip Programmer (Burner) and Its software.
2) Personal Computer
3) Operating system [Windows98, 2000,2003,Xp, Vista]
4) PIC Micro controller Compiler
5) Schematic And Layout Design Software
6) Multi-Meter or volt-meter, Soldering Iron, 12V DC power
supply,
Applications: -
1] Industrial automation control through Internet where any remote place of the world.
2] Home appliances control
3] Embedded Web Server design
This is a proposed system which can be very useful for agriculture Applications such as
soil moisture sensor for measuring moisture in the soil, water level probes reading for
measuring tank level, temp sensor for reading the temp of soil, humidity sensor for
measuring environmental humidity, these types of sensors can be connected to the
hardware. On the other we can also use relays to control the operation of the devices.
46. The output of these sensors will be monitored and will be displayed via a web server,
and same can be controlled remotely through a web portal (Internet).
The data generated by these sensors will be logged by the Device and will be stored in
the Memory Chip on the device. This is a most important feature of this project.
Weather Prophet which can be analyzed to determine the normal, high and low
temperatures of any given duration can be displayed using this device.