This document discusses high efficiency power amplifier technologies. It describes: 1) The requirements for future power amplifiers including high linearity, output power, bandwidth, and reduced energy consumption. 2) How switch-mode power amplifier technology using pulse width modulation can achieve up to 90% efficiency but is limited to low frequencies. 3) Different classes of switch-mode power amplifier operation (Class D, E, and F) and how they work to achieve high efficiency by minimizing voltage-current overlap losses. 4) Performance comparisons of different technologies like GaN and LDMOS transistors, noting advantages like bandwidth and efficiency of GaN for radio applications.

1. High efficiency power amplifiers
Prof Abhishek Kadam
SIES GST, Nerul

2. Background
• Linear RF power amplifiers consume large amounts of
energy, dissipate heat, and take up space in base stations
• The main requirements for future power amplifier
technology are
– high linearity, to satisfy higher-order modulation schemes
– greater average output power levels
– broader operating bandwidths (more than twice today’s typical
20MHz);
– reduced OPEX by decreasing RBS (Radio Base Station) energy
consumption
– reduced environmental impact by decreasing radio network
energy consumption

3. • Switch-mode PA technology has been identified
as a way of achieving high PA efficiency.
• This technology is being used successfully with
pulse width modulation (PWM) for audio and
digital subscriber line (DSL) driver applications..
• In this role, switch-mode PAs are 80% to 90%
efficient but their application is limited to
operating frequencies of around a few
megahertz.

4. Switch-mode PA
technology
• The main idea behind switch-mode PA technology is
to operate the transistor Linear or cutoff region
• so that either voltage or current, depending on
amplifier class, is switched on and off.

5. • When the switch is open, only voltage is
present over the transistor.
• When closed, current flows through it.
• Since there is no overlap in time between
voltage and current, power is not dissipated in
device and one obtains 100% theoretical
efficiency.

6. • In reality, a transistor is not a perfect switch
and overlap does, in fact, limit efficiency

7. • In the switch-mode power
amplifier, an output
resonator helps shape the
waveform by blocking
harmonic components of the
voltage and current
• A flywheel effect is created
generating sinusoidal voltage
and current in the load.

8. • The two necessaryconditions for generating a
single tone with 100% efficiency in the load
are
1. zero overlap between voltage over the
transistor channel and current through the
channel
2. Blocking of harmonic currents to the load.

9. Efficiency of almost ideal Class-AB and
switch-mode Class-D amplifiers.

10. Efficiency of almost ideal Class-AB and
switch-mode Class-D amplifiers.

11. • In real amplifiers, switching and component losses can
significantly degrade efficiency
• Examples of losses are
– parasitic capacitors, such as Cds (drain to source
capacitance). Parasitic capacitors cause loss when voltage
is switched;
– R-ON (the drain-to-source resistance when the transistor is
conducting);
– non-zero transition time.
• The square waveform requires a fast transistor (high ft ). If the
switching frequency is close to ft then loss occurs due to overlap
between voltage and current in the transistor
– PA implementation losses, including driver power
consumption, output circulator, and filtering.

12. Switch-mode PA architectures
• The main differences between these classes
are topologies, waveform shaping, and
method of analysis
• common switch-mode classes of operation are
– Class D
– Class E
– Class F

13. Class-F
• Class-F power amplifiers use multiple
resonators to control the harmonic contents
of the drain voltage and current
• In an ideal Class-F power amplifier, the drain
voltage is square wave; current waveforms are
half-sinusoidal

14. Class-F operation

15. • The main obstacle to the Class-F design is the
realization of harmonic terminations at high
frequencies.
• Practical designs are typically limited to
terminating the third harmonic, which limits
the maximum theoretical efficiency to 75%
• For a 2.2GHz design, this means the
terminations must operate at 6.6GHz.

16. Class-D
• There are two main realizations of Class-D
power amplifiers:
1. voltage-mode Class-D with serial resonator
circuit
2. current-mode Class-D using a parallel resonator
circuit
• Each type has a topology with two transistors.

17. Voltage-mode Class-D
• In this voltage is switched and the
output resonator forces the
current to be sinusoidal
• Voltage-mode Class-D power
amplifiers and PWM Technology
make a highly efficient
combination for audio applications
• But because transistor output
capacitances quickly become a
dominant loss factor at higher
frequencies, it is difficult to
achieve the same good efficiency
in the gigahertz frequency range

18. Current-mode Class-D
• In this current is switched and The short-circuit
harmonic termination of the output resonator
forces the voltage to be sinusoidal
• The amplifier has an interesting balanced
topology
– both its transistors are grounded, and their
output capacitances can be used in the output
filter.
• The half-wave rectified sinusoidal waveform is
created by the flywheel effect of the output
network and the balanced configuration.
• This amplifier shows promise as a highly
efficient performer at high power in the
gigahertz range
• A main drawback is high peak voltage, which
calls for transistors with high breakdown
voltage

19. Class-E
• The Class-E power amplifier, which is an
interesting compromise between a linear
Class- AB power amplifier and a switched
power amplifier
• has zero overlap between voltage and current
over and through the transistor, giving 100%
theoretical efficiency and potentially robust
performance

20. • The output network of a Class-
E power amplifier starts with a
shunt capacitor. Current
passes through the capacitor
when the transistor channel is
closed
• The inductance and
capacitance (LC) resonator
ensures that only the
fundamental frequency
current can flow in the output
network to load, giving a
single tone in the load.
• The flywheel effect of the LC
network drives the current
through either the switch or
the capacitor.

21. • The waveforms of the Class-E power amplifiers
are analog in shape without the ideal pulse-
shaped form presented by other modes of
operation.
• The Class-E mode can thus be supported by a
transistor with slower switching characteristics
and is better suited to high frequency operation
• As with Class-D mode, high peak voltage is a
drawback.

22. Performance Comparison

23. Just for Info
Parameter GaN LDMOS
Full form Gallium Nitride Laterally Diffused MOSFET
Applications
• GaN on SiC (50V) provides
high efficiency, power density
and higher gain in smaller
package
• Used for broadband
applications due to higher
output impedance and lower
Cds capacitance
• Advantages: GaN transistors
have small parasitic capacitance
and hence they have easy
wideband matching compare to
LDMOS transistors of identical
power level.
• LDMOS is used for cellular
and broadcast narrowband
applications due to high
power and efficiency
• LDMOS(50V) is used for
<1.5 GHz applications while
LDMOS (28V) is used for
frequencies upto 4 GHz
• Disadvantages: LDMOS
transistor has large Cgs/Cds
capacitance due to large
peripheral in its design. This
will limit the bandwidth.
Fmax (GHz) 30 GHz for GaN (50V)
22 GHz for LDMOS (28V)
15 GHz for LDMOS (50V)
Power Density (W/mm) 5-10 for GaN (50V)
0.8 for LDMOS (28V)
2 for LDMOS (50V)
Efficiency at P1dB (%) 70 for GaN (50V)
60 for LDMOS (28V)
<55 for LDMOS (50V)
Bandwidth (MHz) 500-2500 for GaN (50V)
100-400 for LDMOS (28V)
100-500 for LDMOS (50V)
Cds (pF/ W)
output capacitance
1/4 smaller for GaN (50V)
0.23 for LDMOS (28V)
1/2 smaller for LDMOS
(50V)
Cgs (pF/ W)
input capacitance
1/2 smaller for GaN (50V)
0.94 for LDMOS (28V)
1/2 smaller for LDMOS
(50V)
GaN LDMOS
Processing Bespoke fab Standard CMOS
Wafer Diameter 3-6 Inches (SiC) 8 Inches (Si)
Max Frequency >12 GHz 3.8 GHz
Band gap 3.4 eV 1.1 eV
Max Temperature 250 °C 225 °C
Johnson FoM 324 1
Mask Count 13 22
Electron Velocity -
Saturated
1.5 x 105m/s 1 x 105m/s
Electron Velocity -
Peak
2.7 x 105m/s 1 x 105m/s
Breakdown Field 300 V/um 25 V/um
typ BVds 175 V 75 V
GaN vs LDMOS Comparison

25. Multi finger Transistor