H64CSA_1B_023799_Osama

The University of Nottingham,
Malaysia Campus
Department of Electrical and Electronic Engineering
H64CSA - Hardware Accelerated Computing
Coursework-1B Report
Title: CPU Design
Submitted by:
Name: Osama Azim
Student Id: 023799
Date: 22nd
April '16

Coursework 1B - CPU Design
Index | H64CSA - Hardware Accelerated Computing Osama Azim
Contents
Index Title Pg.
1. Introduction 1
2. ISA Design 1
3. Micro-architecture Design 2
4. Implementation Model 4
5. Assembly Programs and Test Results 8
6. Discussion and Conclusion 14
-- Appendix - VHDL codes 15
1. Test Bench 15
2. Top Level 19
3. Control Unit 22
4. Instruction Register 25
5. Program Counter 26
6. PC register 28
7. PC increment 29
8. Logic Unit 30
9. A register 33
10. DCR 34
11. INC 35
12. SHL 35
13. cNOT 36

1 | H64CSA - Hardware Accelerated Computing Osama Azim
1. Introduction
A Central Processing Unit (CPU) usually comprises of instruction register (IR) and decoder, program controller (PC)
and control unit (CU) for its functioning and an arithmetic logic unit (ALU) executes, as per the programmed
instructions, various logical and math functions on the input data, thus providing a processed output.
The CPU designed for the following coursework has fixed length instructions similar to those of the 8-bit
microprocessors and executes logical operations on 8-bit input data. It consists of a 16 x 8 bit program memory
that can be loaded externally. The CPU design is implemented using VHDL and can be tested on a FPGA for further
development.
The top-level input/output ports of the CPU are shown in block diagram below:
2. ISA Design
The designed CPU has 8 instructions in total, with 4 logical operations and 4 data movement, jump and control
functions. The instruction set is listed in following table:
Instruction Encoding Operation Description
IN A 0011 xxxx A <-- Input Input to A register
OUT A 0100 xxxx Output <-- A Output from A register
DEC 0101 xxxx A == A - 1 Decrement A register
INC 0110 xxxx A == A + 1 Increment A register
JNZ <addr> 0111 aaaa If (A != 0) then PC = aaaa Jump to address if A is not zero
SHL 1000 xxxx A == Left shifted A Shift Left A register
NOT 1001 xxxx A == not A Compliment A
HALT 1111 xxxx Halt Halt execution
Where:
A = Accumulator, PC = Program Counter, aaaa = memory address, xx = don't cares
Diagram 1: CPU input/output ports
Clock
Input <7..0>
Reset
Output <7..0>
Halt
ROMaddress <3..0>
ROMwea
ROMdata <7..0>

The 4 data movement and program control instructions were designed as per the CPU architecture design, and are
minimum requirement for loading input port data, giving an output from A register and program control such as
loop and end cycle. The 3 logic operation instructions - DEC, INC and SHL were coursework requirements which
include NOT (or compliment) as an extra function for its simplicity and similarity to other logic functions such as
AND, OR and XOR that could be easily expanded in further development.
With 8 total instructions, the instruction length is chosen to be of 8-bit width. The 4 MSBs are selected as opcode,
since it can accommodate 24
or 16 instructions (for easy modification of > 8 instructions) and remaining 4 LSBs are
operand or address bits.
Figure 1: Instruction Set partitioning
It can be also noted that the ISA is of fixed length instructions, because of its design simplicity.
3. Micro-architecture Design
After the design of the ISA, a basic architecture for the processor was designed. An overview plan of all the
elements through which data would flow, the data-path design is shown in following figure. The elements in the
designed CPU are listed below:
 Memory: 16 locations x 8 bits wide
 Registers:
o Instruction Register (IR): 8 Bit
o Program Count Register (PC): 4 Bit
o A Register (Accumulator): 8 Bit
o Output Register: 8 Bit
 Multiplexors:
o PC register source, JNZmux: 2 inputs
o A register source, INmux: 2 inputs
o Logic operation select, LUmux: 4 inputs
 Logic Operations: 4 operations, 8 bit each
 Data Width: 8 Bit

Figure 2: Datapath Design
The ROM is to be written by inputs ROMaddress, ROMdata and ROMwea (write enable), this is discussed in CPU
testing. Although not shown in datapath, the Input data flow along with Input mux (INmux), A register, Logic
operation blocks and output registers are collectively termed as Logic Unit (LU) block. Also, the LUmux selects no
operation when LUmux = "000", this allows for NULL operation.
Instruction Register:
The Instruction Register (IR) performs two operations:
1. Load the instruction from PC specified address location in the ROM
2. Separate the 4 bit opcode and 4 bit address contained in the MSB and LSB of instruction respectively
Control Unit:
The control unit (CU) is a critical component in a CPU; it selects the multiplexor inputs and decides which register
will be written every clock cycle, based on the operation being performed.
The CU provides its outputs as per following Control Output Table:

Control
Word
State,
Q3Q2Q1Q0
IRload PCload INmux Aload JNZmux Aread LUmux Halt
0 0000, Start 0 0 0 0 0 0 000 0
1 0001, Fetch 1 1 0 0 0 0 000 0
2 0010, Decode 0 0 0 0 0 0 000 0
3 0011, IN A 0 0 1 1 0 0 000 0
4 0100, OUT A 0 0 0 0 0 1 000 0
5 0101, DEC 0 0 0 1 0 0 001 0
6 0110, INC 0 0 0 1 0 0 010 0
7 0111, JNZ 0 0 0 0 If Aneq0=1 0 000 0
8 1000, SHL 0 0 0 1 0 0 011 0
9 1001, NOT 0 0 0 1 0 0 100 0
10 1111, HALT 0 0 0 0 0 0 000 1
The CU implements a state diagram which controls the CPU execution cycle. Each CU state has outputs as defined
in the control output table.
Start
0000
Fetch
0001
Decode
0010
Output
0100
DEC
0101 INC
0110
JNZ
0111
SHL
1000
NOT
1001
Input
0011
HALT
1111
IR = 0000 or 0001 or 0010
IR = 0011
IR = 0100
IR = 0101
IR = 0110 IR = 0111
IR = 1000
IR = 1001
IR = 1111
Diagram 2: CU State Diagram

With 4 bit state addressing, 24
or 16 states can be encoded. Hence, additional instruction states can be easily
expanded.
4. Implementation Model
The CPU design was implemented and tested using VHDL on Xilinx ISE. The implementation consisted of various
components as explained earlier, the Top Level code consists of all the component instantiation.
Figure 3: VHDL components
 ROM 16x8 Bit: The Program ROM was implemented using Xilinx ISE built in IP cores, a dual port memory
was selected with following specification:
Figure 4: 16 x 8 ROM

For simplicity in implementation, minimum possible memory control signals were selected. Program writing is
performed by ROMaddress, ROMwea and ROMdata - which are CPU input ports.
 Control Unit: The control unit implements the execution state diagram as described earlier. It also issues
register clear command based on reset signal. VHDL code for this component is straight forward
implementation of states and is included in the Appendix.
 Instruction Register: This 8-bit register separates the opcode (4-bit MSB of Instruction) and address (4-bit
LSB of Instruction) using slices of the 8-bit Instruction. Implemented in VHDL as follows:
process(Clock, Load, Clear)
begin
if rising_edge(Clock) then -- reset register
if Clear = '1' then
iIR <= (others => '0');
elsif Load = '1' then -- load Instruction
iIR <= Din;
iAddressOut <= iIR(3 downto 0); -- 4-Bit LSB
iInstructionOut <= iIR(7 downto 4); -- 4-Bit MSB
end if;
end if;
end process;
 Program Counter: The program counter combines the PC register and PC increment components. It also
implements the JNZ multiplexer using following concurrent code:
iAddressIn <= AddressIn when JNZmux = '1' else -- Address from IR
iPCincr; -- Address from 4-bit increment
The PC register has similar 4-bit implementation as the Instruction Register. The PC increment component
adds upon the current address using VHDL as follows:
Process (Clock)
begin
if rising_edge(Clock) then
if Clear = '1' then
PCincrOut <= (others => '0'); -- clear address
else
PCincrOut <= PCincrIn + '1'; -- increment address
end if;
end if;
end process;

 Logic Unit: The logic unit acts as top-level for the accumulator and various logical function blocks, it also
incorporates the INmux and LUmux multiplexors. The Aneq0 signal is provided by logical OR operation on
accumulator output bits. An output 8-bit buffer loads the accumulator output contents when OUT
instruction is executed. The 8-bit A register acts as an accumulator and is implemented in VHDL similar to
the instruction register code described earlier.
The various logical operations are performed in their respective blocks, and the output is selected
using the 4 to 1 LUmux multiplexor.
o DCR: Executes the decrement operation by subtraction of input bits. In VHDL:
Process (Clock)
begin
Dout <= Din - '1';
end if;
end process;
o INC: Executes the increment operation by addition of 1 at each clock cycle, VHDL code is similar to
DEC.
o SHL: Executes the binary shift left operation by logical manipulation, In VHDL:
process (Clock)
begin
iShiftReg <= Din; -- load input to shift register
iShiftReg(7 downto 1) <= iShiftReg(6 downto 0);
iShiftReg(0) <= '0'; -- '0' loaded at right of bit stream
end if;
end process;
o NOT: Provides a compliment output to A register bits, implemented using concurrent logical not
operations in VHDL:
begin
Dout(7) <= NOT Din(7);

5. Assembly Programs and Test Results
The VHDL implementation of CPU was tested using the Xilinx Test Bench. Appropriate programs were loaded into
the program ROM and test input was provided.
 A clock period of 20ns (50 MHz) was selected for testing. In VHDL:
constant period : time := 20ns;
-- Clock ------------------------------------
process
begin
tb_Clock <= '0';
wait for period/2;
tb_Clock <= '1';
wait for period/2;
end process;
 To write to the dual port ROM, following VHDL test bench was written:
-- control signals --------------------
process
begin
tb_Reset <= '1';
tb_ROMwea <= '1';
wait for 8*period;
tb_Reset <= '0'; -- CPU is reset until Program is loaded
tb_ROMwea <= '0';
wait;
end process;
-- Assembly program load --------------------
process
begin
-- Program for decrement
wait for period/2;
tb_ROMaddr <= "0000"; tb_ROMdata <= "00110000"; -- IN A
wait for period;
tb_ROMaddr <= "0001"; tb_ROMdata <= "01010000"; -- DEC
wait for period;
tb_ROMaddr <= "0010"; tb_ROMdata <= "01000000"; -- OUT
wait for period;
tb_ROMaddr <= "0011"; tb_ROMdata <= "01110001"; -- JNZ Addr (0001)
wait for period;
tb_ROMaddr <= "0100"; tb_ROMdata <= "00000000"; -- NULL
wait for period;
wait for period;

tb_ROMaddr <= "0110"; tb_ROMdata <= "11111111"; -- HALT
wait;
end process;
 Logic Input was provided using test bench as follows:
-- Logic Input --------------------
process
begin
wait for 4*period;
tb_Input <= "00000011";
wait;
end process;
The Program load onto ROM performed using test bench can be viewed in following screen shot:
Figure 5: ROM program load
The CPU execution states can be seen here:
Figure 6: CPU execution states

Program for Decrement from <Input> to 0:
In Assembly:
IN A -- input to A register
loop: DEC -- decrement from A register
OUT -- output A register content
JNZ loop -- return to loop if A register is not zero
NULL -- do nothing, delay
HALT -- Halt if A register is zero
In Binary:
0000: 00110000;
0001: 01010000;
0010: 01000000;
0011: 01110001;
0100: 00000000;
0101: 00000000;
0110: 11111111;
Program for Increment from <Input> to FF, then 0:
In Assembly:
loop: INC -- Increment from A register
JNZ loop -- return to loop if A register is not zero
In Binary:
0000: 00110000;
0001: 01100000;
0010: 01000000;
0011: 01110001;
0100: 00000000;
0101: 00000000;
0110: 11111111;
Program for Shift Left:
In Assembly:
SHL -- Shift left A register contents

In Binary:
0000: 00110000;
0001: 10000000;
0010: 01000000;
0100: 00000000;
0101: 00000000;
0110: 11111111;
Program for Logic Compliment:
In Assembly:
NOT -- Compliment A register
In Binary:
0000: 00110000;
0001: 10010000;
0010: 01000000;
0100: 00000000;
0101: 00000000;
0110: 11111111;
Simulation Results:
 Decrement from 3 to 0 (to view IR opcode at InstructionIn):
Figure 7: 8-bit decrement from 3 to 0

 Decrement from 7 to 0:
Figure 8: 8-bit decrement from 7 to 0
 8 bit Increment :
Figure 9: 8-bit Increment
Although not shown in test bench, the Increment operation can go until 0xFF and then stop at the
consecutive 0x00.
 Logical Shift Left :

Figure 10: 8-bit Shift Left
 Logical Compliment :
Figure 11: 8-bit Compliment

6. Discussion and Conclusion
An 8-bit CPU was designed and simulated using VHDL. Although limited number of instructions were implemented,
expanding on the instruction set would be relatively easier than designing a new CPU architecture. Various
limitations and further improvement scope of this CPU are:
 The instruction set is largely designed without operands, and only JNZ instruction utilizes the 4-bit LSB of
instruction. Encoding operands and other functions into the instruction would require a more elaborate
instruction decoder and complex control unit.
 The execution cycle of JNZ instruction could not be implemented perfectly, and hence at-least one NULL
operations is required after JNZ in program. This allows the consecutive address to be loaded correctly into
the Program Counter.
 Further implementation of shift and rotate operations would be similar in design as that of the SHL
instruction. The same applies for implementation of logical operations such as AND, XOR, which can be
implemented similar to the NOT operation.
 The VHDL code developed would require further effective design, especially concerning actions that are
clock edge triggered, for hardware implementation.

Appendix - VHDL codes
1. Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_TopLevel IS
END tb_TopLevel;
ARCHITECTURE behavior OF tb_TopLevel IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TopLevel
PORT(
Input : IN std_logic_vector(7 downto 0);
Clock : IN std_logic;
Reset : IN std_logic;
ROMaddr : IN std_logic_vector(3 downto 0);
ROMwea : IN std_logic;
ROMdata : IN std_logic_vector(7 downto 0);
Output : OUT std_logic_vector(7 downto 0);
Halt : OUT std_logic
);
END COMPONENT;
--Inputs
signal tb_Input : std_logic_vector(7 downto 0) := (others => '0');
signal tb_Clock : std_logic := '0';
signal tb_Reset : std_logic := '0';
signal tb_ROMaddr : std_logic_vector(3 downto 0) := (others => '0');
signal tb_ROMwea : std_logic := '0';
signal tb_ROMdata : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal tb_Output : std_logic_vector(7 downto 0);
signal tb_Halt : std_logic;
constant period : time := 20ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TopLevel PORT MAP (
Input => tb_Input,

Clock => tb_Clock,
Reset => tb_Reset,
ROMaddr => tb_ROMaddr,
ROMwea => tb_ROMwea,
ROMdata => tb_ROMdata,
Output => tb_Output,
Halt => tb_Halt
);
-- Clock ------------------------------------
process
begin
tb_Clock <= '0';
wait for period/2;
tb_Clock <= '1';
wait for period/2;
end process;
-- control signals --------------------
process
begin
tb_Reset <= '1';
tb_ROMwea <= '1';
wait for 8*period;
tb_Reset <= '0'; -- CPU is reset until Program is loaded
tb_ROMwea <= '0';
wait;
end process;
-- Assembly program load --------------------
process
begin
-- Program for decrement ------------------------
-- wait for period/2;
-- tb_ROMaddr <= "0000"; tb_ROMdata <= "00110000"; -- IN A
-- wait for period;
-- tb_ROMaddr <= "0001"; tb_ROMdata <= "01010000"; -- DEC
-- wait for period;
-- tb_ROMaddr <= "0010"; tb_ROMdata <= "01000000"; -- OUT
-- wait for period;

-- tb_ROMaddr <= "0011"; tb_ROMdata <= "01110001"; -- JNZ Addr (0001)
-- wait for period;
-- tb_ROMaddr <= "0100"; tb_ROMdata <= "00000000"; -- NULL
-- wait for period;
-- wait for period;
-- tb_ROMaddr <= "0110"; tb_ROMdata <= "11111111"; -- HALT
-- wait;
-- end process;
-- Program for Increment-------------------------
wait for period/2;
tb_ROMaddr <= "0000"; tb_ROMdata <= "00110000"; -- IN A
wait for period;
tb_ROMaddr <= "0001"; tb_ROMdata <= "01100000"; -- INC
wait for period;
tb_ROMaddr <= "0010"; tb_ROMdata <= "01000000"; -- OUT
wait for period;
tb_ROMaddr <= "0011"; tb_ROMdata <= "01110001"; -- JNZ Addr (0001)
wait for period;
wait for period;
wait for period;
tb_ROMaddr <= "0110"; tb_ROMdata <= "11111111"; -- HALT
wait;
end process;
-- Program for Shift Left------------------------------
-- wait for period;
-- tb_ROMaddr <= "0001"; tb_ROMdata <= "10000000"; -- SHL
-- wait for period;
-- wait for period;
-- wait for period;
-- wait for period;
-- wait;
-- end process;
-- Program for Logical Compliment--------------------------

-- wait for period;
-- tb_ROMaddr <= "0001"; tb_ROMdata <= "10010000"; -- NOT
-- wait for period;
-- wait for period;
-- wait for period;
-- wait for period;
-- wait;
-- end process;
-- Logic Input ----------------------------------
process
begin
-- for decrement from 7 to 0--------------------
-- wait for 4*period;
-- tb_Input <= "00000111";
-- wait;
-- end process;
-- for decrement from 3 to 0--------------------
-- wait for 4*period;
-- tb_Input <= "00000011";
-- wait;
-- end process;
-- for Incremet from 0 to FF--------------------
wait for 4*period;
tb_Input <= "00000000";
wait;
end process;
END;

2. Top Level:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TopLevel is
port (
Input: in std_logic_vector (7 downto 0);
Clock: in std_logic;
Reset: in std_logic;
ROMaddr: in std_logic_vector (3 downto 0);
ROMwea: in std_logic;
ROMdata: in std_logic_vector (7 downto 0);
Output: out std_logic_vector (7 downto 0);
Halt: out std_logic
);
end TopLevel;
architecture Behavioral of TopLevel is
component ControlUnit
port(
Clock : in STD_LOGIC;
GReset : in STD_LOGIC;
Aneq0 : in STD_LOGIC;
InstructionIn : in STD_LOGIC_VECTOR (3 downto 0);
Reset : out STD_LOGIC;
Halt : out STD_LOGIC;
IRload : out STD_LOGIC;
JNZmux : out STD_LOGIC;
PCload : out STD_LOGIC;
INmux : out STD_LOGIC;
Aload : out STD_LOGIC;
Aread : out STD_LOGIC;
LUmux : out STD_LOGIC_VECTOR (2 downto 0)
);
end component;
component InstructionRegister
port(
Load : in STD_LOGIC;
Clear : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (7 downto 0);

InstructionOut : out STD_LOGIC_VECTOR (3 downto 0);
AddressOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component ProgramCounter
port(
JNZmux : in STD_LOGIC;
AddressIn : in STD_LOGIC_VECTOR (3 downto 0);
PCaddress : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component LogicUnit
port(
ARead : in STD_LOGIC;
INmux : in STD_LOGIC;
LUmux : in STD_LOGIC_VECTOR (2 downto 0);
Input : in STD_LOGIC_VECTOR (7 downto 0);
Aneq0 : out STD_LOGIC;
Output : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component ROM_16x8
port (
addra: IN std_logic_VECTOR(3 downto 0);
addrb: IN std_logic_VECTOR(3 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0);
wea: IN std_logic);
end component;
signal iAneq0, iIRload, iPCload, iINmux, iJNZmux, iAload, iAread, iReset: std_logic := '0';
signal iInstruction: std_logic_VECTOR(3 downto 0) := (others=>'0');
signal iAddress: std_logic_VECTOR(3 downto 0) := (others=>'0');
signal iPCaddress: std_logic_VECTOR(3 downto 0) := (others=>'0');
signal iLUmux: std_logic_VECTOR(2 downto 0) := (others=>'0');
signal iData: std_logic_VECTOR(7 downto 0) := (others=>'0');
begin
U1: ControlUnit

port map(
Clock => Clock,
GReset => Reset,
Aneq0 => iAneq0,
InstructionIn => iInstruction,
Reset => iReset,
Halt => Halt,
IRload => iIRload,
JNZmux => iJNZmux,
PCload => iPCload,
INmux => iINmux,
Aload => iAload,
Aread => iAread,
LUmux => iLUmux
);
U2: InstructionRegister
port map(
Clock => Clock,
Load => iIRload,
Clear => iReset,
Din => iData,
InstructionOut => iInstruction,
AddressOut => iAddress
);
U3: ProgramCounter
port map(
Clock => Clock,
Load => iPCload,
Clear => iReset,
JNZmux => iJNZmux,
AddressIn => iAddress,
PCaddress => iPCaddress
);
U4: LogicUnit
port map(
Clock => Clock,
Load => iAload,
ARead => iAread,
Clear => iReset,
INmux => iINmux,
LUmux => iLUmux,
Input => Input,
Aneq0 => iAneq0,
Output => Output
);
U5: ROM_16x8
port map (

addra => ROMaddr,
addrb => iPCaddress,
clka => clock,
clkb => clock,
dina => ROMdata,
doutb => iData,
wea => ROMwea
);
end Behavioral;
3. Control Unit:
library IEEE;
--library UNISIM;
entity ControlUnit is
port(
GReset : in STD_LOGIC;
Aneq0 : in STD_LOGIC;
InstructionIn : in STD_LOGIC_VECTOR (3 downto 0);
Reset : out STD_LOGIC;
Halt : out STD_LOGIC;
IRload : out STD_LOGIC;
JNZmux : out STD_LOGIC;
PCload : out STD_LOGIC;
INmux : out STD_LOGIC;
Aload : out STD_LOGIC;
Aread : out STD_LOGIC;
LUmux : out STD_LOGIC_VECTOR (2 downto 0)
);
end ControlUnit;
architecture Behavioral of ControlUnit is
type state_type is ( s_start, s_fetch, s_decode,
s_input, s_output, s_dec, s_inc, s_jnz, s_shl,
s_not,
s_halt
);
signal pres_state, next_state: state_type;
signal iReset, iIRload, iJNZmux, iPCload, iINmux, iAload, iAread, iHalt : std_logic :='0';
signal iLUmux: std_logic_vector (2 downto 0) := (others => '0');
begin
process (Clock, GReset) -- state machine increment and reset process

begin
iReset <= GReset;
if iReset = '1' then -- global reset
-- clear all registers
pres_state <= s_start; -- start of state machine
elsif iReset = '0' then
pres_state <= next_state; -- state change
end if;
end if;
end process;
process (pres_state, Clock)
begin
case pres_state is
when s_start =>
if iReset = '1' then
iIRload <= '0'; iJNZmux <= '0'; iPCload <= '0'; -- reset all control outputs
iINmux <= '0'; iAload <= '0'; iAread <= '0'; iLUmux <= (others => '0');
next_state <= s_start;
else
iIRload <= '0'; iPCload <= '0'; -- reset all control outputs
-- iJNZmux <= '0';
next_state <= s_fetch;
end if;
when s_fetch =>
iIRload <= '1'; iPCload <= '1';
-- iJNZmux <= '0';
next_state <= s_decode;
when s_decode =>
if InstructionIn = "0000" then -- return to s_start
elsif InstructionIn = "0001" then
next_state <= s_input;

next_state <= s_output;
next_state <= s_dec;
next_state <= s_inc;
next_state <= s_jnz;
next_state <= s_shl;
next_state <= s_not;
next_state <= s_halt;
end if;
iIRload <= '0'; iJNZmux <= '0'; iPCload <= '0'; -- reset all control outputs
when s_input =>
iINmux <= '1'; -- as per control output table
iAload <= '1';
next_state <= s_start; -- return to start state
when s_output =>
iAread <= '1'; -- as per control output table
when s_dec =>
iAload <= '1'; -- as per control output table
iLUmux <= "001";
when s_inc =>
iLUmux <= "010";
when s_jnz =>
if Aneq0 = '1' then
iJNZmux <= '1'; -- as per control output table
else
iJNZmux <= '0';
end if;
when s_shl =>
iLUmux <= "011";

when s_not =>
iLUmux <= "100";
when s_halt =>
iHalt <= '1'; -- as per control output table
end case;
end process;
Reset <= iReset;
Halt <= iHalt;
IRload <= iIRload;
JNZmux <= iJNZmux;
PCload <= iPCload;
INmux <= iINmux;
Aload <= iAload;
Aread <= iAread;
LUmux <= iLUmux;
end Behavioral;
4. Instruction Register:
library IEEE;
--library UNISIM;
entity InstructionRegister is
port(
InstructionOut : out STD_LOGIC_VECTOR (3 downto 0);
AddressOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end InstructionRegister;
architecture Behavioral of InstructionRegister is

signal iInstructionOut, iAddressOut: STD_LOGIC_VECTOR (3 downto 0) := (others =>
'0');
signal iIR: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
begin
if Clear = '1' then -- reset register
iIR <= (others => '0');
elsif Load = '1' then -- load Instruction
iIR <= Din;
iAddressOut <= iIR(3 downto 0); -- 4-Bit LSB
iInstructionOut <= iIR(7 downto 4); -- 4-Bit MSB
end if;
end if;
end process;
AddressOut <= iAddressOut;
InstructionOut <= iInstructionOut;
end Behavioral;
5. Program Counter:
library IEEE;
--library UNISIM;
entity ProgramCounter is
port(
JNZmux : in STD_LOGIC;
AddressIn : in STD_LOGIC_VECTOR (3 downto 0);
PCaddress : out STD_LOGIC_VECTOR (3 downto 0)
);

end ProgramCounter;
architecture Behavioral of ProgramCounter is
component PCregister
port(
PCregIn : in STD_LOGIC_VECTOR (3 downto 0);
PCregOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component PCincrement
port(
PCincrIn : in STD_LOGIC_VECTOR (3 downto 0);
PCincrOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal iAddressIn, iPCaddress, iPCincr: std_logic_vector(3 downto 0) := (others
=> '0');
begin
U1: PCregister
port map(
Clock => Clock,
Load => Load,
Clear => Clear,
PCregIn => iAddressIn,
PCregOut => iPCaddress
);
U2: PCincrement
port map(
Clock => Clock,
Clear => Clear,
PCincrIn => iPCaddress,
PCincrOut => iPCincr
);
PCaddress <= iPCaddress;
-- JNZ multiplexer ---------------
iAddressIn <= AddressIn when JNZmux = '1' else -- Address from IR

iPCincr; -- Address from 4-bit increment
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if JNZmux = '1' then
-- iAddressIn <= AddressIn;
-- else
-- iAddressIn <= iPCincr;
-- end if;
-- end if;
-- end process;
end Behavioral;
6. PCregister:
library IEEE;
--library UNISIM;
entity PCregister is
port(
PCregIn : in STD_LOGIC_VECTOR (3 downto 0);
PCregOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end PCregister;
architecture Behavioral of PCregister is
signal iPCregister: STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
begin
if Clear = '1' then

iPCregister <= (others => '0');
elsif Load = '1' then
iPCregister <= PCregIn;
end if;
end if;
end process;
PCregOut <= iPCregister;
end Behavioral;
7. PCincrement:
library IEEE;
--library UNISIM;
entity PCincrement is
port(
PCincrIn : in STD_LOGIC_VECTOR (3 downto 0);
PCincrOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end PCincrement;
architecture Behavioral of PCincrement is
begin
Process (Clock)
begin
if Clear = '1' then
PCincrOut <= (others => '0'); -- clear address
else
PCincrOut <= PCincrIn + '1'; -- increment address
end if;

end if;
end process;
end Behavioral;
8. LogicUnit:
library IEEE;
--library UNISIM;
entity LogicUnit is
port(
ARead : in STD_LOGIC;
INmux : in STD_LOGIC;
LUmux : in STD_LOGIC_VECTOR (2 downto 0);
Input : in STD_LOGIC_VECTOR (7 downto 0);
Aneq0 : out STD_LOGIC;
Output : out STD_LOGIC_VECTOR (7 downto 0)
);
end LogicUnit;
architecture Behavioral of LogicUnit is
component Aregister
port(
Aout : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component DCR
port(

Dout : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component INC
port(
);
end component;
component SHL
port(
);
end component;
component cNOT
port(
);
end component;
signal iData, iAreg, iDataMod, iDataDCR, iDataINC, iDataSHL, iDataNOT, iOutput:
std_logic_VECTOR(7 downto 0) := (others=>'0');
begin
U1: Aregister
port map(
Clock => Clock,
Clear => Clear,
Load => Load,
Din => iData,
Aout => iAreg
);
U2: DCR
port map(
Clock => Clock,
Din => iAreg,
Dout => iDataDCR

);
U3: INC
port map(
Clock => Clock,
Din => iAreg,
Dout => iDataINC
);
U4: SHL
port map(
Clock => Clock,
Din => iAreg,
Dout => iDataSHL
);
U5: cNOT
port map(
Clock => Clock,
Din => iAreg,
Dout => iDataNOT
);
-- INmux ---------------------
iData <= Input when INmux = '1' else
iDataMod;
-- LUmux ---------------------
iDataMod <= iDataDCR when LUmux = "001" else
iDataINC when LUmux = "010" else
iDataSHL when LUmux = "011" else
iDataNOT when LUmux = "100";
-- Aneq0 signal ---------------
Aneq0 <= iAreg(7) or iAreg(6) or iAreg(5) or iAreg(4) or iAreg(3) or
iAreg(2) or iAreg(1) or iAreg(0);
-- Aneq0 <= iData(7) or iData(6) or iData(5) or iData(4) or iData(3) or
iData(2) or iData(1) or iData(0);
-- Output register -----------
Process (clock)
begin
if rising_edge(clock) then
if Clear = '1' then

iOutput <= (others=>'0');
elsif ARead = '1' then
iOutput <= iAreg;
end if;
end if;
end process;
Output <= iOutput;
--------------------------------
end Behavioral;
9. Aregister:
library IEEE;
--library UNISIM;
entity Aregister is
port(
Aout : out STD_LOGIC_VECTOR (7 downto 0)
);
end Aregister;
architecture Behavioral of Aregister is
signal iAregister: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
begin
if Clear = '1' then
iAregister <= (others => '0');

elsif Load = '1' then
iAregister <= Din;
end if;
end if;
end process;
Aout <= iAregister;
end Behavioral;
10. DCR:
library IEEE;
--library UNISIM;
entity DCR is
port(
);
end DCR;
architecture Behavioral of DCR is
begin
Process (Clock)
begin
Dout <= Din - '1';
end if;
end process;
end Behavioral;

11. INC:
library IEEE;
--library UNISIM;
entity INC is
port(
);
end INC;
architecture Behavioral of INC is
begin
Process (Clock)
begin
Dout <= Din + '1';
end if;
end process;
end Behavioral;
12. SHL:
library IEEE;

--library UNISIM;
entity SHL is
port(
);
end SHL;
architecture Behavioral of SHL is
signal iShiftReg: std_logic_vector (7 downto 0) := (others => '0');
begin
process (Clock)
begin
iShiftReg <= Din;
iShiftReg(7 downto 1) <= iShiftReg(6 downto 0);
iShiftReg(0) <= '0';
end if;
end process;
Dout <= iShiftReg;
end Behavioral;
13. cNOT:
library IEEE;
--library UNISIM;
entity cNOT is
port(

);
end cNOT;
architecture Behavioral of cNOT is
begin
end Behavioral;

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