IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A review on reversible logic gates and their implementationDebraj Maji
The document provides an overview of reversible logic gates and their implementation. It discusses how reversible logic gates can reduce power dissipation compared to irreversible logic gates. Some key reversible logic gates are described, including NOT, CNOT, Feynman, Toffoli, and Fredkin gates. Their truth tables and quantum costs are given. The document serves to introduce researchers to reversible logic gates that can be used to design more complex computing circuits with potential applications in quantum computing and low-power electronics.
This document outlines the key topics covered in combinational circuits, including:
1) It introduces combinational circuits and their analysis and design procedures.
2) Some common combinational circuits that are used extensively in digital systems design are discussed, such as adders, subtractors, comparators, decoders, encoders, and multiplexers.
3) The analysis of a combinational circuit involves determining the Boolean functions or truth table that represent the circuit's functionality. The design of a combinational circuit starts with specifying the required inputs/outputs and deriving the truth table and Boolean functions that define the required logic.
The document discusses various aspects of VHDL including enumerated types, subtypes, constants, arrays, strings, and different architecture modeling styles like dataflow, behavioral, and structural. Enumerated types allow defining a set of named values for a type. Subtypes restrict a base type to a range of values. Constants contribute to readability and portability. Arrays define ordered sets of elements of the same type indexed by integers. Strings are arrays of characters. Architecture bodies specify the internal logic of an entity using components, concurrent signal assignments, sequential processes, or a combination.
Digital logic is based on the binary number system of 0s and 1s. This two-valued logic system allows statements to be either true or false. One reason for using binary is that electronic circuits can be designed to reliably represent and switch between two states. There are two classes of digital logic - combinational logic, where outputs depend only on current inputs, and sequential logic, where outputs also depend on prior states. Basic logic gates like AND, OR, and NOT are used to combine input signals in circuits. The Karnaugh map provides a visual method to simplify Boolean logic expressions by grouping adjacent ones to minimize variables.
A great power point presentation for DBMS Concepts from start to end and with best examples chapter by chapter. Please go though each chapters sequentially for your knowledge.
A very easy going study material for better understanding and concepts of Database Management System.
The document describes experiments conducted on digital logic circuits using VHDL. It includes summaries of experiments on multiplexers, logic gates, demultiplexers, half adders, full adders, half subtractors, full subtractors, SR latches, and SR clocked latches. Code snippets in VHDL are provided for each circuit along with truth tables and conclusions.
This document discusses digital system design and fault modeling, diagnosis, testing and fault tolerance of digital circuits. It provides definitions of different types of faults including permanent faults like stuck-at faults and temporary faults like transient and intermittent faults. Specific fault models are described, including stuck-at, bridging and delay faults. Methods of fault diagnosis for combinational circuits are discussed, including the path sensitization technique where a path is sensitized from the fault origin to the output to detect the fault.
Verilog is a hardware description language used to model electronic systems. Some key features include:
- It allows design at different levels of abstraction from logic gates to register transfer level.
- It supports both synthesis for implementation on FPGAs and ASICs as well as simulation to verify designs.
- It provides constructs like if/else statements, case statements, always blocks and for loops to describe hardware behavior.
- User-defined primitives and system tasks like $display and $monitor aid in debugging and testing designs.
A review on reversible logic gates and their implementationDebraj Maji
The document provides an overview of reversible logic gates and their implementation. It discusses how reversible logic gates can reduce power dissipation compared to irreversible logic gates. Some key reversible logic gates are described, including NOT, CNOT, Feynman, Toffoli, and Fredkin gates. Their truth tables and quantum costs are given. The document serves to introduce researchers to reversible logic gates that can be used to design more complex computing circuits with potential applications in quantum computing and low-power electronics.
This document outlines the key topics covered in combinational circuits, including:
1) It introduces combinational circuits and their analysis and design procedures.
2) Some common combinational circuits that are used extensively in digital systems design are discussed, such as adders, subtractors, comparators, decoders, encoders, and multiplexers.
3) The analysis of a combinational circuit involves determining the Boolean functions or truth table that represent the circuit's functionality. The design of a combinational circuit starts with specifying the required inputs/outputs and deriving the truth table and Boolean functions that define the required logic.
The document discusses various aspects of VHDL including enumerated types, subtypes, constants, arrays, strings, and different architecture modeling styles like dataflow, behavioral, and structural. Enumerated types allow defining a set of named values for a type. Subtypes restrict a base type to a range of values. Constants contribute to readability and portability. Arrays define ordered sets of elements of the same type indexed by integers. Strings are arrays of characters. Architecture bodies specify the internal logic of an entity using components, concurrent signal assignments, sequential processes, or a combination.
Digital logic is based on the binary number system of 0s and 1s. This two-valued logic system allows statements to be either true or false. One reason for using binary is that electronic circuits can be designed to reliably represent and switch between two states. There are two classes of digital logic - combinational logic, where outputs depend only on current inputs, and sequential logic, where outputs also depend on prior states. Basic logic gates like AND, OR, and NOT are used to combine input signals in circuits. The Karnaugh map provides a visual method to simplify Boolean logic expressions by grouping adjacent ones to minimize variables.
A great power point presentation for DBMS Concepts from start to end and with best examples chapter by chapter. Please go though each chapters sequentially for your knowledge.
A very easy going study material for better understanding and concepts of Database Management System.
The document describes experiments conducted on digital logic circuits using VHDL. It includes summaries of experiments on multiplexers, logic gates, demultiplexers, half adders, full adders, half subtractors, full subtractors, SR latches, and SR clocked latches. Code snippets in VHDL are provided for each circuit along with truth tables and conclusions.
This document discusses digital system design and fault modeling, diagnosis, testing and fault tolerance of digital circuits. It provides definitions of different types of faults including permanent faults like stuck-at faults and temporary faults like transient and intermittent faults. Specific fault models are described, including stuck-at, bridging and delay faults. Methods of fault diagnosis for combinational circuits are discussed, including the path sensitization technique where a path is sensitized from the fault origin to the output to detect the fault.
Verilog is a hardware description language used to model electronic systems. Some key features include:
- It allows design at different levels of abstraction from logic gates to register transfer level.
- It supports both synthesis for implementation on FPGAs and ASICs as well as simulation to verify designs.
- It provides constructs like if/else statements, case statements, always blocks and for loops to describe hardware behavior.
- User-defined primitives and system tasks like $display and $monitor aid in debugging and testing designs.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Dear students get fully solved assignments
Send your semester & Specialization name to our mail id :
“ help.mbaassignments@gmail.com ”
or
Call us at : 08263069601
(Prefer mailing. Call in emergency )
PPT ON VHDL subprogram,package,alias,use,generate and concurrent statments an...Khushboo Jain
this presentation includes information about - subprograms,packages,use clause, aliases,resolved signals,components,configuration,generate statements,concurrent statments and use of vhdl in simulation and synthesis.
1) The document presents designs for reversible logic gates and their applications in low power circuits. It proposes an improved design for a reversible programmable logic array (RPLA) using multiplexer and Feynman gates that is more efficient than existing designs.
2) It also proposes a method for structuring a reversible arithmetic logic unit (ALU) using reversible logic gates instead of traditional gates, achieving the same functionality with reduced information loss.
3) The RPLA design is demonstrated by implementing reversible 1-bit full adders and subtractors. Simulation results show the proposed design optimizes the number of reversible gates used.
A method to determine partial weight enumerator for linear block codesAlexander Decker
This document presents a method to determine partial weight enumerators (PWE) for linear block codes using the error impulse technique and Monte Carlo method. The PWE can be used to compute an upper bound on the error probability of the maximum likelihood decoder. As an application, the document provides PWEs and analytical performances of shortened BCH codes, including BCH(130,66), BCH(103,47), and BCH(111,55). The full weight distributions of these codes are unknown. The proposed method estimates the PWE by drawing random codewords and computing the recovery rate of known-weight codewords, obtaining the PWE within a confidence interval.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes an article from the International Journal of Engineering Research and Development that presents a design for a highly linear Operational Transconductance Amplifier (OTA). The OTA combines two linearization techniques: 1) adaptive biasing of the differential pairs using a circuit that biases the tail current based on the quadratic input voltage to cancel non-linearity, and 2) resistive source degeneration to account for mobility reduction in short channel devices. Simulation results using a 0.18um CMOS technology show that the third order harmonic distortion remains below -60dB for a 300mV peak-to-peak differential input at 3MHz frequency, demonstrating high linearity. The design aims to provide distortion-free and interference-
This document describes functions in VHDL. It states that a function accepts arguments and returns a result of a predetermined type. When called, actual parameters are substituted for formal parameters and the function call is replaced by the return type value. A function can define local types, constants, variables, nested functions and procedures. The keywords begin and end enclose sequential statements executed when the function is called. It then provides a simple example of an inhibit gate using a function.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
This document discusses the basic structures in VHDL, including entities, architectures, packages, configurations, and libraries. It describes how a digital system is designed hierarchically using modules that correspond to design entities in VHDL. Each entity has an external interface defined by its entity declaration and internal implementations defined by architecture bodies. Architectures can describe the design using behavioral, dataflow, or structural styles.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document discusses the implementation of Elliptic Curve Digital Signature Algorithm (ECDSA) using variable text message encryption methods. It begins with an abstract that outlines ECDSA, its advantages over other digital signature algorithms like smaller key size, and implementation of ECDSA over elliptic curves P-192 and P-256 with variable size text message, fixed size text message, and text based message encryption. It then provides details on elliptic curve cryptography, the elliptic curve discrete logarithm problem, finite fields, and domain parameters for ECDSA.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
International Journal of Computational Engineering Research(IJCER) ijceronline
This document presents an implementation of an Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol using VB.NET. ECDH is based on the elliptic curve discrete logarithm problem and allows two parties to generate a shared secret key over an insecure channel. The implementation uses an elliptic curve group over the field F29 with parameters a=1 and b=1. It demonstrates the steps to generate and exchange public keys between two users to compute the same shared secret key. This allows encryption of messages using a symmetric key algorithm. ECDH is suitable for applications requiring security where resources are limited, as smaller key sizes provide the same level of security as larger keys in other cryptosystems.
Dynamic Memory Allocation, Pointers and Functions, Pointers and StructuresSelvaraj Seerangan
After go through this ppt the learners could be able to know the c programming concepts like dynamic memory allocation, pointers and functions and pointers to structures with examples.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document provides information about getting fully solved assignments. It instructs students to send their semester and specialization name to the email address "help.mbaassignments@gmail.com" or call the provided phone number. It notes that email is preferred but calls can be made in emergencies. It then provides an example assignment for the subject BCA1040/IMC1040 - Digital Logic, including questions about converting between number systems, constructing logic gates from NAND gates, expanding Boolean functions, simplifying Boolean functions using K-maps, explaining differences between sequential and combinational circuits, and describing a serial in serial out shift register.
Verilog HDL is introduced for modeling digital hardware at different levels of abstraction. Key concepts discussed include:
- Module instantiation, assignments, and procedural blocks for behavioral modeling.
- Concurrency is modeled using an event-based simulation approach with a time wheel concept.
- Switch level and gate level modeling using built-in primitives like transistors and logic gates.
- User-defined primitives (UDPs) allow custom logic to augment pre-defined primitives.
The document provides a table of contents and questions on various technical aptitude topics such as data structures, C, C++, quantitative aptitude, UNIX concepts, RDBMS concepts, SQL, computer networks, and operating systems. It contains 35 questions related to data structures concepts like linked lists, trees, graphs, hashing etc. and their applications.
This document presents the design and implementation of an FPGA-based BCH decoder. It discusses BCH codes, which are binary error-correcting codes used in wireless communications. The implemented decoder is for a (15, 5, 3) BCH code, meaning it can correct up to 3 errors in a block of 15 bits. The decoder uses a serial input/output architecture and is implemented using VHDL on a FPGA device. It performs BCH decoding through syndrome calculation, running the Berlekamp-Massey algorithm to solve the key equation, and using Chien search to find error locations. The simulation result verifies correct decoding operation.
The document proposes a new optimized design for a binary coded decimal (BCD) adder using reversible logic gates. It summarizes the basic definitions of reversible logic and describes commonly used reversible gates like CNOT, Toffoli, Peres, TR, and MTSG gates. It then presents the conventional design of a BCD adder and proposes a new design using MTSG gates that has lower quantum cost, fewer gates, and less delay compared to existing designs. The proposed 4-bit reversible BCD adder requires only 10 gates and has a quantum cost of 40.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document describes an embedded system for measuring the temperature of an automotive engine. It discusses two methods for measuring engine temperature - using a thermistor or using an LM35 temperature sensor.
The system uses an AT89C55 microcontroller as the central processing unit and runs the μC/OS-II real-time operating system. It constructs an automatic measurement system that accurately and reliably measures temperature. Temperature readings are displayed on a graphical LCD and transmitted via UART serial communication.
The document provides details on temperature measurement circuits using a thermistor or LM35 sensor. It also includes diagrams of the schematic for the measurement system embedded in an engine control unit and photos of the prototype temperature measurement system constructed
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Dear students get fully solved assignments
Send your semester & Specialization name to our mail id :
“ help.mbaassignments@gmail.com ”
or
Call us at : 08263069601
(Prefer mailing. Call in emergency )
PPT ON VHDL subprogram,package,alias,use,generate and concurrent statments an...Khushboo Jain
this presentation includes information about - subprograms,packages,use clause, aliases,resolved signals,components,configuration,generate statements,concurrent statments and use of vhdl in simulation and synthesis.
1) The document presents designs for reversible logic gates and their applications in low power circuits. It proposes an improved design for a reversible programmable logic array (RPLA) using multiplexer and Feynman gates that is more efficient than existing designs.
2) It also proposes a method for structuring a reversible arithmetic logic unit (ALU) using reversible logic gates instead of traditional gates, achieving the same functionality with reduced information loss.
3) The RPLA design is demonstrated by implementing reversible 1-bit full adders and subtractors. Simulation results show the proposed design optimizes the number of reversible gates used.
A method to determine partial weight enumerator for linear block codesAlexander Decker
This document presents a method to determine partial weight enumerators (PWE) for linear block codes using the error impulse technique and Monte Carlo method. The PWE can be used to compute an upper bound on the error probability of the maximum likelihood decoder. As an application, the document provides PWEs and analytical performances of shortened BCH codes, including BCH(130,66), BCH(103,47), and BCH(111,55). The full weight distributions of these codes are unknown. The proposed method estimates the PWE by drawing random codewords and computing the recovery rate of known-weight codewords, obtaining the PWE within a confidence interval.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes an article from the International Journal of Engineering Research and Development that presents a design for a highly linear Operational Transconductance Amplifier (OTA). The OTA combines two linearization techniques: 1) adaptive biasing of the differential pairs using a circuit that biases the tail current based on the quadratic input voltage to cancel non-linearity, and 2) resistive source degeneration to account for mobility reduction in short channel devices. Simulation results using a 0.18um CMOS technology show that the third order harmonic distortion remains below -60dB for a 300mV peak-to-peak differential input at 3MHz frequency, demonstrating high linearity. The design aims to provide distortion-free and interference-
This document describes functions in VHDL. It states that a function accepts arguments and returns a result of a predetermined type. When called, actual parameters are substituted for formal parameters and the function call is replaced by the return type value. A function can define local types, constants, variables, nested functions and procedures. The keywords begin and end enclose sequential statements executed when the function is called. It then provides a simple example of an inhibit gate using a function.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
This document discusses the basic structures in VHDL, including entities, architectures, packages, configurations, and libraries. It describes how a digital system is designed hierarchically using modules that correspond to design entities in VHDL. Each entity has an external interface defined by its entity declaration and internal implementations defined by architecture bodies. Architectures can describe the design using behavioral, dataflow, or structural styles.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document discusses the implementation of Elliptic Curve Digital Signature Algorithm (ECDSA) using variable text message encryption methods. It begins with an abstract that outlines ECDSA, its advantages over other digital signature algorithms like smaller key size, and implementation of ECDSA over elliptic curves P-192 and P-256 with variable size text message, fixed size text message, and text based message encryption. It then provides details on elliptic curve cryptography, the elliptic curve discrete logarithm problem, finite fields, and domain parameters for ECDSA.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
International Journal of Computational Engineering Research(IJCER) ijceronline
This document presents an implementation of an Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol using VB.NET. ECDH is based on the elliptic curve discrete logarithm problem and allows two parties to generate a shared secret key over an insecure channel. The implementation uses an elliptic curve group over the field F29 with parameters a=1 and b=1. It demonstrates the steps to generate and exchange public keys between two users to compute the same shared secret key. This allows encryption of messages using a symmetric key algorithm. ECDH is suitable for applications requiring security where resources are limited, as smaller key sizes provide the same level of security as larger keys in other cryptosystems.
Dynamic Memory Allocation, Pointers and Functions, Pointers and StructuresSelvaraj Seerangan
After go through this ppt the learners could be able to know the c programming concepts like dynamic memory allocation, pointers and functions and pointers to structures with examples.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document provides information about getting fully solved assignments. It instructs students to send their semester and specialization name to the email address "help.mbaassignments@gmail.com" or call the provided phone number. It notes that email is preferred but calls can be made in emergencies. It then provides an example assignment for the subject BCA1040/IMC1040 - Digital Logic, including questions about converting between number systems, constructing logic gates from NAND gates, expanding Boolean functions, simplifying Boolean functions using K-maps, explaining differences between sequential and combinational circuits, and describing a serial in serial out shift register.
Verilog HDL is introduced for modeling digital hardware at different levels of abstraction. Key concepts discussed include:
- Module instantiation, assignments, and procedural blocks for behavioral modeling.
- Concurrency is modeled using an event-based simulation approach with a time wheel concept.
- Switch level and gate level modeling using built-in primitives like transistors and logic gates.
- User-defined primitives (UDPs) allow custom logic to augment pre-defined primitives.
The document provides a table of contents and questions on various technical aptitude topics such as data structures, C, C++, quantitative aptitude, UNIX concepts, RDBMS concepts, SQL, computer networks, and operating systems. It contains 35 questions related to data structures concepts like linked lists, trees, graphs, hashing etc. and their applications.
This document presents the design and implementation of an FPGA-based BCH decoder. It discusses BCH codes, which are binary error-correcting codes used in wireless communications. The implemented decoder is for a (15, 5, 3) BCH code, meaning it can correct up to 3 errors in a block of 15 bits. The decoder uses a serial input/output architecture and is implemented using VHDL on a FPGA device. It performs BCH decoding through syndrome calculation, running the Berlekamp-Massey algorithm to solve the key equation, and using Chien search to find error locations. The simulation result verifies correct decoding operation.
The document proposes a new optimized design for a binary coded decimal (BCD) adder using reversible logic gates. It summarizes the basic definitions of reversible logic and describes commonly used reversible gates like CNOT, Toffoli, Peres, TR, and MTSG gates. It then presents the conventional design of a BCD adder and proposes a new design using MTSG gates that has lower quantum cost, fewer gates, and less delay compared to existing designs. The proposed 4-bit reversible BCD adder requires only 10 gates and has a quantum cost of 40.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document describes an embedded system for measuring the temperature of an automotive engine. It discusses two methods for measuring engine temperature - using a thermistor or using an LM35 temperature sensor.
The system uses an AT89C55 microcontroller as the central processing unit and runs the μC/OS-II real-time operating system. It constructs an automatic measurement system that accurately and reliably measures temperature. Temperature readings are displayed on a graphical LCD and transmitted via UART serial communication.
The document provides details on temperature measurement circuits using a thermistor or LM35 sensor. It also includes diagrams of the schematic for the measurement system embedded in an engine control unit and photos of the prototype temperature measurement system constructed
This document discusses using independent component analysis (ICA) to separate electrocardiogram (ECG) signals recorded using high-density montages. It conducted experiments on five subjects using a 98-channel ECG system to record signals. An ICA algorithm was used to separate the P-wave, QRS complex, and T-wave components from the mixed signals. Results showed the components could be clearly separated, confirming ICA is an effective tool for high-density ECG analysis.
The document summarizes research evaluating the performance of different TCP congestion control variants (Tahoe, Reno, New Reno) in vehicular ad hoc networks (VANETs) using the routing protocols AODV and DSR. Simulations were conducted using OMNeT++ and SUMO simulators to measure throughput and delay. Results showed that New Reno generally performed better than Reno, while Tahoe performed similarly to New Reno except with larger network sizes where Tahoe had lower delay and higher throughput. New Reno was also found to outperform TCP Reno but not achieve the same performance as TCP Tahoe.
This document summarizes a study on implementing Total Productive Maintenance (TPM) in a manufacturing organization to improve Overall Equipment Effectiveness (OEE). TPM aims to maximize equipment availability and minimize downtime through innovative maintenance strategies. The study focuses on measuring OEE and reducing equipment downtime at a manufacturing company. It reviews literature on TPM and maintenance management. The methodology implements TPM steps and measures OEE to increase productivity, quality and profits through improved maintenance policies and continuous production process inspections.
This document discusses built-in self-test (BIST) techniques for testing field programmable gate arrays (FPGAs). It describes how the FPGA can be configured with BIST logic during offline testing to test the programmable logic blocks and interconnects. For online testing, the FPGA can be configured as a processor with an arithmetic logic unit (ALU) that has a BIST feature. The design implements a reduced instruction set computer (RISC) architecture on the FPGA with the ALU and is verified through simulation.
This document proposes new task prioritization rules for project execution that aim to improve upon the rules advocated by Critical Chain Project Management (CCPM). It presents the currently accepted CCPM rule for prioritizing tasks within a single project. Through computer simulations of over 970,000 possible cases, the proposed new rule that prioritizes based on the integration point of feeding chains is shown to result in significantly shorter project lead times. The document also proposes a new rule for prioritizing tasks across multiple projects to avoid mixing task priorities between projects. Another simulation compares this rule to the CCPM approach and again finds the proposed rule leads to faster project completion.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document discusses the bandwidth requirements of the VARSHA meteorological code when run on parallel computing systems. VARSHA is used for weather forecasting and solves nonlinear partial differential equations to predict future atmospheric states. It was originally developed sequentially but has been parallelized. The document analyzes the parallelization strategy used for VARSHA and assesses its bandwidth utilization on a Ethernet-based cluster computer in order to determine the code's bandwidth needs for efficient parallel execution.
The document describes a novel mixed method for order reduction of discrete linear systems. The method uses particle swarm optimization (PSO) to determine the denominator polynomials of the reduced order model. It then uses a polynomial technique to derive the numerator coefficients by equating the original and reduced order transfer functions. This leads to a set of equations that can be solved for the numerator coefficients. The proposed method is illustrated on an 8th order example system from literature. It is found to provide a stable 2nd order reduced model. A lead compensator is then designed and connected to improve the steady state response of the original and reduced order systems.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document analyzes the performance of two routing protocols for mobile ad hoc networks (MANETs) - the Wireless Routing Protocol (WRP) and the Ad Hoc On-Demand Distance Vector (AODV) protocol. It describes the simulation setup used to evaluate the protocols under different scenarios varying offered load, pause time, and node speed. The results show that AODV outperformed WRP in terms of packet delivery ratio, throughput, and average end-to-end delay in most scenarios, demonstrating that AODV is generally better suited for MANETs compared to WRP. The same simulation framework could be used to evaluate other routing protocols.
This document summarizes a study that used computational fluid dynamics (CFD) to analyze different catalytic converter designs with the goal of reducing particulate matter emissions and back pressure. Three catalytic converter models with different wire mesh sizes in each compartment were simulated. The model with a wire mesh size of 1.96mm in the first compartment and 1.61mm in the second (MC-1) had the lowest pressure drop, which would result in lower fuel consumption and higher engine efficiency. In conclusion, optimizing the wire mesh size can both maximize particulate filtration and limit back pressure increase inside the catalytic converter.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
PSOL quer que MPPE apure descaso com limpeza urbana em OlindaPaulo Veras
O PSOL de Olinda entrou com um pedido para que o Ministério Público de Pernambuco (MPPE) abra um inquérito civil público para investigar o descaso com a limpeza urbana
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IJERD(www.ijerd.com)International Journal of Engineering Research and Develop...IJERD Editor
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JavaLand 2024: Application Development Green Masterplan
Gy2412371242
1. Suresh Palaka, Dr. K. Srinivasa Rao / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 4, July-August 2012, pp.1237-1242
Fault Tolerant Logic Design For Multiple Faults In
Combinational Circuits
SURESH PALAKA 1, Dr. K. SRINIVASA RAO 2
1 Research Scholar, JNTUH, Hyderabad , Andhra Pradesh
2 Principal & Professor, Department of ECE, TRRCE, Hyderabad
Abstract:-
A fault detection and analysis of stuck-at faults in synchronous sequential circuits. In this paper, the
multiple fault situation is developed in a analysis discussed in [3] is reviewed and slightly
combinational circuit with basic Boolean logic modified to present a new method for deriving the
gates. Especially Boolean logic gate is proposed for shortest test sequence. Treating the present and next
the computation of multiple faults in parallel bus state of the circuit as pseudo-input and pseudo-output
lines. During programming FPGA devices there is vector respectively, a vector Boolean
a probability of lines getting fused to either stuck difference technique is utilized to determine the set of
at zero or stuck at one faults. Where conventional input/state pair that will produce a difference in
diagnosing tools analyze stuck zero and stuck one output between fault-free and faulty
faults only multiple fault cases are not considered. circuits. Assuming that fault-free and faulty circuits
Using eminent logic fault tolerant design problem start in the same initial state, they must be driven by
is solved out in this paper. applying a sequence of length one input vectors to a
state in which a difference in output is evidenced. If a
Keywords: Multiple Fault, FPGA, Boolean logic, difference in output cannot be achieved immediately
stuck-at fault based on the difference in next state, the shortest
sequence, of length > 1, of input vectors is
I. INTRODUCTION determined, which when applied will propagate the
Fault analysis is currently one of the fault to produce an output difference.
principal research areas of digital systems theory.
One of the most important problems in this area is the II. DEFINITIONS AND NOTATION
generation of fault-detection test sets for Consider a Boolean function f(u1,…,un) of
combinational logic circuits. Much effort on this the Boolean variables u1,…un. Given a combinational
problem has resulted in some significant results logic circuit realizing this Boolean function, the lines
pertaining to problems characterized by the of the circuit is labeled using the terminal numbering
assumption that only single-fault situations can convention [3] where each line of the circuit is
occur in the circuits under consideration. Recently, labeled with an integer such that the output of any
however, there has been increasing emphasis given to gate is labeled with an integer greater than that used
multiple fault situations. Arguments for the to label the input terminals of the gate. In addition,
importance of this work have been made quite well the primary inputs will be denoted as u1,…,un. The
elsewhere and will not be repeated here except to say logical value of line j, j = 1,…,m, of the circuit
that it is evident that there are many situations in clearly depends on the values of the primary
which the possibility of more than one fault existing inputs u1,…,un, and is been denoted by this relation
in the system cannot be ignored. for all lines other than the primary output line as
Xj(u1,…,un). The logical value of the primary output
Fault detection in digital circuits has emerged as an line of the circuit can, of course, be expressed entirely
important principal research area in fault-tolerant in terms of the primary inputs, but it can also be
computing. The increasing complexity and popularity expressed in terms of the primary inputs and some
of today’s LSI realization of digital circuits have specified subset of lines of the circuit, say lines i1, i2,..,
rendered the problem of fault detection, fault and ip. This is denoted as F (u1,…,un, Xi1,…,Xip,). For
analysis, and test generation extremely difficult. example, consider the combinational logic circuit of
Significant results have been achieved in generating Fig. 1. The primary output can be expressed in terms
tests for combinational logic circuits under of the primary inputs as
the assumption that only the occurrence of single
faults of a stuck-at nature is more probable. However, .
there are cases where multiple fault situations must be
considered. Several authors [l], [2] have extended the However, the primary output based on 11 and 12 can
Boolean difference technique to the multiple fault be expressed as
case in combinational circuits, and [3] in
1237 | P a g e
2. Suresh Palaka, Dr. K. Srinivasa Rao / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 4, July-August 2012, pp.1237-1242
Each line of the circuit is labeled with a unique
integer. A line numbered j has a logical value
which is dependent on the current
values of the input and state vectors. Assuming that
the initial state of the circuit is known as , the
behavior of the circuit can be described by vector-
valued Boolean output and next state functions as
follows:
(1)
Figure. 1:
(2)
In the following, to simplify the formulas which will where has the form
be developed, we will abbreviate this expression for
the logical value of the primary output line as
F(Xi2,...Xip). It will be understood that primary input
variables may also be present in the (3)
expression. Referring to the circuit of Figure 1, Iji,i = 1,2, . . . , p , is either primary input variable
from the set Xl,X2,. . . ,Xm, or one of the specified set
of internal variables of the circuit.
When it is clear that we are concerned with some In considering multiple faults, we must determine the
specific subset of the lines, say i1,…,ip, and have dominating faults and discuss about equivalent faults.
expressed the primary output accordingly as Two faults α, and β in the circuit starting in an initial
F(Xi2,...,Xip,), the expression resulting from setting state S’(0) are said to be strongly equivalent if the
Xi, = ai2,…,Xip = aip, where ai Ε {0,1}, j = 1,…,p, is output and next-state function of the circuit with fault
denoted as F(Xi, = ail ,Xi, = ai,) = F(ai1,…,ai,). α, are identical to those of the circuit with fault
Referring again to the circuit of Figure1, β. Strong equivalence of faults in a synchronous
sequential circuit reset-able to an initial state S’(0) is
or if it were clear that we were considering identical to the concept of equivalence of faults in the
F(X11,X12), it can be written as combinational circuit derived from the
synchronous sequential circuit by breaking all
feedback loops, and considering the current or present
III CIRCUIT AND FAULT DESCRIPTIONS state vector as a pseudo-input and the next-
Consider a synchronous sequential circuit state vector as a pseudo-output.
with m inputs, n outputs, and b-bits of memory as
shown in Figure 2. In vector notation, the circuit can IV BOOLEAN DIFFERENCE FORMULAS
be described as: FOR MULTIPLE FAULT ANALYSIS
Input Vector = (k) = [xi(k),…, xm(k)] The Boolean difference [1], [2] of a Boolean
Output Vector = (k) = [Y1(k),…,Yn(k)] function F(ul,….u,Xk) = F(Xk) with respect to the
State Vector = (k) = [Si(k), …, Sn( k )] variable Xk is defined as:
(4)
where 0 denotes the EXCLUSIVE-OR operator.
Similarly, the double Boolean difference of
F(ul,u2,…,UmXi,Xi) = F (Xi,Xj) with respect to Xi and
Xj is defined as:
(5)
Or
Figure 2: Synchronous Sequential Circuit
where k is the time parameter, and Xi;(k), 1 ≤ i ≤ m, (6)
Yi(k), 1 ≤ I ≤ n , and Si(k), 1 ≤ i ≤ b are Boolean
variables. And still more generally,
1238 | P a g e
3. Suresh Palaka, Dr. K. Srinivasa Rao / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 4, July-August 2012, pp.1237-1242
The state vector S’ in Eqn. (10) must be replaced by
the initial state vector S’(0) as follows:
(7)
where F-F(Xi1,…,Xi) = F(ul,…,un,Xi1,…,Xip).
(11)
Some other interesting properties of the Boolean
difference and the EXCLUSIVE-OR operation which
However, if the output functions do not depend on the
will be useful in the following are:
selected internal variables with the initial state
setting, i.e., Eqn. (11) = 0, the vector Boolean
difference of the next state
. with respect to should be considered as in the
next equation:
(8)
and
(12)
(9)
The vector Boolean differences in Eq.(11) and (12)
V. BOOLEAN DIFFERENCE EXPRESSION equal to one if any term in the sum equals to one, and
FOR MULTIPLE FAULTS IN SEQUENTIAL equal to zero only if every term in the sum equals to
CIRCUITS zero. Our next objective is to solve Eq. (11) for the
input/state pairs that will sensitize the output to the
Consider a fault involving p internal variables I’= [I j1,
differences in the specified internal variables.
Ij2,…,Ijp] simultaneously. The internal inputs can be
However, if the output functions do not depend on the
primary inputs, primary outputs, and memory lines.
selected internal variables, then Eq. (12) must be
The vector Boolean difference of the output Y’ with
solved for the input/state pairs that sensitize the next
respect to I’ is defined as [3].
state to the differences in the internal variables under
consideration. The simplified forms for Eq.(11) and
(12) are [2]:
(10)
One of the modifications to Goldstein’s work [3]
should be pointed out here. As mentioned earlier,
since Figure. 3 is just a conventional combinational (13)
circuit, Eqn. (10) should be modified with a sense of
sequential circuit, i.e., the state vectors cannot be
treated as primary input as in a “pure” combinational
circuit.
(14)
Where, 1Gα = 1G[X’,S’(0), p-tuple of decimal
equivalent of α], 1Fα = 1F[X’,S’,p-tuple of decimal
equivalent of α], and mr = p-tuple of decimal
equivalent of r.
VI DETECTING STAGES
The circuit is in a detecting state for a fault
a, if an applied input can produce a difference in
output between fault-free and fault-n circuits.
Suppose that at time t the fault-free and fault-a
circuits are in state Sff ( t ) and Sπ(t), respectively. Let
Figure 3. Combinational Circuit obtained from Sff(t) = Sx and Sπ (t) = Sy where Sx may be the same as
Synchronous Sequential Circuit of Figure 2. Sy. The pair (Sx,Sy) is called a detecting pair of states,
or shortly detecting pair, if there exists at least one
input vector which when applied to both circuits will
1239 | P a g e
4. Suresh Palaka, Dr. K. Srinivasa Rao / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 4, July-August 2012, pp.1237-1242
produce a difference in output between them at time VIII APPLICATIONS AND DISCUSSION
(t + 1) which means that the fault π is detected. In the previous section we have developed
Boolean difference formulas for various types of
Goldstein [3] has used a successor tree for keeping multiple fault situations. These results are not only
track of the states reached and the outputs generated interesting in the sense that they give a physical
by the fault-free and faulty circuits. We use a meaning to expressions which have heretofore had no
different technique called detecting tree in which the such interpretation associated with them, but are also
transition tables of both circuits are used to find the clearly useful in the fault analysis of combinational
set of detecting pairs Σ*π for fault π, and to form the circuits. The attractive completeness of the Boolean
detecting tree searching for the shortest input difference concept has been extended to the multiple
sequence which will lead the fault-π circuit from the fault case. For example, suppose we are given some
initial state to a detecting state. multiple fault. To use the developed results, we
would first determine the corresponding reduced
Since faulty lines may be memory or state lines, and multiple fault, and then express the Boolean function
since we are looking for test sequences of length realized by the circuit in terms of the primary inputs
greater than one, we may drive some of the faulty and the lines on which the reduced multiple fault
state lines to logical values that are complements of existed. If two or more components of this reduced
their faulty values in the process of driving the fault-a multiple fault were on paths of the circuit which
circuit through some different states before reaching emanated from the same fan-out point, or if one of
the first detecting state. So for simplicity, we look for the components was at a fan-out point and one or
both type I and type I1 test sets for fault π. more of the remaining components were on paths
emanating from this fan-out point, then with the
resulting Boolean expression, we would be
VII DETECTING TREE effectively considering an equivalent circuit where
If the test sequence of length one does not such a point of fan-out has been removed. This is a
exist, or the output difference between the two significant observation since it indicates that the
circuits cannot be obtained immediately, we can try results of the previous section involve an algebraic
to find a test sequence of length greater than one, if form of the conversion of a circuit to an equivalent
one exists, from the detecting tree. The procedure for fan-out-free circuit used by Schertz and Metze [4] for
construction of the detecting tree is as follows: the purposes of making combinational circuits readily
diagnosable for multiple faults.
Step 1: Form the output and next-state equations and
solve Eqns.(9) and (10). Case I (Eqn. (9) = 0, Eqn.
(10) # 0): This indicates that the output functions do IX RESULTS AND OBSERVATIONS
not depend on the specified multiple fault and the
selected internal variables at all, but the next state
functions do.
Case I1 (Eqn. (9) # 0): This is the case in which the
output functions depend on the specified multiple
fault, but not on the selected internal variables. Note
that there is no need to check if Eqn.(lO) # 0 in this
case, Case I11 (Eqns.(S) and (10) = 0): This indicates
that the fault is undetectable.
(15)
Figure 4. Write operation
+…
+ +…
+ …..
(16)
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5. Suresh Palaka, Dr. K. Srinivasa Rao / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 4, July-August 2012, pp.1237-1242
Figure 8: RTL view of the implemented system using
Xilinx synthesizer.
Figure 5. Read Operation X CONCLUSION
This paper contributes in developing
simplified Boolean logic architecture for the detection
and analysis of multiple faults in programmable
devices. A diagnosing approach for multiple faults at
one time in various lines or locations is been
suggested the simulation observations were carried
out for the suggested approach defined using VHDL
definition. The fault detecting system is analyzed for
both sequential and combinational circuits with stuck-
at one and stuck-at zero fault simultaneously.
XI REFERENCES
[1] C. T. Ku and G. M Mason, “The Boolean
Differ ence and Multiple Fault Analysis”,
Figure 6. Summarized synthesis report for the ZEEE Trans. on Computers, Vol. C-21,
developed estimation system. No.1 Jan 1975, pp.62-71.
[2] S. R. Das, P. K. Srimani, and C R. Dutta,
“On Multiple Fault Analysis in
Combinational circuits by Means of Boolean
The obtained power analysis report is obtained as, Difference”, P.m of the ZEEE Vol 64, No.9,
Sept.1976, pp.1447-1449
[3] L.H Goldstien “Analysis of Multiple Faults
in Synchronous Sequential Circuits by
Boolean Difference Techniques”, Private
Communication
[4] D R Schertz and G Metze “On the design of
multiple fault diagnosable network”, IEEE
Trans. Comput., 1361-1364, Nov 1971.
vol.C-20,pp
[5] A Dehon and M. J Wilson, “Nanowire based
Sub lithographic programmable logic
arrays”, in Proc. Int. Symp, Field program
Gate Arrays, Feb 2004, pp 123-132
[6] H. Naeimi and A DeHon, “Fault secure
encoder and decoder for memory
Figure 7. Power analysis applications”, in Proc. IEEE Int Symp
Defect Fault Tolerance VLSI Syst.,
Timing report for the implementation is observed as, Sep 2007, pp.409-417
[7] S.J. Piestrak, A.Dandache and F Monterio,
“Design ing fault secure parallel encoders
for systematic linear error correcting
codes”, IEEE Trans. reliability , vol.52
no.4, pp.492-500, jul 2003.
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6. Suresh Palaka, Dr. K. Srinivasa Rao / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 4, July-August 2012, pp.1237-1242
[8] Naeimi H and DeHon A, “Fault-tolerant
nano-memory with fault secure encoder and
decoder,” presented at the Int. Conf. Nano-
Netw., Catania, Sicily, Italy, Sep. 2007.
About the authors:
Mr. Suresh Palaka is working as an
Assistant Professor in the Dept of ECE,
HITS, Hyderabad, AP, India He is
currently pursuing Ph. D. from JNT
University, Hyderabad, India. His
research interests include Fault tolerance, Testability,
VLSI and Embedded Systems.
Dr. K. Srinivasa Rao received Ph.. D.
degree from Andhra University, India.
He is currently working as Professor of
ECE and Principal, TRRCE, Hyderabad,
AP. He has 27 years of experience in the
field of education. He is an active
member of IEEE, ISTE, SEMCEI, BMESI. He is a
Fellow of IE(l), and IETE. He has several
publications in various journal and conferences of
National and International repute. He is a resource
person for SONET, Visiting professor for ISTE .
He organized many technical events. His research
interests include Communications, VLSI and
Embedded Systems. He is guiding 09 scholars
affiliated to JNTUH & on these submitted to JNTUH.
Awaiting for vivo.
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