2016年度の日本ロボット学会において使用した資料です。

1. PEAR-LAB Utsunomiya Univ.
2016/9/9 34 1

2. PEAR-LAB Utsunomiya Univ.
SCOPE 152103014
• FPGA
•
• 27 29
2016/9/9 34 2

3. PEAR-LAB Utsunomiya Univ.
•
• SLAM Deep Learning
•
•
FPGA*
• Field Programmable Gate Array
LSI
• & [1]
• FPGA ×
• FPGA
2016/9/9 34 3
[1] Li, F., Lin, Y., He, L., and Cong, J., “Low-power FPGA using pre-defined dual-Vdd/dual-Vt
fabrics,” In Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field
programmable gate arrays (pp. 42-50). ACM, 2004.

4. PEAR-LAB Utsunomiya Univ.
• FPGA
cReComp
• cReComp creator for Reconfigurable Component
• FPGA ROS
• ROS (Robot Operating System)
•
2016/9/9 34 4

5. PEAR-LAB Utsunomiya Univ.
ROS FPGA [2]
• FPGA ROS ×
• ROS
• Programmable SoC (CPU FPGA)
• CPU-FPGA
2016/9/9 34 5
FPGA
( )
CPU FPGA
ROS
ROS
ROS
Topic
Topic
[2] Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota : “Proposal of ROS-compliant
FPGA Component for Low- Power Robotic Systems - case study on image processing application -”, Proceedings
of 2nd International Workshop on FPGAs for Software Programmers, FSP2015, pp. 62-67, 2015.

6. PEAR-LAB Utsunomiya Univ.
ROS FPGA
2016/9/9 34 6
( ) FPGA ( )
ROS
Topic
Topic
ROS
Component
(software only)
ROS FPGA
Topic
• FPGA
•
• FPGA I/F
• PWM
• HW-SW
• FPGA
• FPGA HW-SW

7. PEAR-LAB Utsunomiya Univ.
cReComp creator for Reconfigurable Component
• FPGA ROS FPGA
• HW-SW
•
Python or scrp
2016/9/9 34 7
git clone https://github.com/kazuyamashi/cReComp.git
pip install crecomp

8. PEAR-LAB Utsunomiya Univ.
cReComp
2016/9/9 34 8
•
• HDL
• HW-SW
• scrp (specification for cReComp )
• Python
•
• (HDL)
•
(C++)
• ROS msg
•
•
• SW HW
• HW SW
•
•
HW I/FSW I/F
ROS
*.v
ROS FPGA
*.cpp
( )
I/F
cReComp
*.scrp or *.py
*.v
*.msg

9. PEAR-LAB Utsunomiya Univ.
cReComp
2016/9/9 34 9
crecomp -s sensor_ctl.scrp -u sonic_sensor.v
crecomp -b sensot_ctl.scrp
sensor_ctl/
+--hardware/
+----sensor_ctl.v
+----sonic_sensor.v
+--software/
+----lib_cpp.h
+----Makefile
+----sensor_ctl.cpp
+----ros_package/

10. PEAR-LAB Utsunomiya Univ.
2016/9/9 34 10
Software
Interface
(C++)
FIFO
32-bits
sig_out
Hardware
Interface
(Verilog-HDL)
sonic_sensor
( )
write
read
HW→SW
SW→HW
/
Sensor
ROS Pub/Sub
CPU FPGA
req_in
sensor_data32
32
finish_flag
busy_flag
cReComp

11. PEAR-LAB Utsunomiya Univ.
cReComp [4]
cReComp
•
• cReComp
scrp
• 6
• FPGA 3
• C++ 1 6
• Linux 1 3
•
1. cReComp
2. Scrp
3.
( )
•
• 5
(5 × 4 ×
3 2 1 )
•
•
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0:00
0:02
0:05
0:08
0:11
0:14
0:17
0:20
1
2
3
4
5
cReComp Scrp
()
(5 1 )
Zedboard Avnet
Programmable SoC Zynq-7020 Xilinx ARM 666MHz
OS xillinux-1.3 Ubuntu12.04
ROS groovy
Parallax PING Ultrasonic Distance Sensor
FPGA
42
[4] FPGA ROS ,”
60 , 2016.
×

12. PEAR-LAB Utsunomiya Univ.
• FPGA
cReComp
• cReComp
• FPGA ROS FPGA
• HW-SW
•
•
• 10
• Visual SLAM FPGA “
2016/9/9 34 12

13. PEAR-LAB Utsunomiya Univ.
2016/9/9 34 13
cReComp :
git clone https://github.com/kazuyamashi/cReComp.git
pip install crecomp
FPGA ROS
FPGA ROS : OpenReroc
https://github.com/Kumikomi/OpenReroc
OpenReroc FPGAROS

14. PEAR-LAB Utsunomiya Univ.
*
2016/9/9 34 14