2016年度、9月RECONFにおいて使用した資料です。

1. PEAR-LAB Utsunomiya Univ.
FPGA
cReComp
2016/9/8 RECONF 1

2. PEAR-LAB Utsunomiya Univ.
•
•
•
•
FPGA
•
• HW-SW FPGA
•
• →ROS (Robot Operating System)
2016/9/8 RECONF 2

3. PEAR-LAB Utsunomiya Univ.
ROS Robot Operating System
•
•
•
• 3,000
• Publish/Subscribe
2016/9/8 RECONF 3
Publication Subscription
SubscriberPublisher
Topic
Service invocation
msg
Massage (data)
→

4. PEAR-LAB Utsunomiya Univ.
• FPGA ROS
• Publish/Subscribe
• FPGA
• HW-SW
ROS FPGA [1]
2016/9/8 RECONF 4
[1] Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota : “Proposal of ROS-compliant
FPGA Component for Low- Power Robotic Systems - case study on image processing application -”,
Proceedings of 2nd International Workshop on FPGAs for Software Programmers, FSP2015, pp. 62-67, 2015.
FPGA
( )
CPU FPGA
ROS
ROS
ROS
Topic
Topic

5. PEAR-LAB Utsunomiya Univ.
• FPGA cReComp
• cReComp
2016/9/8 RECONF 5

6. PEAR-LAB Utsunomiya Univ.
• FPGA ROS FPGA
• HW-SW
• HW
cReComp creator Reconfigurable Component [2]
2016/9/8 RECONF 6
[2] 2016/9/22 Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota,
“cReComp: Automated Design Tool for ROS-Compliant FPGA Component”,
IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16)

7. PEAR-LAB Utsunomiya Univ.
ROS FPGA
• Programmable SoC CPU FPGA
• Zynq-7000 Xilinx CycloneV Altera
•
• FPGA
• HW-SW
•
• CPU
• HW-SW
• HW-SW
2016/9/8 RECONF 7

8. PEAR-LAB Utsunomiya Univ.
cReComp
2016/9/8 RECONF 8
•
• HDL
•
• scrp
(specification for cReComp )
• Python
•
• (HDL)
•
(C++)
• ROS msg
•
•
• SW HW
• HW SW
•
•
HW I/FSW I/F
ROS
*.v
ROS FPGA
*.cpp
( )
I/F
cReComp
*.scrp or *.py
*.v
Xillybus Xillinux Xillybus IP core
*.msg

9. PEAR-LAB Utsunomiya Univ.
scrp
• scrp (specification for cReComp)
1. cReComp
2.
r_cycle_32 1 →
32bit FIFO SW 1
•
• cReComp
•
• Verilog-HDL
•
2016/9/8 RECONF 9
cReComp

10. PEAR-LAB Utsunomiya Univ.
2016/9/8 RECONF 10

11. PEAR-LAB Utsunomiya Univ.
cReComp [3]
•
• cReComp
scrp
• 6
• FPGA 3
• C++ 1 6
• Linux 1 3
•
1. cReComp
2. Scrp
3.
( )
•
• 5
(5 4
3 2 1 )
•
•
2016/9/8 RECONF 11
0:00
0:02
0:05
0:08
0:11
0:14
0:17
0:20
1
2
3
4
5
cReComp Scrp
()
(5 1 )
Zedboard Avnet
Programmable SoC Zynq-7020 Xilinx ARM 666MHz
OS xillinux-1.3 Ubuntu12.04
ROS groovy
Parallax PING Ultrasonic Distance Sensor
FPGA
42
[3] FPGA ROS ,”
60 , 2016.

12. PEAR-LAB Utsunomiya Univ.
• scrp
• scrp 27 385
• 17
•
• scrp
• scrp
•
2016/9/8 RECONF 12

13. PEAR-LAB Utsunomiya Univ.
• Python
• Python
• for
•
•
scrp
•
•
2016/9/8 RECONF 13

14. PEAR-LAB Utsunomiya Univ.
Python
2016/9/8 RECONF 14
veriloggen[4]
[4] , “Python ,” ,
RECONF2015-36, pp.21-26, 2015.

15. PEAR-LAB Utsunomiya Univ.
Python
2016/9/8 RECONF 15
python file_name.py

16. PEAR-LAB Utsunomiya Univ.
scrp
2016/9/8 RECONF 16

17. PEAR-LAB Utsunomiya Univ.
scrp
2016/9/8 RECONF 17
crecomp -b sensor_ctl.scrp

18. PEAR-LAB Utsunomiya Univ.
•
• FPGA HLS
• FPGA I/F RTL
•
→
• SSRC fir_ssrc
• Vivado HLS 14.04 Xilinx
• cReComp 1.4.4
2016/9/8 RECONF 18

19. PEAR-LAB Utsunomiya Univ.
2016/9/8 RECONF 19
C++
Verilog-HDL
•
• din_V_empty_n, dout_V_full_n
• SSRC
• ap_start, ap_ready
88 2099
44 900

20. PEAR-LAB Utsunomiya Univ.
2016/9/8 RECONF 20
state
machine
16
din_V_dout
dout_V_full_n
ap_start
din_V_empty_n
fir_top.v
input:19bit
output:40bit
dout_V_din
fir_ctl.vfir_ctl.cpp
dout_V_write
cReComp
I/F
Vivado HLS
14.04
fir_ssrc
( FIFO
10 )
• Zedboard
• SW 10 10 →
•
Zedboard Avnet
Programmable SoC Zynq-7020 Xilinx
OS xillinux-1.3 Ubuntu12.04
ROS groovy
fir_ctl.v 301 6813
fir_ctl.cpp 149 3501

21. PEAR-LAB Utsunomiya Univ.
2016/9/8 RECONF 21
Ssrc All Available
FF 226 7968 106400
LUT 323 5669 53200
ROS FPGA
Topic Topic
sample_input sample_output
•
• gettimeofday()
• FPGA Vivado Simulator Vivado 14.04
• 3.7 ms
• → 6.0ms
1.0 ms 0.9 ms
3.8 ms
FPGA → → 0.69 μs
HW-SW 3.7 ms
ROS
msg 19 byte

22. PEAR-LAB Utsunomiya Univ.
• ROS FPGA
cReComp
• cReComp
•
•
→
•
→ 10
2016/9/8 RECONF 22
git clone https://github.com/kazuyamashi/cReComp.git
pip install crecomp

23. PEAR-LAB Utsunomiya Univ.
” SCOPE 152103014
2016/9/8 RECONF 23

24. PEAR-LAB Utsunomiya Univ.
FPGA
CRECOMP
*
2016/9/8 RECONF 24

25. PEAR-LAB Utsunomiya Univ.
cReComp
2016/9/8 RECONF 25

26. PEAR-LAB Utsunomiya Univ.
fir_ssrc
2016/9/8 RECONF 26

27. PEAR-LAB Utsunomiya Univ.
FIFO
ROS msg
2016/9/8 RECONF 27
• ROS *.msg
•
• bit
•
msg