The document describes Janus, a gigaflops RISC+VLIW system-on-chip tile containing an ARM7TDMI core and a mAgic VLIW DSP core capable of 1.0 gigaflops at 100MHz. The mAgic core uses very long instruction word and dynamic program decompression to achieve 15 operations per cycle. Janus has been implemented in 180nm CMOS with a die size of 39mm2 and is targeted for applications like audio beamforming and ultrasound imaging. Dimensional analysis is used to balance instruction level parallelism, frequency, and wire delays for high performance VLIW tiles in future deep submicron technologies.
PowerDRC/LVS is an advanced physical verification toolset for checking IC layouts. It provides fast and accurate design rule checking (DRC), layout vs schematic (LVS) verification, and parasitic extraction. The toolset uses a unique one-shot processing approach that delivers maximum hardware efficiency. It has been proven at various process nodes and can scale to utilize multiple CPUs. Support and licensing options are available.
The document describes the specifications of various computer processors from Intel and AMD. It provides the clock speed, core count, cache size, manufacturing process, and other key details for processors including Core 2 Duo, Core i7, Phenom, Athlon and more. Specifically, it lists 15 different processors ranging from dual-core to quad-core models from both manufacturers.
The document discusses audio signal improvement techniques for a D740 architecture, including:
1. Spectral subtraction is proposed to remove background noise from audio signals.
2. A simple microphone preamplifier design is presented that provides amplification but has limitations in distortion performance and power consumption.
3. Future work is proposed combining spectral subtraction with direction of arrival techniques using a microphone array to further improve noise reduction.
Introduction to Vortex86DX2 Motion-Control Evaluation Boardroboard
The document describes the Vortex86DX2 system on chip from DMP Electronics, which integrates an x86 CPU with motion control modules. Key features of the SoC include integrated pulse/direction, encoder, and PWM interfaces for controlling motors and reading encoders, as well as various interrupt sources and filtering options for real-time control applications. The motion control modules support servo control, encoder reading, SSI communication, and pulse capture in different operating modes.
Universal Reconfigurable Processing Platform For Space Rev Voice4dseagrave
This document summarizes a universal reconfigurable processing platform for space applications. It provides:
- Flexible and reconfigurable processing using a LEON3FT processor, Xilinx FPGAs, and standard interfaces like SpaceWire and 1553.
- Radiation-hardened components including the LEON3FT processor and Xilinx FPGAs.
- Configurable I/O including user-defined interfaces through unused FPGA pins.
- Development features like Ethernet ports and JTAG for debugging.
This document provides information on the PIC16C7X family of 8-bit microcontrollers from Microchip. It describes the core features of the CPU including the instruction set, memory organization, I/O ports, and timer modules. It also details the peripheral features such as the synchronous serial port, USART, analog-to-digital converter, and special CPU features like interrupts and power management modes. Electrical specifications and packaging information are provided for the different devices in the family.
This document contains block diagrams and pin connections for the Quanta Computer Sandy Bridge laptop motherboard. The first page shows the overall system block diagram including components like the Sandy Bridge processor, memory, graphics interfaces, and I/O. Following pages provide more detailed diagrams for the Sandy Bridge processor showing its DMI, PCIe, FDI and clock/control pin connections. The document also includes a power stage diagram and tables of contents and pin descriptions.
This document provides a block diagram and component list for the QT8 notebook computer system. It includes details on the clock generator chip and clock signal routing. The clock generator uses a custom IC to generate various core clocks from a 100MHz spreading clock source, including clocks for the CPU, graphics, SATA, memory, and other components. Precise resistor values are specified for signal termination and level shifting of different clock signals.
PowerDRC/LVS is an advanced physical verification toolset for checking IC layouts. It provides fast and accurate design rule checking (DRC), layout vs schematic (LVS) verification, and parasitic extraction. The toolset uses a unique one-shot processing approach that delivers maximum hardware efficiency. It has been proven at various process nodes and can scale to utilize multiple CPUs. Support and licensing options are available.
The document describes the specifications of various computer processors from Intel and AMD. It provides the clock speed, core count, cache size, manufacturing process, and other key details for processors including Core 2 Duo, Core i7, Phenom, Athlon and more. Specifically, it lists 15 different processors ranging from dual-core to quad-core models from both manufacturers.
The document discusses audio signal improvement techniques for a D740 architecture, including:
1. Spectral subtraction is proposed to remove background noise from audio signals.
2. A simple microphone preamplifier design is presented that provides amplification but has limitations in distortion performance and power consumption.
3. Future work is proposed combining spectral subtraction with direction of arrival techniques using a microphone array to further improve noise reduction.
Introduction to Vortex86DX2 Motion-Control Evaluation Boardroboard
The document describes the Vortex86DX2 system on chip from DMP Electronics, which integrates an x86 CPU with motion control modules. Key features of the SoC include integrated pulse/direction, encoder, and PWM interfaces for controlling motors and reading encoders, as well as various interrupt sources and filtering options for real-time control applications. The motion control modules support servo control, encoder reading, SSI communication, and pulse capture in different operating modes.
Universal Reconfigurable Processing Platform For Space Rev Voice4dseagrave
This document summarizes a universal reconfigurable processing platform for space applications. It provides:
- Flexible and reconfigurable processing using a LEON3FT processor, Xilinx FPGAs, and standard interfaces like SpaceWire and 1553.
- Radiation-hardened components including the LEON3FT processor and Xilinx FPGAs.
- Configurable I/O including user-defined interfaces through unused FPGA pins.
- Development features like Ethernet ports and JTAG for debugging.
This document provides information on the PIC16C7X family of 8-bit microcontrollers from Microchip. It describes the core features of the CPU including the instruction set, memory organization, I/O ports, and timer modules. It also details the peripheral features such as the synchronous serial port, USART, analog-to-digital converter, and special CPU features like interrupts and power management modes. Electrical specifications and packaging information are provided for the different devices in the family.
This document contains block diagrams and pin connections for the Quanta Computer Sandy Bridge laptop motherboard. The first page shows the overall system block diagram including components like the Sandy Bridge processor, memory, graphics interfaces, and I/O. Following pages provide more detailed diagrams for the Sandy Bridge processor showing its DMI, PCIe, FDI and clock/control pin connections. The document also includes a power stage diagram and tables of contents and pin descriptions.
This document provides a block diagram and component list for the QT8 notebook computer system. It includes details on the clock generator chip and clock signal routing. The clock generator uses a custom IC to generate various core clocks from a 100MHz spreading clock source, including clocks for the CPU, graphics, SATA, memory, and other components. Precise resistor values are specified for signal termination and level shifting of different clock signals.
The MSP430G2x53 and MSP430G2x13 are ultra-low power mixed signal microcontrollers from Texas Instruments with various features including low power consumption, integrated timers, analog comparator, and communication interfaces. They are available in different package and memory configurations suitable for applications such as low-cost sensor systems that capture analog signals and transmit processed digital data.
The document discusses the hardware and software architecture of Intel-based computers. It describes the CPU components like registers, arithmetic logic unit, flags, and buses. It also explains the memory architecture with segments, real mode, and protected mode. Finally, it provides an overview of the Intel processor family from 8080 to Pentium and memory types like cache, RAM, and storage devices.
Altera is now shipping our Cyclone® IV FPGAs, the market's lowest cost, lowest power FPGAs, with an integrated 3.125-Gbps transceiver variant. Learn how to meet increasing bandwidth requirements while lowering costs in high-volume applications in this presentation. http://www.altera.com/b/cyclone-iv-fpga-shipping.html
- TSMC 10nm process with Apple's 4th generation ARMv8a architecture and M10 motion coprocessor
- Six high-performance cores and two high-efficiency cores
- 12-core GPU, 8-channel LPDDR4 memory, and PCIe NVMe SSD storage
The document discusses ASIC prototyping using FPGAs at Ericsson. It provides an overview of the ASIC prototyping team and their history of using FPGAs to prototype ASIC designs. It describes the FPGA platforms used from 2001-present, the design flow and differences between prototyping with FPGAs versus ASICs. Timescales and resources needed for FPGA firmware development are also outlined.
Webinar: Nova família de microcontroladores STM32WL – Sub Giga MultiprotocoloEmbarcados
Neste webinar você vai conhecer o primeiro microcontrolador monolítico com radio Sub Giga multi protocolo (range de frequência: 150 MHz a 960 MHz , Modulações : LoRa®, (G)FSK, (G)MSK and BPSK ). Também será apresentado o Ambiente de desenvolvimento (CubeIDE) e outras ferramentas, mostrando um exemplo de uma aplicação LoRa.
Assista o webinar em: https://www.embarcados.com.br/webinar-nova-familia-de-microcontroladores-stm32wl-sub-giga-multiprotocolo/
This document provides specifications for the THEMIS device, a high frequency front-end for GNSS equipment. It includes specifications for the targeted GNSS signals, functions, software, default parameters, file format, antenna, RF input and quality, synthesizer, synchronization, digital input/output, environmental conditions, power supply, and mechanical specifications. The device is designed to receive signals from GPS, Galileo, GLONASS, EGNOS, and IRNSS across frequency bands from 1164 to 2506 MHz.
Key Features
MGC3130 3D Tracking and Gesture Controller
Built-in 7" frame electrodes
Interface select
LED bar signalling when board is powered and indicating the communication status
Microchip’s PIC18F14K50 USB microcontroller passing messages between MGC3130 and the PC
USB mini-B connector to connect the board to a PC
Reset button resetting the MGC3130
Microchip’s MCP1801 LDO voltage regulator converting 5V USB power to 3.3V board supply
Acrylic glass (180 x 116.5 x 2 mm) simulating the housing of a target device
Plastic rivets mounting the acrylic glass to the PCB
Supports Windows XP, Windows 7 or Windows 8 Operating system
- See more at: https://www.pantechsolutions.net/gesture-kit#sthash.5i5RiEmE.dpuf
This document describes various PCIe/104 form factor modules for real-time embedded applications including sensors, software defined radios, and test and measurement equipment. It lists modules with FPGAs and high-speed analog-to-digital converters and digital-to-analog converters for applications such as radar control systems, lidar instruments, signal generators, satellite testbenches, software defined radios, ultrasound instruments, sonar applications, and digital video systems. Contact information is provided for technical sales support.
This document discusses advanced design methodologies used at Philips Semiconductors. It describes the increasing complexity of chip designs over time, from early 3000 gate chips to modern chips with over 1 million gates. It also outlines various prototyping platforms used at Philips, such as Xplorer boards with FPGA tiles, to allow testing of designs before final silicon. Advanced methodologies such as UML, system C, and automatic platform building tools are needed to manage today's highly complex system on chip designs with both hardware and software components.
The document provides information on various DSP companies and their products. It discusses Analog Devices' ADSP-218xN and EZ-KIT Lite evaluation boards, as well as its ADSP-2191, ADSP-21535, ADSP-BF561, ADSP 21mod980, ADSP-TS201/202/203, and ADSP-TS201S processors. It also summarizes Texas Instruments' OMAP1510 application processor and TMS320C54CST client-side telephony DSP, among other TI products. Hitachi Semiconductor of America's SH7727 microprocessor is also mentioned. The document concludes with information on DSP products from various other companies.
The document provides an inventory report of PCs at an organization. It lists 22 PCs divided among different departments like Call Center, Tech, HR/Admin, Finance and Help Desk. It provides details of each PC like processor, RAM, HDD and other specifications. There is also an inventory of machines at the co-location center including routers, NTUs, firewalls, modems, switches and UPS. It ends with a summary of total machines in each category.
This document contains a table of contents and schematic for a board design. The table of contents lists over 60 pages covering topics like the power supply topology, PoE supplies, voltage regulators, Ethernet and PCIe interfaces, and more. The schematic shown is for the PoE supply-A which uses a mosfet bridge and isolated DC/DC converter to provide 12V from the 57V PoE input.
Webinar: Criando Soluções LoRaWAN Otimizadas com Silicon LabsEmbarcados
Webinar apresentado no dia 11/03 através do Embarcados. Para mais detalhes acesse: https://www.embarcados.com.br/webinars/webinar-criando-solucoes-lorawan-otimizadas-com-silicon-labs/
Participe dos webinars do Embarcados: https://www.embarcados.com.br/webinars/
This document provides information about Xilinx Zynq UltraScale+ MPSoCs, including:
- An overview of the different device types - CG (commercial grade), EG (extended temperature), and EV (automotive) with their key components.
- Block diagrams and descriptions of the processing system and programmable logic for each device type.
- Tables comparing the specifications of devices within each type such as logic resources, memory, connectivity, and integrated IP.
- Potential applications for each device type including image processing, video, networking, and more.
Nanos and Nanos2 modules catalog september 2014ETEP
The document describes NanoS and NanoS2 airborne data acquisition modules. It provides an overview and specifications for various module types including analog input modules, digital communication modules, and video/audio modules. Module options include single-ended voltage, current measurement, accelerometers, thermocouples, strain gauges, and digital bus interfaces. The modules range from 1 to 64 channels and sample rates from 1 Hz to 200 kHz depending on the module type and application.
The V30 GNSS RTK system is a dual-frequency, multi-constellation GNSS receiver with 220 tracking channels. It is designed for high-precision surveying applications including static, PPK, and RTK surveys. Key features include multi-day battery life, rugged design, integrated radio options, and compatibility with various field controllers and software.
This document discusses the development of an RFID-MIMO prototype using GNU Radio. The goal is to set up a testbed using USRP devices to implement MIMO for UHF RFID systems and compare performance to single antenna solutions. It describes implementing a single antenna listener first, then adding selection combining as a diversity combining technique with two antennas. Results show selection combining improves read range and listener success ratio over a single antenna. The document concludes by proposing implementing maximal ratio combining next to further improve performance.
La Feria de Cali se celebra anualmente entre el 25 y 30 de diciembre en Cali, Colombia. Este evento atrae a unos 2 millones de personas locales y 500,000 visitantes para disfrutar de espectáculos, conciertos, desfiles y gastronomía. El documento ofrece paquetes publicitarios para empresas que deseen promocionarse durante la feria a través de publipostes, publipuentes, vallas y otras opciones.
This document appears to be a creative portfolio belonging to Ankit Pareek. It lists various copywriting and creative projects he has worked on for brands such as Jaipur Pink Panthers, Smaaash, Monky Ink Blots, EPlus, DHL, and APM Terminals. The projects include landing pages, websites, print ads, emailers, in-store communications, videos, menu cards, branding, and promotional materials. The overall purpose of the portfolio is to showcase Ankit Pareek's copywriting and creative concept work for various clients and briefs.
The MSP430G2x53 and MSP430G2x13 are ultra-low power mixed signal microcontrollers from Texas Instruments with various features including low power consumption, integrated timers, analog comparator, and communication interfaces. They are available in different package and memory configurations suitable for applications such as low-cost sensor systems that capture analog signals and transmit processed digital data.
The document discusses the hardware and software architecture of Intel-based computers. It describes the CPU components like registers, arithmetic logic unit, flags, and buses. It also explains the memory architecture with segments, real mode, and protected mode. Finally, it provides an overview of the Intel processor family from 8080 to Pentium and memory types like cache, RAM, and storage devices.
Altera is now shipping our Cyclone® IV FPGAs, the market's lowest cost, lowest power FPGAs, with an integrated 3.125-Gbps transceiver variant. Learn how to meet increasing bandwidth requirements while lowering costs in high-volume applications in this presentation. http://www.altera.com/b/cyclone-iv-fpga-shipping.html
- TSMC 10nm process with Apple's 4th generation ARMv8a architecture and M10 motion coprocessor
- Six high-performance cores and two high-efficiency cores
- 12-core GPU, 8-channel LPDDR4 memory, and PCIe NVMe SSD storage
The document discusses ASIC prototyping using FPGAs at Ericsson. It provides an overview of the ASIC prototyping team and their history of using FPGAs to prototype ASIC designs. It describes the FPGA platforms used from 2001-present, the design flow and differences between prototyping with FPGAs versus ASICs. Timescales and resources needed for FPGA firmware development are also outlined.
Webinar: Nova família de microcontroladores STM32WL – Sub Giga MultiprotocoloEmbarcados
Neste webinar você vai conhecer o primeiro microcontrolador monolítico com radio Sub Giga multi protocolo (range de frequência: 150 MHz a 960 MHz , Modulações : LoRa®, (G)FSK, (G)MSK and BPSK ). Também será apresentado o Ambiente de desenvolvimento (CubeIDE) e outras ferramentas, mostrando um exemplo de uma aplicação LoRa.
Assista o webinar em: https://www.embarcados.com.br/webinar-nova-familia-de-microcontroladores-stm32wl-sub-giga-multiprotocolo/
This document provides specifications for the THEMIS device, a high frequency front-end for GNSS equipment. It includes specifications for the targeted GNSS signals, functions, software, default parameters, file format, antenna, RF input and quality, synthesizer, synchronization, digital input/output, environmental conditions, power supply, and mechanical specifications. The device is designed to receive signals from GPS, Galileo, GLONASS, EGNOS, and IRNSS across frequency bands from 1164 to 2506 MHz.
Key Features
MGC3130 3D Tracking and Gesture Controller
Built-in 7" frame electrodes
Interface select
LED bar signalling when board is powered and indicating the communication status
Microchip’s PIC18F14K50 USB microcontroller passing messages between MGC3130 and the PC
USB mini-B connector to connect the board to a PC
Reset button resetting the MGC3130
Microchip’s MCP1801 LDO voltage regulator converting 5V USB power to 3.3V board supply
Acrylic glass (180 x 116.5 x 2 mm) simulating the housing of a target device
Plastic rivets mounting the acrylic glass to the PCB
Supports Windows XP, Windows 7 or Windows 8 Operating system
- See more at: https://www.pantechsolutions.net/gesture-kit#sthash.5i5RiEmE.dpuf
This document describes various PCIe/104 form factor modules for real-time embedded applications including sensors, software defined radios, and test and measurement equipment. It lists modules with FPGAs and high-speed analog-to-digital converters and digital-to-analog converters for applications such as radar control systems, lidar instruments, signal generators, satellite testbenches, software defined radios, ultrasound instruments, sonar applications, and digital video systems. Contact information is provided for technical sales support.
This document discusses advanced design methodologies used at Philips Semiconductors. It describes the increasing complexity of chip designs over time, from early 3000 gate chips to modern chips with over 1 million gates. It also outlines various prototyping platforms used at Philips, such as Xplorer boards with FPGA tiles, to allow testing of designs before final silicon. Advanced methodologies such as UML, system C, and automatic platform building tools are needed to manage today's highly complex system on chip designs with both hardware and software components.
The document provides information on various DSP companies and their products. It discusses Analog Devices' ADSP-218xN and EZ-KIT Lite evaluation boards, as well as its ADSP-2191, ADSP-21535, ADSP-BF561, ADSP 21mod980, ADSP-TS201/202/203, and ADSP-TS201S processors. It also summarizes Texas Instruments' OMAP1510 application processor and TMS320C54CST client-side telephony DSP, among other TI products. Hitachi Semiconductor of America's SH7727 microprocessor is also mentioned. The document concludes with information on DSP products from various other companies.
The document provides an inventory report of PCs at an organization. It lists 22 PCs divided among different departments like Call Center, Tech, HR/Admin, Finance and Help Desk. It provides details of each PC like processor, RAM, HDD and other specifications. There is also an inventory of machines at the co-location center including routers, NTUs, firewalls, modems, switches and UPS. It ends with a summary of total machines in each category.
This document contains a table of contents and schematic for a board design. The table of contents lists over 60 pages covering topics like the power supply topology, PoE supplies, voltage regulators, Ethernet and PCIe interfaces, and more. The schematic shown is for the PoE supply-A which uses a mosfet bridge and isolated DC/DC converter to provide 12V from the 57V PoE input.
Webinar: Criando Soluções LoRaWAN Otimizadas com Silicon LabsEmbarcados
Webinar apresentado no dia 11/03 através do Embarcados. Para mais detalhes acesse: https://www.embarcados.com.br/webinars/webinar-criando-solucoes-lorawan-otimizadas-com-silicon-labs/
Participe dos webinars do Embarcados: https://www.embarcados.com.br/webinars/
This document provides information about Xilinx Zynq UltraScale+ MPSoCs, including:
- An overview of the different device types - CG (commercial grade), EG (extended temperature), and EV (automotive) with their key components.
- Block diagrams and descriptions of the processing system and programmable logic for each device type.
- Tables comparing the specifications of devices within each type such as logic resources, memory, connectivity, and integrated IP.
- Potential applications for each device type including image processing, video, networking, and more.
Nanos and Nanos2 modules catalog september 2014ETEP
The document describes NanoS and NanoS2 airborne data acquisition modules. It provides an overview and specifications for various module types including analog input modules, digital communication modules, and video/audio modules. Module options include single-ended voltage, current measurement, accelerometers, thermocouples, strain gauges, and digital bus interfaces. The modules range from 1 to 64 channels and sample rates from 1 Hz to 200 kHz depending on the module type and application.
The V30 GNSS RTK system is a dual-frequency, multi-constellation GNSS receiver with 220 tracking channels. It is designed for high-precision surveying applications including static, PPK, and RTK surveys. Key features include multi-day battery life, rugged design, integrated radio options, and compatibility with various field controllers and software.
This document discusses the development of an RFID-MIMO prototype using GNU Radio. The goal is to set up a testbed using USRP devices to implement MIMO for UHF RFID systems and compare performance to single antenna solutions. It describes implementing a single antenna listener first, then adding selection combining as a diversity combining technique with two antennas. Results show selection combining improves read range and listener success ratio over a single antenna. The document concludes by proposing implementing maximal ratio combining next to further improve performance.
La Feria de Cali se celebra anualmente entre el 25 y 30 de diciembre en Cali, Colombia. Este evento atrae a unos 2 millones de personas locales y 500,000 visitantes para disfrutar de espectáculos, conciertos, desfiles y gastronomía. El documento ofrece paquetes publicitarios para empresas que deseen promocionarse durante la feria a través de publipostes, publipuentes, vallas y otras opciones.
This document appears to be a creative portfolio belonging to Ankit Pareek. It lists various copywriting and creative projects he has worked on for brands such as Jaipur Pink Panthers, Smaaash, Monky Ink Blots, EPlus, DHL, and APM Terminals. The projects include landing pages, websites, print ads, emailers, in-store communications, videos, menu cards, branding, and promotional materials. The overall purpose of the portfolio is to showcase Ankit Pareek's copywriting and creative concept work for various clients and briefs.
- The document appears to be discussing a meeting or discussion involving multiple topics. It mentions percentages, numbers, and questions/responses between various individuals.
- Key details that emerge include discussing percentages related to a recent election outcome, debating policy proposals, and questions around balancing budgets and spending on programs.
- There is debate on various budget and spending proposals, with individuals questioning and responding to each other on balancing priorities and managing within financial constraints.
The document discusses the implementation of best practices in two companies. It finds that Company A takes a broad and incremental approach to implementation, initially seeing reduced performance but gradual improvement over time. Company B's "big bang" approach does not seem to lead to deterioration in performance. The document aims to provide insight into how implementation approaches influence performance outcomes.
Este documento presenta los resultados de la cuarta fecha del cross country familiar en Sausalito, Viña del Mar. Dividió a los participantes en varias categorías por edad y sexo, e incluyó el nombre, número y tiempo de los tres primeros lugares de cada categoría. Carlos Villa fue el ganador de la categoría de adultos jóvenes varones con un tiempo de 6:58. Agustín Medina Tapia ganó la categoría de senior de 51 años o más varones con un tiempo de 8:13.
Mobutu received plane from president KennedyThierry Debels
On Jan 8 1979, there was a lunch between president Mobutu and a US citizen (probably the ambassador of the US in Brussels).
The lunch is being served in the house of Mobutu near Brussels.
It is a very positive conversation.
Mobutu mentions the plane he received from president Kennedy (in 1963).
HE SPOKE WARMLY AND AT LENGTH OF THREE PREVIOUS VISITS TO THE UNITED STATES, AND IN PARTICULAR OF HIS MEETING WITH PRESIDENT KENNEDY (WHO, HE NOTED IN PASSING, HAD GIVEN HIM AN AIRPLANE).
Mobutu is very positive about the US and ‘he spoke warmly of his 3 visits to the US’.
This telex is in stark contrast to the general opinion.
The meeting between JFK and Mobutu took place in early 1963 in Washington. Mobutu was offered a gift from the president of the USA, in order to underline the enduring relations between the two nations.
Mobutu was major-general at that time.
‘Surprise for him, as this vintage “Jalopy” Aircraft arrived: it was a personal gift from JFK after their meeting, and indeed Mobutu was disappointed – no brand new Jet, he got an 18 year old DC-3 instead’, states dc3dakotahunter.com.
And in 1976 Henry Kissinger was aboard Mobutu’s yacht.
Mobutu: “In 1963, I came to Washington to see President Kennedy and in our discussions, he said I ought to have a small jet aircraft so that I could more easily move about the country; in those days I did not even have a Piper Cub. But there was one colonel there who explained that I did not need an executive jet. What I really needed was a DC-3. If I want to fly from here to Lubumbashi in a DC-3, it’s a five and one-half hour flight.”
Kissinger: “And what did you get?”
Mobutu: “The Colonel prevailed. I got a DC-3.”
Kissinger: “They always like to get rid of their old equipment.”
But as stated in the private conversation in 1979, Mobutu was very happy with this
Este documento presenta tres paquetes publicitarios (Oro, Plata y Bronce) para promover marcas y productos durante el Carnaval de Barranquilla de 2017, del 25 al 28 de febrero. El paquete Oro incluye la mayor variedad de elementos publicitarios como vallas, paraderos de bus, autobuses y pantallas LED por un valor total de $151.220.000. El paquete Plata incluye menos elementos por un valor de $99.482.500, y el paquete Bronce es el más básico por $51.930.000
Victor presenta fotos suyas, de sus amigos y familiares, así como de sus mascotas. Incluye una foto hipotética de cómo se vería con barba y varias imágenes reales suyas y de las personas cercanas a él.
Este documento presenta los planes de mejoramiento para estudiantes de cuarto grado del Colegio Técnico Benjamín Herrera en las áreas de matemáticas y español. Los planes incluyen objetivos, conceptos, actividades y evidencias de aprendizaje para fortalecer las competencias de los estudiantes. También presenta ejemplos de ejercicios de matemáticas y lectura comprensiva en español para que los estudiantes demuestren su comprensión.
El documento discute la importancia de la cultura en el comercio internacional. Explica que la cultura incluye las costumbres, creencias y tradiciones compartidas por un grupo que influyen en cómo se realizan los negocios. La cultura determina las reglas y protocolos de interacción, y si un producto o idea no se alinea con la cultura, es probable que sea rechazado. Por lo tanto, entender y respetar la cultura local es fundamental para el éxito comercial.
El documento presenta las instrucciones para una evidencia de aprendizaje en la unidad 3 de Administración de Recursos Informáticos. Los estudiantes deben crear una presentación en SlideShare sobre temas como diagnóstico organizacional, cultura organizacional, evaluación del desempeño, mejora organizacional y reingeniería, y enviar la dirección de la presentación al docente para su evaluación.
El documento describe los formatos y elementos básicos para la creación de guiones de ficción y corporativos. Explica que el cine de ficción se basa en la recreación de la realidad utilizando una estructura dramática. Luego enumera 10 reglas básicas para la escritura de guiones, como enumerar todas las escenas de forma consecutiva, incluir encabezados para cada escena con la locación y momento del día, y usar mayúsculas y doble espacio para separar diferentes secciones. El objetivo es proporcionar una guía para el des
This document provides an overview of pediatric compounding sterile preparations. It discusses how pediatric medicine considers the specific healthcare needs of children. Pediatric compounding involves preparing small volume sterile solutions and considering factors like pediatric dosing, formulations, administration routes, potential complications, and USP guidelines. The document outlines supplies and procedures for compounding a pediatric special dilution, including anteroom and clean room preparation steps.
Educating Pharmacy Technicians for Success: Understanding Current Issues in ...FLAVORx
Presenter Ursula Chizhik, PharmD discuses common barriers to medication adherence and reviews the anatomy and physiology of taste and identify how taste can impact medication adherence. She will also explain the importance of choice and patient preferences with regards to medication adherence and highlight how flavoring can improve the patient medication experience and ultimately increase .
This document discusses morphological changes caused by viral infections, known as cytopathic effects (CPE). It describes how John Franklin Enders classified viruses based on their CPE. Common CPE include cell destruction, degeneration, swelling, clumping, fusion, and inclusion bodies. Specific examples of CPE are provided for measles, mumps, herpes simplex, varicella-zoster, cytomegalovirus, Epstein-Barr virus, HPV, and rabies viruses. Techniques for studying viruses include cell culture, electron microscopy, and examining clinical signs in infected tissues.
South Korea--Macro Environmental Analysistomasptacek
This document analyzes the macro-environment of South Korea across several factors. It finds that South Korea presents:
1) Low risk overall, with a stable political system, rule of law, and supportive policies for business.
2) Moderate risks around property rights protection and transparency/corruption. Environmental issues also pose moderate risks.
3) High risks are limited to restrictions around raw materials sourcing and property taxes. Protection of intellectual property rights also carries high risk.
The document summarizes the current landscape of dengue vaccine development. Several companies are developing both live-attenuated and recombinant subunit dengue vaccines. Clinical trials are underway to evaluate the first tetravallent vaccine from Sanofi Pasteur. Licensure of the first dengue vaccine may occur as early as 2013, with two or more vaccines potentially available by 2016. Rapid progress is being made but preparations for introduction and implementation of dengue vaccines must be made within the next three years.
This project aims to develop ubiquitous low-power image processing platforms. It has several objectives including defining a reference platform, instantiating it through use cases, and demonstrating performance improvements. Several partners from industry and academia are involved. Key tasks include selecting hardware components, developing interfaces and tools, and validating the platform using applications like medical imaging, automotive driver assistance, and unmanned aerial vehicles. An initial hardware instance was selected using the Sundance EMC2 board with an ARM CPU and FPGA. The UAV use case involves real-time stereo depth estimation for obstacle avoidance.
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The MYC-C7Z015 CPU Module is an SOM (System on Module) board based on Xilinx XC7Z015 (Z-7015) All Programmable System-on-Chip (SoC) which is among the Xilinx Zynq-7000 family, featuring integrated dual-core ARM Cortex-A9 processor with Xilinx 7-series FPGA logic, four 6.25Gbps SerDes transceivers and one PCIe Gen2 x 4 integrated block. The MYC-C7Z015 module has 1GB DDR3 SDRAM, 4GB eMMC, 32MB quad SPI Flash, a Gigabit Ethernet PHY, a USB PHY and external watchdog on board. It provides a large number of I/O signals for ARM peripherals and FPGA I/Os through two 0.8mm pitch 140-pin board-to-board connectors, which is ideal for your next embedded design.
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Webinar: NVIDIA JETSON – A Inteligência Artificial na palma de sua mãoEmbarcados
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Convidado: Marcel Saraiva
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this presentation is a great to deliver in classrooms, stage or also can be used to deliver lecture on "Evolution of processor".
it is also very helpful to learn about microprocessor, directly we can say its a self pack containing all about microprocessor.
this ppt contains evolution not only on the basis of generations but also on the basis of their invention.
must gothrough it
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1. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 1
Janus – A Gigaflop RISC + VLIW SoC Tile
Pier S. PAOLUCCI a,b,*, Ben ALTIERI a, Federico AGLIETTI a,
Stefano V. BASILE a, Piergiovanni BAZZANA a, Sergio BRUZZONE a,
Alessandro CATASTA a, Antonio CERRUTO a, Maurizio COSIMI a,
Yves FUSELLA d, Philippe KAJFASZ c, Andrea MICHELOTTI a,
Elena PASTORELLI a, Silvia PIRIA a, Enrico REMONDINI a,
Andrea RICCIARDI a, Fabrizio ROSCIARELLI a
– a IPITEC srl, an ATMEL Company, Via Vito Giuseppe Galati 87, 00155 Roma, Italy
– b INFN Roma, Dip. Fisica Uni. Roma “La Sapienza”, P.le Aldo Moro 5, 00185 Roma, Italy
– c THALES Communications 66, rue du Fossé Blanc – BP 156 - 92231 Gennevilliers Cedex, France
– d ATMEL, Zone Industrielle 13106 Rousset cedex, France
– *Corresponding author: pier.paolucci@roma1.infn.it (Pier Stanislao PAOLUCCI)
3. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 3
Agenda (2/2)
Dimensional Analysis for Deep Sub-Micron
(DSM) VLIW tile design methodology for high
performance at moderate clock speed
– ILP*frequency vs. Wire Delay balance on present and future designs
– Memory area vs. Operator Area on present and future designs
– Validation of the dimensional analysis using mAgic detailed Gate
Counts and Technological Implementation feedbacks.
– Tiles for Short Wires:
RISC+VLIW Tile for SoC on future DSM designs
Hypothesis for a 90 nm multiple tile design
4. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 4
mAgic™ DSP Core
1.0 Gigaflops @ 100 MHz, 15 ops/cycle
Complex Domain, 40-bit Floating Point VLIW DSP Core
Seamless VLIW: from linear assembler to VLIW scheduling
DyProDe: Dynamic Program Decompression: 4 PM bit/op
Low clock, high ILP core: easier SoC Design Closure, less
internal pipelines (no need for custom operators), higher
efficiency on applications
Memory mapped slave on the controller’s system bus
Expected dissipation: less than 500mW (typical)
2.4X the performance or 41% the clock at 40 bit vs.
classical 32-bit stand-alone floating point DSP
5. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 5
mAgic™ VLIW DSP core Architecture
mAgic – ARM I/F
PARM Memory
Left 512x40
PARM Memory
Right 512x40
Data Memory
Left 6Kx40
Data Memory
Right 6Kx40
Buffer Data
Memory Left
2Kx40
Buffer Data
Memory Right
2Kx40
External Memory I/F
Multiple
Address
Generation
Unit
Address
Register
File
Operator
Block
Data
Register File
VLIW Program Memory
Flow control and VLIW Decoder
Instruction
Decoder
Condition
Generation
Status
Register
Program
Counter
On chip 8 k*128 VLIW
Program Memory
(equivalent to 24k using
our patented DyProDe
Code compression
scheme)
2*256 entry multi-port
Register File
On core 8 k*80 Data
Memory
10 arithmetic operation
per cycle, native
complex arithmetic,
single cycle butterfly
Multiple Address
Generation Unit
6. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 6
Native Complex Domain Arithmetic
Significant DSP applications regard wave-processing in
audio, radio or ultrasound domains complex domain
The area required for each floating point arithmetic operator
is <1/2 mm2 on 180 nm and ~0.1 mm2 on 90 nm CMOS.
mAgic VLIW DSP benchmarks (Native Complex Domain
Support, added operators, added memory bandwidth):
–1024 points FFT:
5962 cycles on mAgic VLIW DSP vs 14400 on C67
–64 output from a 64 taps complex FIR filter:
4663 cycles on mAgic VLIW DSP vs. 8225 on C67
– Single cycle butterfly (40 bit floating point)
– Single cycle complex mulacc (40 bit floating point)
7. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 7
mAgic™ Operator block
• Operator
Block: 10
Float/Int Op
per Cycle
• Complex
Arithmetic
support
• Vector 2
Arithmetic
• Butterfly
Arithmetic
• Large (512)
Multiport
(8+8)
Register File
Conv2
Div2
Sh/Log2
Conv1
Div1
Sh/Log1
LEFT
0 1 2 3
4 5 6 7
FP/I
*
FP/I
*
RIGHT
0 1 2 3
4 5 6 7
FP/I
*
FP/I
*
FP/I
-
FP/I
+
FP/I
- +
FP/I
+ -
L Memory R Memory
LMemory
RMemory
Mul1 Mul2 Mul4Mul3
Cadd1 Cadd2
Add1 Add2
Min
Max2
Min
Max1
8. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 8
Automatic VLIW Scheduling
The designer writes in a serial fashion, and the
assembler schedules optimized code that takes
advantage of the DSPs Instruction Level Parallelism,
accounting for data dependencies and latencies
IS SCHEDULED AS:
A=B+C; D=E*F;Q=Memory[I]
L=M+N;
G=A+D; P=Q*R
A SEQUENTIAL CODE LIKE:
A=B+C
D=E*F
G=A+D
L=M+N
Q=Memory[I]
P=Q*R
9. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 9
Multiple Address Generation Unit
S: 11 bits Start reg,
vector absolute base
address or circular
buffer starting address
L: 11 bits Length reg,
vector length
A: 11 bits Address
reg, offset or abs base
address
M: 7 bits Increment
reg, increment
P: 9 bits Page reg, for
internal memories
pages addressing
Description Address out Modified A
Assembly
suffix
Just Use S+A A -
Modify & Use S+A+M A M
Use Modify & Update S+A A+M U
Modify Use & Update S+A+M A+M MU
Just Use S+A A -
Modify & Use S+A+M A M
Use Modify & Update S+A A+M U
Modify Use & Update S+A+M A+M MU
Just Use S+A A -
Modify & Use S+ (A+M)mod.L A M
Use Modify & Update S+A (A+M)mod.L U
Modify Use & Update S+ (A+M)mod.L (A+M)mod.L MU
Modular:
Offset:
L=0
Linear:
S=L=0
SLAMP fields and MAGU Addressing Modes
10. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 10
mAgic™ DSP Core interface with SoC Bus and
External Memories
Slave memory
mapped device on
the controller’s
system bus
1.6 Mbit internal
Program and Data
Core Memories are
memory mapped as
well
XM DMA and SoC
System Bus activities
run in parallel with
the core on
dedicated Double
Port Buffers
mAAR
Core Memories
mAgic DSP core
Global
Sequencer
mAgic Internal Resources Mapper (mIrm )
PM
P2P3
XM
Burst Service
Local Sequencer
Register
File
Operators
M
A
G
U
PC
P 4
P1 P0
CSE Reg
mAgic System Mode Interface
ASB slave Wrapper
Registers
11. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 11
Examples of target Gigaflops Applications
Hands free home phone
– Audio Beam-Forming
Better audio hearing aids and ear prosthesis / Real time
modeling of cochlea
– Real-time Differential Equation Solution
Missile Guidance / Seeker
– Radar Beam-forming / Anti-jamming
SW Ultrasound Scanner / Better Diagnostic Image Quality
– Ultrasound Beam-forming
JANUS: An ARM7TDMI + mAgic VLIW DSP SoC for those
applications.
12. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 12
Janus: a DUAL CORE VLIW DSP + RISC
mAgic VLIW FiPU DSP:
1.5 GOPS @ 100 MHz
(1.0 GFLOPS)
32 bit ARM7TDMI RISC
Set of SoC peripherals
1.9 Mbit SRAM on Board
352 BGA, 243 functional I/O
1.2 W worst case @ 100 MHz
Arm7TDMI
32K ARM
Mem
ASB / APB Bridge
mAgic VLIW
GigaFlops
DSP core
8Kx128 bit
Program
Mem
Shared
Memory
Data Buffer 2 x 2k word
Double Bank, Double Port
Amba ASB
EBI
Data / Program Bus Mux
Program Bus
Mux / Demux
Data Bus
Mux / Demux
Data Mem
2 x 6k x 40 bit
Double Bank
Double Port
SPI0
USART0
USART1
TIMER
Watchdog
PIO
PDC
ADDA
Clock Gen
IRQ Ctrl
Run Mode data paths
System Mode data paths
ARM exclusive data paths
SPI1
13. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 13
Janus Floorplan & Technological Measurements
DSP Reg Files:
2 * 8 Ports *
256 Regs * 40 bit
mAgic VLIW floating point
DSP SW Core: 15
op/cycle, 390 Kgate
DSP Progr SRAM:
2 * 1 Port *
8K * 64 bit
ARM7TDMI 32 BIT
RISC CORE
RISC
PERIPHERALS:
135 Kgate
RISC SRAM:
4 * 1 Port *
8K * 8 bit
DSP Data SRAM:
8 * 2 Ports *
2K * 40 bit
Atmel 180 nm, five-level, Aluminum CMOS
Pad excluded, 39 mm2
Pad included, 55 mm2
243 functional IO
352 Ball Grid Array package
1.8 V (Core), 3.3 V (I/O)
<1.2 W (worst case) @ 100MHz
1.5 Gops, 1.0 Gigaflops
55 Kgate/mm2 effective density (10 mm2 for
550Kgate logic required for the software
macros: VLIW DSP + Arm peripherals +
testability stuff)
14. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 14
HW Tools: JANUS Test & Evaluation Board
CLK
DIV
3.3V
RST
PLL
PIO
PIO
ARM DATA H
SRAM
128Kx8
ARM DATA L
SRAM
128Kx8
FLASH
ARM PRG
512Kx16
SSRAM
MAGIC
DATA L
128Kx36
EXTCLK
MTM DIP SWITCH
SPI-0
M-ICE
USART 0
RS232
Janus
PIO USARTs
RST
XMA
XMD[15:0]
CLKs
CNTRLs
SPIsADDA
ARMD
PLL
ICE
ARMC
ARMA
XMD[55:40]
XMD[31:16]
XMD[71:56]
XMD[39:32]
XMD[79:72]
SPI-1
SSRAM
MAGIC
DATA H
128Kx36
SSRAM
MAGIC
DATA E
128Kx36
USART 1
USB
CNTRL
USB
D-9 RS232D-9 RS232
RS232RS232
3.3-1.8
EXT
PSU
uPR
CODEC
LED
BUFF
CODEC
(opt)
CODEC
(opt)
CODEC
(opt)
LINE
IN
LINE
OUT
LINE
IN
(opt)
LINE
OUT
(opt)
LINE
IN
(opt)
LINE
OUT
(opt)
LINE
IN
(opt)
LINE
OUT
(opt)
CLK
DIV
25
MHz
MTM Works @ 100MHz and
Provides the following resources:
– Memories for mAgic and ARM
– Stereo Audio CODECs (up to 4)
– Serial I/O:
1 USB 2.0 Full Speed (12 Mbps)
2 RS232/LVTTL a/sync serial lines
2 SPI serial I/O lines
1 ÷ 4 audio codecs
– IO connectors (USART, SPI, PIO, AUDIO)
– Configuration DIP SWITCH
– Status 7-segment Display
– JTAG ARM M-ICE connector
– Size: 5 x 5 inch2 (12.7x12.7 cm2)
15. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 15
Development Effort
Our SIMD/VLIW mAgic DSP architecture is largely based on the
know-how acquired by some of the authors thanks to their
participation to three generations of the Massively Parallel
Processing experiment APE, conducted since 1983 by INFN (Istituto
Nazionale di Fisica Nucleare). The design and development of
custom VLIW processors, hardware and system software for those
machines accounted for more than 300 Person Years.
From that background, the development and validation of mAgic
VLIW DSP and the essential system software required
approximately 65 Person Years.
The integration and validation at Janus level with the ARM core and
the set of pre-validated ARM peripherals, plus physical design and
validation board activities should required approximately 10 Person
Years.
16. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 16
A Differentiation Era beyond the Single
Processor Barrier
Log(SystemComplexity)
Time
Massive Parallel Computers
SuperScalar
32 bit Float Multiplier
Resources available on a single chip
1980
Single Processor
Barrier
1990 2000 2010
Risc
Forced
Convergence
Era
Multi Core Differentiation
Era
Power density, overhead logic and interconnect delays for monolithic high clock
speed processor design are approaching embarrassing figures according to
ITRS. The human brain has got a processing power >> 106 times than DSP
processors of 2003, yet runs at <<100 Hz, ~10W. A precious Hint for adoption of
moderate clock speed, better memory architectures and parallelism
management to exploit higher silicon densities provided by DSM technologies?
17. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 17
Dimensional Analysis for Deep Sub-Micron
Processor design with ASIC methodology
A possible concern regarding synthesizable cores for next decade
SoCs:
maximum frequency dominated by wire delays, not by gate
propagation
our simple dimensional analysis suggests that:
– adequate ILP + multiple tiles, lower clock speed, lower pipelining,
shorter wire lengths simpler design closure
– floating point relatively un-expensive Balancing Memory area vs.
Operating area
– DSP treatment of wave phenomena useful ILP >= 15 native
complex domain support
18. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 18
Multiple Tile SoC: Tiles for Short Wires
External Memories Interface
RISCMem
DSP Prog
Mem
DSPData
mem
Reg File
VLIW
DSP
RISC
Y+ Communication Interface
Y- Communication Interface
X-Communication
X+Communication
RISCMem
DSP Prog
Mem
DSPData
mem
Reg File
VLIW
DSP
RISC
Y+ Communication Interface
Y- Communication Interface
X-Communication
X+Communication
Y- Communication Interface Y- Communication Interface
19. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 19
ILP * frequency vs. Wire Delay
r and c := technological resistance and capacitance per wire unit length (e.g.
180 nm rc = 58 ps/mm2, 90 nm rc = 160ps/mm2)
L := processor’s tile size; 2L:=worst Manhattan path length
g:= gate density (e.g. 180 nm g=55Kgate/mm2; 90 nm g=200Kgate/mm2)
o:= arithmetic operator cost (e.g. 7Kgate 24 bit floating point, 25Kgate 40 bit)
)4(
rco
g
66.ILP*wfwG
)3(2L
o
g
ILP
)2(
rc38.
1pt
2TLL2
)1(
2)L2(rc38.
1
RC38.
1
wf0f
≤=
≤
==
≤=≤ logic delay f0, wire delay fw. f0<< fw
indicates designs far away from
interconnect troubles
LT repeater insertion critical length ~
4.4mm ~ 419 ps on 180 nm
L2 areas support VLIW ILP determined by
gate density over operator cost
peak power for a VLIW area below critical
area (NOTE the interesting
independency on size and ILP)
20. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 20
Dimentional Hints
Equation (4) Gw =fw * ILP <= .66 g/rco, provides suggestions:
At one extreme, it states the obvious. You should divide a die
too large into N smaller tiles.
At intermediate scale, it suggests to insert at least the
number of operators that can be reached by non repeated
wires. In fact a lower frequency reduces the number of local
pipelines, permits the adoption of a classical ASIC RTL
methodology and simplifies the adoption of lower Vdd.
A lower bound for the ILP is imposed by:
– adequate program and data memory inside each tile
– maintain a higher granularity to avoid classical massive parallel processing
inefficiencies
– balance memory vs processing resources
21. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 21
mAgic VLIW Arith Oper Gate Count
#Units Combina
torial
Non
Comb.
Total Grand
Total
4 40 bit Float Adder 10900 8400 19300 77200
4 40 bit Float and 32 bit Int
Mult
24100 2700 26800 107200
4 32 bit Int Adder 900 1600 2500 10000
2 Float Div & Sqrt Seed 3300 700 4000 8000
2 40 bit Shift & Logic Unit 6600 800 7400 14800
2 Float<->Int Converter 4500 400 4900 9800
1 Decoder 1200 1700 2900 2900
Total VLIW Arithmetic
Operators
251300
SUPPORT FOR NATIVE COMPLEX DOMAIN 40-bit FLOATING
POINT ARITHMETIC <= 1.5 mm2 on 90 nm CMOS
22. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 22
mAgic VLIW Floating Point DSP Gate Count
Combinato
rial
Non
Comb.
Total
VLIW Arithmetic & Logic Operators 186800 64500 251300
VLIW Multiple Address Generation Unit 18900 13100 32000
VLIW Flow Controller 8300 18000 26300
VLIW DMA + Global Status Controller 4600 11300 15900
VLIW Program Decompression Engine 7600 10500 18100
VLIW Local Memory Mux Logic & Bist 18700 13800 32500
VLIW<->RISC Memory Mapping Interface 1300 6800 8100
VLIW DSP ENGINE TOTAL GATE COUNT 250400 141400 391800
payload for mAgic VLIW core >= 70% grows to 90% considering
processor + memory tiles
equations (3) and (4) are reasonable approximations
23. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 23
Dimensional Analysis results
On 180 nm Atmel technology, the gate delay for a 25 Kgate
40-bit floating point operator with two pipeline stages is 8 ns.
Therefore f0<< fw for the full VLIW core with ILP = 15.
Complete RISC+VLIW logic area ~ 10 mm2, 550 Kgates
On 90 nm copper CMOS, f0 / fw ~ 1 / 6for the 250 Kgate
complex domain data path with 10 floating point operators. A
pipeline stage will be required on core<->memory busses.
8 Gigaflops, 4 Janus tiles SOC feasible with ASIC
methodology on 90 nm technology with classical RTL
synchronous design. Insertion of repeaters and promotion of
global wires on thicker layers helps, but is not yet mandatory.
24. Hot Chips 15
August 2003Janus – A Gigaflops RISC+VLIW SoC TilePier S. PAOLUCCI 24
Summary
mAgic VLIW DSP: a synthesizable complex domain floating point
core: 1.0 Gigaflops @ 100 MHz, 180 nm CMOS
Janus: a 180 nm RISC+floating point VLIW platform for Gigaflops
SoC applications
A Dimensional Analysis based on the technological parameter g/rco
provides an interconnect bound to the processing power of simple
synthesizable RTL designs on DSM techologies with ASIC
methodology
We will follow a simple roadmap for SoC integration of multiple
gigaflops on 90 nm using:
– Tiles for Short Wires
– Appropriate VLIW parallelism
– Moderate Clock Speed
– This methodology keeps the cost down to a few tens of designers and M$.