This document summarizes a research paper that proposes a new asymmetrical multilevel inverter topology with a reduced number of switches. The topology uses four voltage sources with levels in a specific ratio to produce 15 output levels using only 8 switches and 4 diodes, reducing complexity compared to other topologies. The operation is simulated in MATLAB and validated through an FPGA-based hardware prototype. Simulation results show the output voltage waveform and a total harmonic distortion lower than conventional inverters.
Asymmetrical Nine-level Inverter Topology with Reduce Power Semicondutor DevicesTELKOMNIKA JOURNAL
In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is
capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging
available switches and dc sources in a fashion such that the maximum combination of addition and
subtraction of the input dc sources can be obtained. To verify the viability of the proposed topology, the
circuit model is developed and simulated in Matlab-Simulink software. Experimental testing results of the
proposed nine-level inverter topology, developed in the laboratory, are presented. A low frequency
switching strategy is employed in this work. The results show that the proposed topology is capable to
produce a nine-level output voltage, capable in handling inductive load and yields acceptable harmonic
distortion content.
Structure of 15-Level Sub-Module Cascaded H-Bridge Inverter for Speed Control...IJPEDS-IAES
This paper deals with the implementation of a single phase 15-level Sub- Multilevel Cascaded H-Bridge Inverter (SMCHBI) for variable speed industrial drive applications. It consists of sub-multilevel modules and H- bridge inverter configuration. Sub-multilevel switches synthesize stepped DC link voltage and current from the DC sources. H-bridge inverter switches renovate stepped DC link voltage and current into sinusoidal waveform. Compared with conventional Cascaded Multilevel Inverter (CMLI), the proposed system employs the reduced number of power switches, DC sources and gate driver requirements. The proposed system not only reduces the overall system cost but also reduces the voltage stress across the inverter switches. The proposed system does not required additional resonant soft switching circuits for Zero Voltage Switching (ZVS) of inverter. In the proposed method, variable frequency method is adopted for the speed control of industrial induction motor drives. A prototype model of 15-level SMCHB is developed and the performance of the systems is validated experimentally.
A Low Cost Single-Switch Bridgeless Boost PFC ConverterIJPEDS-IAES
This paper proposes the single-switch bridgeless boost power factor correction (PFC) converter to achieve high efficiency in low cost. The proposed converter utilizes only one active switching device forPFC operation as well as expecting higher efficiency than typical boost PFC converters. On the other hand, the implementation cost is less than traditional bridgeless boost PFC converters, in where two active switching deivces are necessary. The operational principle, the modeling, and the control scheme of the proposed converter arediscussed in detail. In order to verify the operation of the proposed converter, a 500W switching model is built in PSIM software package. The simulation results show that the proposed converter perfectly achieves PFC operation with only a single active switch.
A New Multilevel Inverter with Reduced Number of SwitchesIAES-IJPEDS
In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.
Asymmetrical Nine-level Inverter Topology with Reduce Power Semicondutor DevicesTELKOMNIKA JOURNAL
In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is
capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging
available switches and dc sources in a fashion such that the maximum combination of addition and
subtraction of the input dc sources can be obtained. To verify the viability of the proposed topology, the
circuit model is developed and simulated in Matlab-Simulink software. Experimental testing results of the
proposed nine-level inverter topology, developed in the laboratory, are presented. A low frequency
switching strategy is employed in this work. The results show that the proposed topology is capable to
produce a nine-level output voltage, capable in handling inductive load and yields acceptable harmonic
distortion content.
Structure of 15-Level Sub-Module Cascaded H-Bridge Inverter for Speed Control...IJPEDS-IAES
This paper deals with the implementation of a single phase 15-level Sub- Multilevel Cascaded H-Bridge Inverter (SMCHBI) for variable speed industrial drive applications. It consists of sub-multilevel modules and H- bridge inverter configuration. Sub-multilevel switches synthesize stepped DC link voltage and current from the DC sources. H-bridge inverter switches renovate stepped DC link voltage and current into sinusoidal waveform. Compared with conventional Cascaded Multilevel Inverter (CMLI), the proposed system employs the reduced number of power switches, DC sources and gate driver requirements. The proposed system not only reduces the overall system cost but also reduces the voltage stress across the inverter switches. The proposed system does not required additional resonant soft switching circuits for Zero Voltage Switching (ZVS) of inverter. In the proposed method, variable frequency method is adopted for the speed control of industrial induction motor drives. A prototype model of 15-level SMCHB is developed and the performance of the systems is validated experimentally.
A Low Cost Single-Switch Bridgeless Boost PFC ConverterIJPEDS-IAES
This paper proposes the single-switch bridgeless boost power factor correction (PFC) converter to achieve high efficiency in low cost. The proposed converter utilizes only one active switching device forPFC operation as well as expecting higher efficiency than typical boost PFC converters. On the other hand, the implementation cost is less than traditional bridgeless boost PFC converters, in where two active switching deivces are necessary. The operational principle, the modeling, and the control scheme of the proposed converter arediscussed in detail. In order to verify the operation of the proposed converter, a 500W switching model is built in PSIM software package. The simulation results show that the proposed converter perfectly achieves PFC operation with only a single active switch.
A New Multilevel Inverter with Reduced Number of SwitchesIAES-IJPEDS
In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.
Prof. Cuk invited talk at APEC 2011 plenary session to celebrate
35 years of his creation of this modeling and analysis method.
This talk was also recorded on video by IEEE.tv and can be viewed together. Here is a link to that video.
https://youtu.be/BLx57J2fF5w
Note: first few minutes of the video is Prof. Cuk's interview made after his presentation. This is thern followed by full 25 minutes presentation, which can be followed by the enclosed 67 slides.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Three Phase Single Stage Isolated Cuk based PFC ConverterAsoka Technologies
In this paper, analysis and design of a three phase isolated Cuk based power factor correction (PFC) converter has been proposed. The proposed converter is operated in discontinuous output inductor current mode (DOICM) to achieve PFC at ac input. This avoids the inner current control loop which further eliminates the sensing of current. This makes the system more reliable and robust. The converter requires only one simple voltage control loop for output voltage regulation and all the power switches are driven by the same gate signal which simplifies the gate driver circuit. The detailed operation of the converter and design calculations are presented. And also a small signal model of the converter by using CIECE approach is presented to aid the controller design. The experimental results from a 2-kW laboratory prototype with 208-V line-to-line input voltage, 400-V output voltage are presented to confirm the operation of the proposed converter. An input power factor of 0.999, an input current total harmonic distortion of as low as 4.06% and a high conversion efficiency of 95.1% are achieved from laboratory prototype.
Multilevel inverter offers many benefits for high power application compavered to conventional cascaded Multilevel Inverter topology.This paper presents Symmetric CMLI using variable frequency carrier based pulse width modulation techniques. The proposed topology reduces total harmonic distortion and reduced switching losses for seven level inverter. The simulation study of the proposed topology has been carried out in MATLAB/SIMULINK. The main objective of this paper is to achieve number of levels of MLI with reduced number of switches and DC power sources compared to conventional topology.
SIMULATION OF CASCADED H- BRIDGE MULTILEVEL INVERTER USING PD, POD, APOD TECH...ecij
Multilevel inverter (MLI) can achieve medium voltage high power efficiency inverters in industrial
application. It can generate stepped waveform by reducing harmonic distortion with increase in the
number of voltage level; a full bridge is known as H-bridge inverter because it shows alphabet ‘H’. In this
paper, Multicarrier PWM topologies and there Modulation schemes are discussed. Level Shifted [LS]
Scheme is applied to the Cascade H-bridge multilevel inverter and the complete analysis of THD to 9 levels
is done.
Review of Integrated Power Factor Correction (PFC) Boost converter topologies...IJARBEST JOURNAL
This paper provides a review of various Power Factor Correction (PFC) boost
converter topologies suitable for telecoms. A novel integrated PFC topology is proposed which acts
as a backup power supply for telecommunication systems. The advantage of the proposed circuit is
that it operates based on soft switching principle thereby reducing the switching losses in the
converter. The topologies analyzed in this paper are conventional average current mode control
boost PFC, bridgeless boost PFC, semi-bridgeless boost PFC, totem-pole bridgeless boost PFC and
proposed integrated boost PFC. All these topology studies are investigated by carrying out the
simulation of the converter circuits using PSIM software. A detailed comparison of all the
topologies have been done and they are compared in terms of supply power factor, supply current
THD and displacement factor. From the results, it is inferred that the proposed integrated PFC
provides a reduced supply current THD and improved power factor. The results are validated.
Cascaded h bridge multilevel inverter in a three phase eleven leveleSAT Journals
Abstract
This paper essentially concentrates on the design and implementation of a unique topology for a three phase eleven level
cascaded H-bridge multilevel cluverter by employing different kinds of switching schemes. The basic purpose of this paper is to
enhance the number of voltage level at the output without addition of any complexity to power circuit.
The main advantages of this proposed topology is to scale down the THD and reducing electromagnetic interface EMI generation
and high voltage with very close to sine waveform. In this paper, severel kinds of carrier pulse width modulation techniques are
proposed as which scale down the total harmonic distortion and improve the out voltage from the proposed topology and POD
modulation techniques reduce the THD. A number of H-bridge arranged in cascaded to increase the voltage level with the
different switching schemes analyzed in this paper. It is observed that this new topology can be recommended to three phase
eleven level cascaded H-bridge inverter for the best and optimum performance over the conventional methods. This performance
in optimized in the eleven level of inverter.
Improving the fundamental waveforms and reducing the total harmonic distortion by using 60 IGBTs and switching is arranged
by a topology in cascaded manners.
The simulation model is produced by MATLAB2009 software version.
Key Words: Cascaded H-bridge multilevel inverter, different phase pulse width modulation, total harmonic
distortionTHD, EMI
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
Improved performance with fractional order control for asymmetrical cascaded ...journalBEEI
This paper proposes a control scheme for seven level asymmetrical cascaded H-bridge multi level inverter (ACHBMLI) based on fractional order calculus. The seven level ACHBMLI consists of two H-bridges that are connected in series and are excited by different dc voltage sources. A simplified model is developed by assuming the small signal variation component is equal in both the H-bridges. A fractional order PID (FO-PID) controller is designed for the ACHBMLI using the simplified model. Simulation study shows the adequacy of FO-PID controller in giving an output voltage with minimum distortions. A conventional PID controller is also designed for ACHBMLI using the same simplified model. The performance of the ACHBMLI with FO-PID controller is compared with the performance of ACHBMLI with conventional PID controller. The simulation results prove the superiority of FO-PID controller in maintaining the output voltage of the ACHBMLI close to the reference voltage and in reducing the harmonic distortion of output voltage of the inverter. The simulation was done using MATLAB and the parameters of FO-PID controller was designed using FOMCON tool box.
IMPLEMENTATION OF DISCONTINUOUS INDUCTOR CURRENT MODE IN CUK CONVERTERS FED B...Journal For Research
This paper presents a bridgeless Cuk converter-fed brushless DC (BLDC) motor drive. A Bridgeless Cuk converter is constructed to operate at discontinuous inductor current mode to improve the quality of power and power factor at the AC mains for better speed control. The bridgeless converter is designed for obtaining the low conduction losses and requirement of low size of heat sink for the switches. TI-TMS320-F2812-based Digital Signal Processor (DSP) is used for the development of the hardware prototype of proposed BLDC motor drive.
New Two Simple Sinusoidal Generators with Four 45 Phase Shifted Voltage Outp...IJECEIAES
Two new 45 o phase shifted sinusoidal oscillator configurations employing single Second Generation Fully Differential Current Conveyor (FDCCII), two grounded capacitors and two grounded resistors are presented. The proposed oscillators can provide four sinusoidal voltage outputs with each a 45 o phase difference. These circuits can also be utilized as voltage-mode quadrature oscillators. Additional output stages incorporation in FDCCII can also result in current outputs spaced 45 degree apart. The proposed circuits enjoy the simplicity and less passive and active component. The Total Harmonic Distortion (THD) of the output waveforms was reasonability values (less than 4.5%). The circuits can supply two equi-quadrature outputs and the Lissajous patterns confirm the quadrature voltage output waveforms. The workability of the circuits is simulated by PSPICE 0.18 µm CMOS technology. The non-ideal analysis and simulation results verifying theoretical analyses are also investigated.
Comparison of PI and PID Controlled Bidirectional DC-DC Converter SystemsIJPEDS-IAES
This paper deals with comparison of responses of the PI and the PID
controlled bidirectional DC-DC converter systems. A coupled inductor is
used in the present work to produce high gain. Open loop and closed loop
controlled systems with PI and PID controllers are designed and simulated
using Matlab tool. The principles of operation and simulation case studies are
discussed in detail. The comparison is made in terms of rise time, fall time,
peak overshoot and steady state error.
Now day’s the power factor has become a major problem in power system to improve the power quality of the grid, as power factor is affected on the grid due to the nonlinear loads connected to it. Single phase bridgeless AC/DC power factor correction (PFC) topology to improve the power factor as well as the total harmonic distortion (THD) of the utility grid is proposed. By removing the input bridge in conventional PFC converters, the control circuit is simplified; the total harmonics distortion (THD) and power factor (PF) are improved. The PI controller operates in two loops one is the outer control loop which calculates the reference current through LC filter and signal processing. Inner current loop generates PWM switching signals through the PI controller. The output of the proposed PFC topology is verified for prototype using MATLAB circuit simulations. The experimental system is developed, and the simulation results are obtained.
AN ACTIVE PFC WITH FLYBACK DESIGN FOR INTELLIGENCE IN STREET LIGHT APPLICATIONJournal For Research
As the requirement of energy demand is increasing due to rapid industrial development, it is necessary to meet the growing demand of energy. This can be achieved in two ways: find alternate resource to supply power or energy; or reduce the energy consumption of present resources available. The proposed work is basically the design and implementation of an intelligent street light of 50 W power output from the offline converter by using power LED. As power LED draws huge non sinusoidal current due to the presence of AC-DC converter, a Boost PFC and a fly back converter is used for better power factor and for dc voltage regulation. Along with this a PIR sensor and LDR sensors are also used. A PIC microcontroller is used for PWM dimming. This makes to reduce the power consumption in street light especially in urban cities in which most of the power is wasted in lighting streets during late night.
This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.
A New Multilevel Inverter Structure For High-Power Applications using Multi-c...IJPEDS-IAES
In recent, several numbers of multilevel inverter structures have been
introduced that the numbers of circuit devices have been reduced. This paper
introduces a new structure for multilevel inverter which can be used in highpower
applications. The proposed topology is based on cascaded connection
of basic units. This topology consists of minimum number of circuit
components such as IGBT, gate driver circuit and antiparallel diode. For
proposed topology, two methods are presented for determination of dc
voltage sources values. Multi-carrier PWM method for 25-level proposed
topology is used. Verification of the analytical results is done using
MATLAB simulation.
This paper presents a new topology for cascaded H-bridge multilevel inverter utilizing multicarrier modulation technique. The new five-level topology utilizes a capacitive divider network consisting of two capacitors for producing output voltage levels. The developed circuit has reduced number of switches and dc sources compared to conventional five level inverters. Five main power switches, a single additional diode apart from antiparallel diodes, two capacitors and a dc supply constitute a single five level unit. Simulations as well as experimental results are verified for the new topology utilising multicarrier modulation technique with reduced harmonic distortions in the output.
Prof. Cuk invited talk at APEC 2011 plenary session to celebrate
35 years of his creation of this modeling and analysis method.
This talk was also recorded on video by IEEE.tv and can be viewed together. Here is a link to that video.
https://youtu.be/BLx57J2fF5w
Note: first few minutes of the video is Prof. Cuk's interview made after his presentation. This is thern followed by full 25 minutes presentation, which can be followed by the enclosed 67 slides.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Three Phase Single Stage Isolated Cuk based PFC ConverterAsoka Technologies
In this paper, analysis and design of a three phase isolated Cuk based power factor correction (PFC) converter has been proposed. The proposed converter is operated in discontinuous output inductor current mode (DOICM) to achieve PFC at ac input. This avoids the inner current control loop which further eliminates the sensing of current. This makes the system more reliable and robust. The converter requires only one simple voltage control loop for output voltage regulation and all the power switches are driven by the same gate signal which simplifies the gate driver circuit. The detailed operation of the converter and design calculations are presented. And also a small signal model of the converter by using CIECE approach is presented to aid the controller design. The experimental results from a 2-kW laboratory prototype with 208-V line-to-line input voltage, 400-V output voltage are presented to confirm the operation of the proposed converter. An input power factor of 0.999, an input current total harmonic distortion of as low as 4.06% and a high conversion efficiency of 95.1% are achieved from laboratory prototype.
Multilevel inverter offers many benefits for high power application compavered to conventional cascaded Multilevel Inverter topology.This paper presents Symmetric CMLI using variable frequency carrier based pulse width modulation techniques. The proposed topology reduces total harmonic distortion and reduced switching losses for seven level inverter. The simulation study of the proposed topology has been carried out in MATLAB/SIMULINK. The main objective of this paper is to achieve number of levels of MLI with reduced number of switches and DC power sources compared to conventional topology.
SIMULATION OF CASCADED H- BRIDGE MULTILEVEL INVERTER USING PD, POD, APOD TECH...ecij
Multilevel inverter (MLI) can achieve medium voltage high power efficiency inverters in industrial
application. It can generate stepped waveform by reducing harmonic distortion with increase in the
number of voltage level; a full bridge is known as H-bridge inverter because it shows alphabet ‘H’. In this
paper, Multicarrier PWM topologies and there Modulation schemes are discussed. Level Shifted [LS]
Scheme is applied to the Cascade H-bridge multilevel inverter and the complete analysis of THD to 9 levels
is done.
Review of Integrated Power Factor Correction (PFC) Boost converter topologies...IJARBEST JOURNAL
This paper provides a review of various Power Factor Correction (PFC) boost
converter topologies suitable for telecoms. A novel integrated PFC topology is proposed which acts
as a backup power supply for telecommunication systems. The advantage of the proposed circuit is
that it operates based on soft switching principle thereby reducing the switching losses in the
converter. The topologies analyzed in this paper are conventional average current mode control
boost PFC, bridgeless boost PFC, semi-bridgeless boost PFC, totem-pole bridgeless boost PFC and
proposed integrated boost PFC. All these topology studies are investigated by carrying out the
simulation of the converter circuits using PSIM software. A detailed comparison of all the
topologies have been done and they are compared in terms of supply power factor, supply current
THD and displacement factor. From the results, it is inferred that the proposed integrated PFC
provides a reduced supply current THD and improved power factor. The results are validated.
Cascaded h bridge multilevel inverter in a three phase eleven leveleSAT Journals
Abstract
This paper essentially concentrates on the design and implementation of a unique topology for a three phase eleven level
cascaded H-bridge multilevel cluverter by employing different kinds of switching schemes. The basic purpose of this paper is to
enhance the number of voltage level at the output without addition of any complexity to power circuit.
The main advantages of this proposed topology is to scale down the THD and reducing electromagnetic interface EMI generation
and high voltage with very close to sine waveform. In this paper, severel kinds of carrier pulse width modulation techniques are
proposed as which scale down the total harmonic distortion and improve the out voltage from the proposed topology and POD
modulation techniques reduce the THD. A number of H-bridge arranged in cascaded to increase the voltage level with the
different switching schemes analyzed in this paper. It is observed that this new topology can be recommended to three phase
eleven level cascaded H-bridge inverter for the best and optimum performance over the conventional methods. This performance
in optimized in the eleven level of inverter.
Improving the fundamental waveforms and reducing the total harmonic distortion by using 60 IGBTs and switching is arranged
by a topology in cascaded manners.
The simulation model is produced by MATLAB2009 software version.
Key Words: Cascaded H-bridge multilevel inverter, different phase pulse width modulation, total harmonic
distortionTHD, EMI
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
Improved performance with fractional order control for asymmetrical cascaded ...journalBEEI
This paper proposes a control scheme for seven level asymmetrical cascaded H-bridge multi level inverter (ACHBMLI) based on fractional order calculus. The seven level ACHBMLI consists of two H-bridges that are connected in series and are excited by different dc voltage sources. A simplified model is developed by assuming the small signal variation component is equal in both the H-bridges. A fractional order PID (FO-PID) controller is designed for the ACHBMLI using the simplified model. Simulation study shows the adequacy of FO-PID controller in giving an output voltage with minimum distortions. A conventional PID controller is also designed for ACHBMLI using the same simplified model. The performance of the ACHBMLI with FO-PID controller is compared with the performance of ACHBMLI with conventional PID controller. The simulation results prove the superiority of FO-PID controller in maintaining the output voltage of the ACHBMLI close to the reference voltage and in reducing the harmonic distortion of output voltage of the inverter. The simulation was done using MATLAB and the parameters of FO-PID controller was designed using FOMCON tool box.
IMPLEMENTATION OF DISCONTINUOUS INDUCTOR CURRENT MODE IN CUK CONVERTERS FED B...Journal For Research
This paper presents a bridgeless Cuk converter-fed brushless DC (BLDC) motor drive. A Bridgeless Cuk converter is constructed to operate at discontinuous inductor current mode to improve the quality of power and power factor at the AC mains for better speed control. The bridgeless converter is designed for obtaining the low conduction losses and requirement of low size of heat sink for the switches. TI-TMS320-F2812-based Digital Signal Processor (DSP) is used for the development of the hardware prototype of proposed BLDC motor drive.
New Two Simple Sinusoidal Generators with Four 45 Phase Shifted Voltage Outp...IJECEIAES
Two new 45 o phase shifted sinusoidal oscillator configurations employing single Second Generation Fully Differential Current Conveyor (FDCCII), two grounded capacitors and two grounded resistors are presented. The proposed oscillators can provide four sinusoidal voltage outputs with each a 45 o phase difference. These circuits can also be utilized as voltage-mode quadrature oscillators. Additional output stages incorporation in FDCCII can also result in current outputs spaced 45 degree apart. The proposed circuits enjoy the simplicity and less passive and active component. The Total Harmonic Distortion (THD) of the output waveforms was reasonability values (less than 4.5%). The circuits can supply two equi-quadrature outputs and the Lissajous patterns confirm the quadrature voltage output waveforms. The workability of the circuits is simulated by PSPICE 0.18 µm CMOS technology. The non-ideal analysis and simulation results verifying theoretical analyses are also investigated.
Comparison of PI and PID Controlled Bidirectional DC-DC Converter SystemsIJPEDS-IAES
This paper deals with comparison of responses of the PI and the PID
controlled bidirectional DC-DC converter systems. A coupled inductor is
used in the present work to produce high gain. Open loop and closed loop
controlled systems with PI and PID controllers are designed and simulated
using Matlab tool. The principles of operation and simulation case studies are
discussed in detail. The comparison is made in terms of rise time, fall time,
peak overshoot and steady state error.
Now day’s the power factor has become a major problem in power system to improve the power quality of the grid, as power factor is affected on the grid due to the nonlinear loads connected to it. Single phase bridgeless AC/DC power factor correction (PFC) topology to improve the power factor as well as the total harmonic distortion (THD) of the utility grid is proposed. By removing the input bridge in conventional PFC converters, the control circuit is simplified; the total harmonics distortion (THD) and power factor (PF) are improved. The PI controller operates in two loops one is the outer control loop which calculates the reference current through LC filter and signal processing. Inner current loop generates PWM switching signals through the PI controller. The output of the proposed PFC topology is verified for prototype using MATLAB circuit simulations. The experimental system is developed, and the simulation results are obtained.
AN ACTIVE PFC WITH FLYBACK DESIGN FOR INTELLIGENCE IN STREET LIGHT APPLICATIONJournal For Research
As the requirement of energy demand is increasing due to rapid industrial development, it is necessary to meet the growing demand of energy. This can be achieved in two ways: find alternate resource to supply power or energy; or reduce the energy consumption of present resources available. The proposed work is basically the design and implementation of an intelligent street light of 50 W power output from the offline converter by using power LED. As power LED draws huge non sinusoidal current due to the presence of AC-DC converter, a Boost PFC and a fly back converter is used for better power factor and for dc voltage regulation. Along with this a PIR sensor and LDR sensors are also used. A PIC microcontroller is used for PWM dimming. This makes to reduce the power consumption in street light especially in urban cities in which most of the power is wasted in lighting streets during late night.
This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.
A New Multilevel Inverter Structure For High-Power Applications using Multi-c...IJPEDS-IAES
In recent, several numbers of multilevel inverter structures have been
introduced that the numbers of circuit devices have been reduced. This paper
introduces a new structure for multilevel inverter which can be used in highpower
applications. The proposed topology is based on cascaded connection
of basic units. This topology consists of minimum number of circuit
components such as IGBT, gate driver circuit and antiparallel diode. For
proposed topology, two methods are presented for determination of dc
voltage sources values. Multi-carrier PWM method for 25-level proposed
topology is used. Verification of the analytical results is done using
MATLAB simulation.
This paper presents a new topology for cascaded H-bridge multilevel inverter utilizing multicarrier modulation technique. The new five-level topology utilizes a capacitive divider network consisting of two capacitors for producing output voltage levels. The developed circuit has reduced number of switches and dc sources compared to conventional five level inverters. Five main power switches, a single additional diode apart from antiparallel diodes, two capacitors and a dc supply constitute a single five level unit. Simulations as well as experimental results are verified for the new topology utilising multicarrier modulation technique with reduced harmonic distortions in the output.
A Novel Topology of Multilevel Inverter with Reduced Number of Switches and D...IAES-IJPEDS
This paper introduces new topology of cascaded multilevel inverter, with considerable reduction in the number of switches and DC voltage sources. The proposed topology is based on asymmetrical multilevel inverter which produces 21 levels of output with the use of 11 unidirectional switches, 3 diodes and 4 DC voltage sources. The advantages of this topology are reduction in the number of switches (2 nos.) and gate driver circuits (2 nos.), reduction in the number of DC sources (2 nos.) also cost, complexity, and space required for hardware is reduced without sacrificing the quality output of the inverter. To reduce the THD further Level shifting SPWM techniques such as PD, POD & APOD are used and comparison is shown on the basis of THDs obtained from the above SPWM techniques. Frequency of carrier waves is 1KHz, and modulation index is 1.0. To validate the proposed topology the circuit is simulated and verified by using MATLAB/Simulink.
Implementation of Three phase SPWM Inverter with Minimum Number of Power Elec...IJMTST Journal
In the past decades, the researchers have dealt with the conventional topology, which possesses sum switches of Multilevel Inverter is applied to PWM method. The present research work has been introduced a new method of multilevel inverter using reduced switches is applied with PWM technique. In introduction part the conventional new multilevel inverter & switching pattern are explained. In second part PWM technique of proposed work and circuits is explained. The width of this pulses are modulated in order to obtain inverter output voltage control and to reduce its harmonic content. Sinusoidal pulse width modulation or SPWM is the most common method in motor control and inverter application. Conventionally, to generate the signal, triangle wave as a carrier signal is compared with the sinusoidal wave, whose frequency is the desired frequency.
Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter. This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/SIMULINK. Experimental results are presented to validate the effectiveness of the operation of the diode clamped multilevel inverter using field programmable gate array.
Multilevel converters have a significant role in power processing control in the power system, which has some inherent features like reduced harmonics, high power & medium voltage, reduced voltage stress. In this proposed paper, a novel multilevel inverter with reduced number of switches and without passive components. The proposed inverter generates 15 level output voltage with suitable switching pulse generation using multicarrier sinusoidal pulse width modulation (MSPWM) and different level of voltages are obtained with variation of modulation index. Also coupled inductor is used to minimize the harmonic content and smoothing output current. The scheme which includes different range of unequal voltage sources. As a result, the proposed system it reduces switching control complexity and there is no voltage balancing problem. This paper elucidates the operating modes, voltage stress minimisation and harmonic reduction are discussed. The results of the proposed multilevel dc-ac converter are verified using matlab/simulink. The simulation & hardware results of the proposed inverter were verified using matlab simulink and dsPIC controller respectively, which was analysed with different voltage level and different modulation index.
Cascaded H-Bridge Multilevel Inverter Using SPWM and MSPWM StrategiesIJERA Editor
Nowadays, the multilevel inverter is growing hugely in medium voltage-high power applications. It produces staircase output voltage near sinusoidal waveform. The multilevel inverter is as compared to a two level inverter has high output voltage at high switching frequency , less EMI (electro-magnetic interference), lower THD (total harmonics distortion), low voltage stress (dv/dt) and it reduces the size of the filter components. In this paper various techniques cascaded H-bridges inverter are designed and implemented. Single phase sinusoidal pulse width modulation (SPWM) and modified sinusoidal pulse width modulation (MSPWM) topologies of (three, five and seven) levels inverters are designed and implemented. The results in percentage value of THD before and after filter are compared. The simulink/matlab and proteus are used to simulate the systems and finally, result are obtained experimentally using microcontroller (arduino mega 2560). When the number of levels is increased using SPWM technique the THD reduced, THD improves in MSPWM technique too, and comparison table II illustrated that.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Swit...Scientific Review
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through simulation and the simulation results are compared with the conventional multilevel inverter. From the result the proposed inverter offers much less total harmonic distortion.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Sw...Scientific Review SR
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through
simulation and the simulation results are compared with the conventional multilevel inverter. From the result the
proposed inverter offers much less total harmonic distortion
Use of multilevel inverters have been widely accepted as an effective solution for high power and high voltage applications. The performance of a multilevel inverter is superior to that of traditional inverters due to their advantages such as, reduced THD, less switching stress, lower EMI. Different types of topologies and modulation techniques for multilevel inverters have been discussed in the recent literature. In this paper three phase multilevel inverter based on Diode Clamped Multilevel DC Link (DC-MLDCL) and full bridge inverter has been proposed to reduce switch count and THD using multi reference based modulation techniques. The proposed multi reference modulation techniques are based on sinusoidal and third harmonic reference wave compared with U-type carrier wave. The performance parameters for the proposed DC-MLDCL inverter are analyzed in terms of THD, fundamental output line voltage and output line current for R and RL loads. The results are verified through MATLAB/simulation tool to verify the results of the proposed three phase seven level DC-MLDCL inverter .
Analysis of Multilevel Inverter using Bipolar and Unipolar Switching Schemes ...ijsrd.com
Cascaded H-bridge Multilevel Inverter (MLI) is most efficient topology for medium and high voltage DC-AC conversion, having less output harmonics and less commutation losses. Disadvantages are their complexity, more number of power devices, passive components and a complex control circuitry. Here a Cascaded Hybrid Multilevel Inverter is used to produce a three phase 9-level output voltages. Now a day inverter is also know as a DC-AC converter, is one of the most popular part of electrical device. This proposed inverter widely used in industries application such as speed control of induction motor. This thesis focus on three phase 9-level bipolar and unipolar switching inverter with characteristics like output voltage boosting ability and also we discus about the bipolar and unipolar switching scheme along with capacitor voltage control. The modified topology uses Cascaded H-bridge (CHB) with bidirectional and unidirectional switches producing boost up output voltage. Here a hybrid Pulse Width Modulation (PWM) technique is applied to control the power devices. This modulation technique uses a sine wave and a repeating wave, these waves are combined and a complete reference wave is generated. There is comparative study between CHB and modified topology between number of power devices used and Total Harmonic Distortions (THD). THD of modified topology is reduced and analyzed by FFT window. The results are observed by MATLAB/SIMULINK software.
Design of 15 level reduced switches inverter topology using multicarrier sinu...TELKOMNIKA JOURNAL
In this proposed paper, multicarrier sinusoidal pulse width modulation (M-SPWM) method is implemented for design of 15 level reduced switches inverter topology. This inverter topology generates 15 level output-voltage with suitablelswitching pulse production using M-SPWM and altered level of voltages are attained with distinction of modulationlindex. The split inductor is used to diminish the harmoniclcontent and flatted output current. This type of system which contains different range of different range of voltage supplies. As a result, this inverter reduces the difficulty in gating time calculation and there is no neutral point fluctuation issue. This paper illuminates the modes of switching and minimization of stress in voltage and harmonic diminution are examined. The grades of the projected multilevel inverter (MLI) system are verified using Matlab/Simulink and dsPIC controller respectively.
One of the preferred choices of electronic power conversion for high power applications are multilevel inverters topologies finding increased attention in industry. Cascaded H-Bridge multilevel inverter is one of these topologies reaching the higher output voltage, power level and higher reliability due to its modular topology. Level Shifted Carrier Pulse Width Modulation (LSCPWM) and Phase Shifted Carrier Pulse Width Modulation are used generally for switching cascaded H-bridge (CHB) multilevel inverters. This paper compares LSCPWM and PSCPWM in terms of total harmonics distortion (THD) and output voltage among inverter cells. Simulation for 21-level CHB inverter is carried out in MATLAB/SIMULINK and simulation results are presented.
A Single-Phase Multilevel Current-Source Converter using H-Bridge and DC Curr...IJPEDS-IAES
This paper presents a different topology of H-bridge based multilevel current-source inverter (CSI). In this new inverter configuration, an H-bridge CSI is connected with a single or more current modules to generate a multilevel output current waveform with lower di/dt, and less distortion. Using the proposed multilevel CSI, the number of the power switching devices, and isolated gate drive circuits can be reduced. Moreover, chopper based DC current sources are presented to reduce the inductor size effectively to be in micro-Henry order, and to ensure the balance of the intermediate current levels. The proposed topology is inherently able to reduce the inductor conduction losses if compared with the conventional multilevel CSIs and the H-bridge CSI. Seven-level PWM inverter configurations with non-isolated DC current sources and with a single DC power source are verified through computer simulations. Furthermore, laboratory prototypes of seven-level CSI is setup and tested. The results show that the inverter circuit works properly to generate the multilevel output current waveform with low harmonics currents, small inductors and with less conduction losses which proves feasibility of the proposed multilevel CSI.
Asymmetrical Cascaded Multi Level Inverter using Control Freedom Pulse width ...IAES-IJPEDS
In this paper, the suggested topologies are gained by cascading a full bridge inverter with dissimilar DC sources. This topology has several new patterns adopting the fixed switching frequency, multicarrier control freedom degree with mixture conceptions are established and simulated for the preferred three-phase cascaded multilevel inverter. In outstanding switching arrangement terminations, there are convinced degrees of freedom to produce the nine level AC output voltages with terminated switching positions for producing altered output voltages. These investigations focus on asymmetrical cascaded multilevel inverter engaging with carrier overlapping pulse width modulation (PWM) topologies. These topologies offer less amount of harmonics present in the output voltage and superior root mean square (RMS) values of the output voltages associated with the traditional sinusoidal pulse width modulation. This research studies carries with it MATLAB/SIMULINK based simulation and experimental results obtained using appropriated prototype to prove the validity of the proposed concept.
This paper introduces a new topology of multilevel inverter, which is able to operate at high performance. This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level inverters need at least twelve switches. The proposed topology has only ten switches. The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms. The detailed operation of the proposed inverter is explained. The theoretical analysis and design procedure are given. Simulation results are presented to confirm the analytical approach of the proposed circuit. A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz.
Similar to FPGA Based Design and Validation of Asymmetrical Reduced Switch Multilevel Inverter (20)
Inter-Area Oscillation Damping using an STATCOM Based Hybrid Shunt Compensati...IJPEDS-IAES
FACTS devices are one of the latest technologies which have been used to
improve power system dynamic and stability during recent years. However,
widespread adoption of this technology has been hampered by high cost
and reliability concerns. In this paper an economical phase imbalanced shunt
reactive compensation concept has been introduced and its ability for power
system dynamic enhancement and inter-area oscillation damping are
investigated. A hybrid phase imbalanced scheme is a shunt capacitive
compensation scheme, where two phases are compensated by fixed shunt
capacitor (C) and the third phase is compensated by a Static Synchronous
Compensator (STATCOM) in shunt with a fixed capacitor (CC). The power
system dynamic stability enhancement would be achieved by adding
a conventional Wide Area Damping Controller (WADC) to the main control
loop of the single phase STATCOM. Two different control methodologies
are proposed: a non-optimized conventional damping controller
and a conventional damping controller with optomised parameters that are
added to the main control loop of the unbalanced compensator in order to
damp the inter area oscillations. The proposed arrangement would, certainly,
be economically attractive when compared with a full three-phase
STATCOM. The proposed scheme is prosperously applied in a 13-bus
six-machine test system and various case studies are conducted to
demonstrate its ability in damping inter-area oscillations and power system
dynamic enhancement.
Fuzzy Gain-Scheduling Proportional–Integral Control for Improving the Speed B...IJPEDS-IAES
In this article, we have set up a vector control law of induction machine
where we tried different type of speed controllers. Our control strategy is of
type Field Orientated Control (FOC). In this structure we designed a Fuzzy
Gain-Scheduling Proportional–Integral (Pi) controller to obtain best result
regarding the speed of induction machine. At the beginning we designed a Pi
controller with fixed parameters. We came up to these parameters by
identifying the transfer function of this controller to that of Broïda (second
order transfer function). Then we designed a fuzzy logic (FL) controller.
Based on simulation results, we highlight the performances of each
controller. To improve the speed behaviour of the induction machine, we
have designend a controller called “Fuzzy Gain-Scheduling Proportional–
Integral controller” (FGS-PI controller) which inherited the pros of the
aforementioned controllers. The simulation result of this controller will
strengthen its performances.
Advance Technology in Application of Four Leg Inverters to UPQCIJPEDS-IAES
This article presents a novel application of four leg inverter with
conventional Sinusoidal Pulse Width Modulation (SPWM) Scheme to
Unified Power Quality Conditioner (UPQC). The Power Quality problem
became burning issues since the starting of high voltage AC transmission
system. Hence, in this article it has been discussed to mitigate the PQ issues
in high voltage AC systems through a three phase Unified Power Quality
Conditioner (UPQC) under various conditions, such as harmonic mitigation
scheme, non linear loads, sag and swell conditions as well. Also, it proposes
to control harmoincs with various artificial intelligent techniques. Thus
application of these control technique such as Neural Networks (ANN)
Fuzzy Logic makes the system performance in par with the standards
and also compared with existing system. The simulation results based on
MATLAB/Simulink are discussed in detail to support the concept developed
in the paper.
Modified SVPWM Algorithm for 3-Level Inverter Fed DTC Induction Motor DriveIJPEDS-IAES
In this paper, a modified space vector pulse width modulation (MSVPWM)
algorithm is developed for 3-level inverter fed direct torque controlled
induction motor drive (DTC-IMD). MSVPWM algorithm simplifies
conventional space vector pulse width modulation (CSVPWM) algorithm for
multilevel inverter (MLI), whose complexity lies in sector/subsector/subsubsector
identification; which will commensurate with number of levels. In
the proposed algorithm sectors are identified as in two level inverter
and subsectors/sub-subsectors are identified by shifting the original reference
vector to sector 1 (S1). This is valid due to the fact that a three level space
vector plane is a composition of six two level space planes, and are
symmetrical with reference to six pivot states. Switching state/sequence
selection is also very important while dealing with SVPWM strategy for
MLI. In the proposed algorithm out of 27 available switching states apt
switching state is selected based on sector and subsector number, such that
voltage ripple is considerably less. To validate the proposed algorithm, it is
tested on a three level neutral point clamped (NPC) inverter fed DTC-IMD.
The performance of the MSVPWM algorithm is analyzed by comparing no
load stator current ripple of the three level DTC-IMD with two level
DTC-IMD. Significant reduction in steady state torque and flux ripple is
observed. Hence, reduced acoustic noise is a distinctive facet of the proposed
method.
Modelling of a 3-Phase Induction Motor under Open-Phase Fault Using Matlab/Si...IJPEDS-IAES
The d-q model of Induction Motors (IMs) has been effectively used as an
efficient method to analyze the performance of the induction machines. This
study presents a step by step Matlab/Simulink implementation
of a star-connected 3-phase IM under open-phase fault (faulty 3-phase IM)
using d-q model. The presented technique in this paper can be simply
implemented in one block and can be made available for control purposes.
The simulated results provide to show the behavior of the star-connected 3-phase IM under open-phase fault condition.
Performance Characteristics of Induction Motor with FielIJPEDS-IAES
With development of power electronics and control Theories, the AC motor
control becomes easier. So the AC motors are used instead of the DC motor
in the drive applications. With this development, a several methods of control
are invented. The field oriented control and direct torque control are from the
best methods to control the drive systems. This paper is compared between
the field oriented control and direct torque control to show the advantages
and disadvantages of these methods of controls. This study discussed the
effects of these methods of control on the total harmonic distortion of the
current and torque ripples. This occurs through study the performance
characteristics of the AC motor. The motor used in this study is an induction
motor. This study is simulated through the MATLAB program.
A Novel Modified Turn-on Angle Control Scheme for Torque- Ripple Reduction in...IJPEDS-IAES
In recent years, Switched Reluctance Motors (SRM) have been dramatically
considered with both researchers and industries. SRMs not only have a
simple and reliable structure, but also have low cost production process.
However, discrete torque production of SRM along with intensive magnetic
saturation in stator and rotor cores are the major drawbacks of utilizing in
variety of industrial applications and also causes the inappropriate torque
ripples. In this paper, a modified logical-rule-based Torque Sharing Function
(TSF) method is proposed considering turn-on angle control. The optimized
turn-on angle for conducting each phase is achieved by estimating the
inductance curve in the vicinity of unaligned position and based on an
analytical solution for each phase voltage equation. Simulation results on a
four-phase switched reluctance motor and comparison with the conventional
methods validates the effectiveness of the proposed method.
Modeling and Simulation of Induction Motor based on Finite Element AnalysisIJPEDS-IAES
This paper presents the development of a co-simulation platform of induction
motor (IM). For the simulation, a coupled model is introduced which
contains the control, the power electronics and also the induction machine.
Each of these components is simulated in different software environments.
So, this study provides an advanced modeling and simulation tools for IM
which integrate all the components into one common simulation platform
environment. In this work, the IM is created using Ansys-Maxwell based on
Finite Element Analysis (FEA), whereas the power electronic converter is
developed in Ansys-Simplorer and the control scheme is build in MATLABSimulink
environment. Such structure can be useful for accurate design
and allows coupling analysis for more realistic simulation. This platform is
exploited to analyze the system models with faults caused by failures of
different drive’s components. Here, two studies cases are presented: the first
is the effects of a faulty device of the PWM inverter, and the second case is
the influence of the short circuit of two stator phases. In order to study the
performance of the control drive of the IM under fault conditions,
a co-simulation of the global dynamic model has been proposed to analyze
the IM behavior and control drives. In this work, the co-simulation has been
performed; furthermore the simulation results of scalar control allowed
verifying the precision of the proposed FEM platform.
Comparative Performance Study for Closed Loop Operation of an Adjustable Spee...IJPEDS-IAES
In this paper an extensive comparative study is carried out between PI
and PID controlled closed loop model of an adjustable speed Permanent
Magnet Synchronous Motor (PMSM) drive. The incorporation of Sinusoidal
Pulse Width Modulation (SPWM) strategy establishes near sinusoidal
armature phase currents and comparatively less torque ripples without
sacrificing torque/weight ratio. In this closed loop model of PMSM drive, the
information about reference speed is provided to a speed controller, to ensure
that actual drive speed tracks the reference speed with ideally zero steady
state speed error. The entire model of PMSM closed loop drive is divided
into two loops, inner loop current and outer loop speed. By taking the
different combinations of two classical controllers (PI & PID) related with
two loop control structure, different approximations are carried out. Hence a
typical comparative study is introduced to familiar with the different
performance indices of the system corresponding to time domain and
frequency domain specifications. Therefore overall performance of closed
loop PMSM drive is tested and effectiveness of controllers will be
determined for different combinations.
Novel Discrete Components Based Speed Controller for Induction MotorIJPEDS-IAES
This paper presents an electronic design based on general purpose discrete
components for speed control of a single phase induction motor drive. The
MOSFETs inverter switching is controlled using Sampled Sinusoidal Pulse
Width Modulation (SPWM) techniques with V/F method based on Voltage
Controlled Oscillator (VCO). The load power is also controlled by a novel
design to produce a suitable SPWM pulse. The proposed electronic system
has ability to control the output frequency with flexible setting of lower limit
to less than 1 Hz and to higher frequency limits to 55 Hz. Moreover, the
proposed controller able to control the value of load voltage to frequency
ratio, which plays a major parameter in the function of IM speed control.
Furthermore, the designed system is characterized by easy manufacturing
and maintenance, high speed response, low cost, and does not need to
program steps as compared to other systems based on Microcontroller
and digital signal processor (DSP) units. The complete proposed electronic
design is made by the software of NI Multisim version 11.0 and all the
internal sub-designs are shown in this paper. Simulation results show the
effectiveness of electronic design for a promising of a high performance IM
PWM drive.
Sensorless Control of a Fault Tolerant PMSM Drives in Case of Single-Phase Op...IJPEDS-IAES
This paper introduces a sensorless-speed-controlled PMSM motor fed by a
four-leg inverter in case of a single phase open circuit fault regardless in
which phase is the fault. To minimize the system performance degradation
due to a single phase open circuit fault, a fault tolerant control strategy that
includes taking appropriate actions to control the two remaining healthy
currents is used in addition to use the fourth leg of the inverter. Tracking the
saliency is done through measuring the dynamic current responses of the
healthy phases of the PMSM motor due the IGBT switching actions using the
fundamental PWM method without introducing any modification to the
operation of the fourth leg of the inverter. Simulation results are provided to
verify the effectiveness of the proposed strategy for sensorless controlling of
a PMSM motor driven by a fault-tolerant four-phase inverter over a wide
speed ranges under the case of a single phase open circuit.
Improved Stator Flux Estimation for Direct Torque Control of Induction Motor ...IJPEDS-IAES
Stator flux estimation using voltage model is basically the integration of the
induced stator back electromotive force (emf) signal. In practical
implementation the pure integration is replaced by a low pass filter to avoid
the DC drift and saturation problems at the integrator output because of the
initial condition error and the inevitable DC components in the back emf
signal. However, the low pass filter introduces errors in the estimated stator
flux which are significant at frequencies near or lower than the cutoff
frequency. Also the DC components in the back emf signal are amplified at
the low pass filter output by a factor equals to . Therefore, different
integration algorithms have been proposed to improve the stator flux
estimation at steady state and transient conditions. In this paper a new
algorithm for stator flux estimation is proposed for direct torque control
(DTC) of induction motor drives. The proposed algorithm is composed of a
second order high pass filter and an integrator which can effectively
eliminates the effect of the error initial condition and the DC components.
The amplitude and phase errors compensation algorithm is selected such that
the steady state frequency response amplitude and phase angle are equivalent
to that of the pure integrator and the multiplication and division by stator
frequency are avoided. Also the cutoff frequency selection is improved; even
small value can filter out the DC components in the back emf signal. The
simulation results show the improved performance of the induction motor
direct torque control drive with the proposed stator flux estimation algorithm.
The simulation results are verified by the experimental results.
Minimization of Starting Energy Loss of Three Phase Induction Motors Based on...IJPEDS-IAES
The purpose of this paper is to minimize energy losses consumed by three
phase induction motors during starting with wide range of load torque from
no load to full load. This will limit the temperature rise and allows for more
numbers of starting during a definite time. Starting energy losses
minimization is achieved by controlling the rate of increasing voltage
and frequency to start induction motor under certain load torque within a
definite starting time. Optimal voltage and frequency are obtained by particle
swarm optimization (PSO) tool according to load torque. Then, outputs of the
PSO are used to design a neuro-fuzzy controller to control the output voltage
and frequency of the inverter during starting for each load torque. The
starting characteristics using proposed method are compared to that of direct
on line and V/F methods. A complete model of the system is developed using
SIMULINK/MATLAB.
Hardware Implementation of Solar Based Boost to SEPIC Converter Fed Nine Leve...IJPEDS-IAES
Multi level inverters are widely used in high power applications because of
low harmonic distortion. This paper deals with the simulation
and implementation of PV based boost to SEPIC converter with multilevel
inverter. The output of PV system is stepped up using boost to sepic
converter and it is converted into AC using a multilevel inverter.
The simulation and experimental results with the R load is presented in this
paper. The FFT analysis is done and the THD values are compared. Boost to
SEPIC converter is proposed to step up the voltage to the required value. The
experimental results are compared with the simulation results. The results
indicate that nine level inverter system has better performance than seven
level inverter system.
Transformer Less Voltage Quadrupler Based DC-DC Converter with Coupled Induct...IJPEDS-IAES
In this paper a voltage quadrupler dc-dc converter with coupled inductor
and π filter is presented. The use of the coupled inductor reduces the high
leakage inductance which is present in a transformer enabled converter.
The output ripples in the converter is reduced by providing a π filter.
The interleaved voltage quadrupler is used in this system in order to boost the
output voltage. The voltage multiplier improves the output voltage gain.
The main advantage of this system is more voltage gain when compared with
the transformer eneabled circuit and the overall efficiency of the system is
improved. The circuit is simple to control. As a final point of this research,
the simulation and the hardware investigational results are presented to
demonstrate the effectiveness of this proposed converter.
IRAMY Inverter Control for Solar Electric VehicleIJPEDS-IAES
Solar Electric Vehicles (SEV) are considered the future vehicles to solve the issues of air pollution, global warming, and the rapid decreases of the petroleum resources facing the current transportation technology. However, SEV are still facing important technical obstacles to overcome. They include batteries energy storage capacity, charging times, efficiency of the solar panels and electrical propulsion systems. Solving any of those problems and electric vehicles will compete-complement the internal combustion engines vehicles. In the present work, we propose an electrical propulsion system based on three phase induction motor in order to obtain the desired speed and torque with less power loss. Because of the need to lightweight nature, small volume, low cost, less maintenance and high efficiency system, a three phase squirrel cage induction motor (IM) is selected in the electrical propulsion system. The IM is fed from three phase inverter operated by a constant V/F control method and Space Vector Pulse Width Modulation (SVPWM) algorithm. The proposed control strategy has been implemented on the texas instruments TM320F2812 Digital Signal Processor (DSP) to generate SVPWM signal needed to trigger the gates of IGBT based inverter. The inverter used in this work is a three phase inverter IRAMY20UP60B type. The experimental results show the ability of the proposed control strategy to generate a three-phase sine wave signal with desired frequency. The proposed control strategy is experimented on a locally manufactured EV prototype. The results show that the EV prototype can be propelled to speed up to 60km/h under different road conditions.
Design and Implementation of Single Phase AC-DC Buck-Boost Converter for Powe...IJPEDS-IAES
This paper discusses the Power Factor Correction (PFC) for single phase AC-DC Buck-Boost Converter (BBC) operated in Continuous Conduction Mode (CCM) using inductor average current mode control. The proposed control technique employs Proportional-Integral (PI) controller in the outer voltage loop and the Inductor Average Current Mode Control (IACMC) in the inner current loop for PFC BBC. The IACMC has advantages such as robustness when there are large variations in line voltage and output load. The PI controller is developed by using state space average model of BBC. The simulation of the proposed system with its control circuit is implemented in MatLab/Simulink. The simulation results show a nearly unity power factor can be attained and there is almost no change in power factor when the line frequency is at various ranges. Experimental results are provided to show its validity and feasibility.
Improvement of Wind farm with PMSG using STATCOMIJPEDS-IAES
This paper studies about the dynamic performance of the Permanent Magnet Synchronous Generator with Static Synchronous Compensator (STATCOM) for Wind farm integration. A whole dynamic model of wind energy conversion system (WECS) with PMSG and STATCOM are established in a MATLAB environment. With this model the dynamic behaviour of the generator and the overall system has been studied to determine the performance of them with and without STATCOM. Final results portrays that the WECS based PMSG with STATCOM improves the transient response of the wind farm when the system is in fault.
Modeling and Control of a Doubly-Fed Induction Generator for Wind Turbine-Gen...IJPEDS-IAES
This paper presents a vector control direct (FOC) of double fed induction generator intended to control the generated stator powers. This device is intended to be implemented in a variable-speed wind-energy conversion system connected to the grid. In order to control the active and reactive power exchanged between the machine stator and the grid, the rotor is fed by a bi-directional converter. The DFIG is controlled by standard relay controllers. Details of the control strategy and system simulation were performed using Simulink and the results are presented in this here to show the effectiveness of the proposed control strategy.
A Review on Design and Development of high Reliable Hybrid Energy Systems wit...IJPEDS-IAES
Hybrid Energy system is a combination of two or more different types of energy resources. Now a day this hybrid energy system plays key role in various remote area power applications. Hybrid energy system is more reliable than single energy system. This paper deals with high reliable hybrid energy system with solar, wind and micro hydro resources. The proposed hybrid system cable of multi mode operation and high reliable due to non communicated based controllers (Droop Characteristic Control) are used for optimal power sharing. Size of battery can be reduced because hydro used as back up source and Maximum power point Tracking also applied to solar and wind energy systems.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
AIRCRAFT GENERAL
The Single Aisle is the most advanced family aircraft in service today, with fly-by-wire flight controls.
The A318, A319, A320 and A321 are twin-engine subsonic medium range aircraft.
The family offers a choice of engines
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
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reduced, increasing the efficiency of the output. [9], [10] and [11] describe the generation of multilevel
output with a direct more number of switches that which is proposed. The proposed multilevel inverter
overcomes all these disadvantages while being more compact. Carrier based Pulse Width Modulation
(PWM) techniques are currently widely used due to their reduced computational requirement, simplicity and
robustness [12]. A novel PWM technique has been implemented which makes use of 15 carrier signals
compared with a reference signal which is fed to a 16-4 priority encoder to control the switching. The
proposed topology is evaluated by simulation and hardware implementation. The simulation is carried out in
MATLAB R2011a and the hardware implementation is carried out in a Xilinx based system generator facility
in union with a FPGA based processor [13].
2. PROPOSED MULTILEVEL INVERTER TOPOLOGY
The proposed MLI generated fifteen level output without using bidirectional switches and
capacitors. It consisted of four sources and diodes connected in between the switches S1, S2, S3, andS4 as
shown in the Figure 1. The sources V1, V2, V3 and V4 generate voltages in the ratio 8:4:2:1 respectively. The
H-Bridge inverter uses the four sources in series as its voltage source. The sources V1-V4 can be connected or
disconnected using the switches S1-S4 respectively for producing different voltage levels. Switches S5-S6are
used to control the direction of current flow and hence produces alternating output across the load. For the
generation of 15 level output, an Diode clamped MLI requires 24 Switching devices, 60 diodes and 12 dc
link capacitors whereas in the proposed topology, it requires only 8 switching devices and 4 diodes to
generate same fifteen level output, the details of which are shown in Table 1.
Figure 1. Proposed multilevel inverter topology
Table 1. Comparison of the per phase proposed topology with the conventional topologies
Nlevel Components
Conventional Topologies
Proposed
Topology
Diode
Clamped
Flying
Capacitor
Cascaded
Bridge
Referenced
Topology
15
Dc sources 1 1 7 1 4
Dc link capacitor 12 12 - - -
Diodes 60 - - 12 4
Clamping capacitors - 30 - - -
Switching devices (IGBT) 24 24 28 11 8
Considering the maximum dc link voltage level as Vdc, the inverter produced fifteen output-voltage
levels (Vdc/15, 2Vdc/15, 3Vdc/15, 4Vdc/15, 5Vdc/15, 6Vdc/15, 7Vdc/15, 8Vdc/15, 9Vdc/15, 10Vdc/15, 11Vdc/15,
12Vdc/15, 13Vdc/15, 14Vdc/15, Vdc) from the dc supply voltage.
The operation is divided into 15 modes having different voltage levels. Considering the variable
‘m’, Mode m will have the voltage level of (m-1)Vdc/15. The switching states of the 15 modes are illustrated
by Figure (2.1-2.15). The same voltage levels are obtained in negative as well.
The modified H-bridge topology is significantly advantageous over other topologies, i.e., less power
switches, power diodes, and less capacitor for inverters of the same number of level [14].
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Figure 2.1. Mode I Figure 2.2. Mode II Figure 2.3. Mode III Figure 2.4. Mode IV
Figure 2.5. Mode V Figure 2.6. Mode VI Figure 2.7. Mode VII Figure 2.8. Mode VIII
Figure 2.9. Mode IX Figure 2.10. Mode X Figure 2.11. Mode XI Figure 2.12. Mode XII
Figure 2.13. Mode XIII Figure 2.14. Mode XIV Figure 2.15. Mode XV
Figures 2.1 – 2.15. Show the various modes of operation of producing the DC link voltage
The switching sequence to the switches S1, S2, S3, S4 are given by a “Binary Logic”, in which the digits in the
binary system are formed such as 0000 to 1111. ‘0’ indicates that the switch is in OFF condition and ‘1’
indicates that Switch is in ON. This logic is explained in the next section. Based on this condition the
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switching sequence to the front end IGBT’s are fired, which generates the multilevel waveforms. The
positive levels are attained when switches S5 and S8 are ON and switches S6 and S7 are OFF and similarly,
negative levels are attained when switches S6 and S7 are ON and S5 and S8 are OFF respectively. The
Switching pulses for the H-Bridge IGBTs are controlled by normal sinusoidal pulse width modulation
technique, in which pair of IGBTs is fired simultaneously to obtain positive and negative cycle waveforms.
3. PROPOSED PWM TECHNIQUES
It is necessary to supply switching pulses to 8 switches in the circuit – 4(S1, S2, S3 and S4) that
produce the DC Link voltage and 4 (S5, S6, S7 and S8) in the H bridge inverter circuit. Different PWM
techniques are used here for each. For S5-S8, we use the normal SPWM technique. For generating the firing
pulses for the switches S1-S4, a novel PWM technique is described. In this technique, there is one reference
sine waveform, Vref and 15 triangular carrier waves (VCar1 – VCar15), each of much higher frequency than that
of Vref, as shown in Figure 3. In Figure 3, the topmost career wave is Vcar15 and the bottommost is Vcar1. Each
of the carrier waves is compared with the reference wave Vref. If the carrier signal’s instantaneous value is
less than that of the reference value, the comparator output is high. The outputs of the comparator values are
tabulated in Table 3. These outputs are fed to a 16-to-4 bit Priority Encoder; the output bits act as the trigger
pulses for switches S1-S4 as show (in Table 3). For example, consider the instant of time at which the output
is 13Vdc/15 – S4-ON, S3-ON, S2-OFF, S1-ON. This is the instant at which the value if Vcar13 becomes lesser
than Vref. Therefore the encoder produces the value “1101”, fed to the switches. Thus the switches S1-S4
switch at the rate of carrier signals. The firing pulses of the switches S1-S4 are shown in Figure 4.
Table 2 provides an insight about four arbitrary time frames of the waveform.The Switching Pulses
given to the H-bridge IGBT’s are controlled by normal SPWM. When a pair of switches is ON the other
switches are OFF and vice-versa. When S5 and S8 are ON positive half of the waveform is generated and
when S6 and S7 are ON, the negative half of waveform is formed. The firing pulses of the H-bridge are shown
in Figure 5.
Figure 3. Carrier and Reference waveforms Figure 4. Firing Pulses to Switches S1, S2, S3 and S4
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Figure 5. Firing Pulses to Switches S5, S6, S7 and S8 Figure 6. Simulink circuit of the proposed
multilevel topology inverter
Table 2. Some timeframes of the switching pulses of S1-S, shown in figure 5
Time S1 S2 S3 S4 DC Link Voltage
0.002 1 0 0 0 8Vdc/15
0.004 1 1 1 1 Vdc
0.008 1 0 0 1 9Vdc/15
0.010 0 0 0 1 Vdc/15
4. SIMULATION
The proposed topology is simulated in MATLAB/SIMULINK R2011a. Figure 6 shows the
simulated circuit. It consists of four front end IGBT’s (S1-S4) which are connected with a four DC voltage
sources rating V1=40V, V2=20V, V3=10V, V4=5V and diodes are connected to them as shown in the
circuit. It also consists of four IGBT’s which are connected in an H-bridge model as shown in the circuit.
Table 3. Truth Table for 15-to-4 Priority Encoder – ‘X’ represents a Don’t Care Condition
Inputs Outputs
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 S1 S2 S3 S4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1 X 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 X X 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 1 X X X 0 1 0 0
0 0 0 0 0 0 0 0 0 0 1 X X X X 0 1 0 1
0 0 0 0 0 0 0 0 0 1 X X X X X 0 1 1 0
0 0 0 0 0 0 0 0 1 X X X X X X 0 1 1 1
0 0 0 0 0 0 0 1 X X X X X X X 1 0 0 0
0 0 0 0 0 0 1 X X X X X X X X 1 0 0 1
0 0 0 0 0 1 X X X X X X X X X 1 0 1 0
0 0 0 0 1 X X X X X X X X X X 1 0 1 1
0 0 0 1 X X X X X X X X X X X 1 1 0 0
0 0 1 X X X X X X X X X X X X 1 1 0 1
0 1 X X X X X X X X X X X X X 1 1 1 0
1 X X X X X X X X X X X X X X 1 1 1 1
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Figure 7. Output voltage and current waveform for
proposed MLI
Figure 8. FFT Analysis for load voltage of proposed
MLI
The Switching pulses are given to the H Bridge circuit by normal sinusoidal pulse width modulation
technique (for the generation of positive and negative cycles). The switching pulses for the frontend IGBT’s
are given by the binary priority encoder logic as explained earlier (Circuit as shown in Figure 11). Table 3
shows the various switching pulse values of the frontend switches. These pulses are generated when the
reference signal overlaps the carrier signals. The pulses are generated along with a delay which is given to
each switch. Frequency of the Reference Sine wave is 50 Hz and those of the carrier waves are about 5 KHz
each. The output voltage and current waveforms of the 15 level MLI are shows in Figure 7. Figure 8 shows
the FFT analysis and the Total Harmonic Distortion (THD) obtained is about 5.08% for load voltage. Figure
9 shows the FFT analysis and the Total Harmonic Distortion (THD) obtained is about 5.28% for Load
Current.
The number of levels in the output may be changed dynamically by changing the value of the
Modulation Index (ma). The values of ma and the number of levels they correspond to are shown in
Table 4 and in Figure 10.
Figure 9. FFT Analysis for load current of proposed MLI Figure 10. Number of Levels Vs Modulation
Index
2 3 4 5 6 7 8 9 101112131415
0
5
10
15
20
0.133
0.267
0.4
0.533
0.667
0.8
0.933
Number of Levels Vs Modulation
Index
Number of
Levels
Linear
(Number
of Levels)
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Figure 11. MATMAB/SIMULINK Simulation circuit of Proposed Control
Technique using BINARY Code
Table. 4 Modulation Index
Vs.No.Of Levels
Modulation
Index (0-1)
Number of
Levels
(1-15)
0.133 2
0.200 3
0.267 4
0.333 5
0.400 6
0.467 7
0.533 8
0.600 9
0.667 10
0.733 11
0.800 12
0.867 13
0.933 14
1.0 15
Figure 12. Hardware implementation Figure 13. 5 level voltage output at ma=0.71
Figure 14. 5 level THD Spectrum at ma=0.71 Figure 15. 7 level voltage output at ma=1.0
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5. HARDWARE IMPLEMENTATION
Hardware implementation of the simulation is done by constructing a 7 level MLI prototype (Figure
12). The power switches and conditions are similar to that of the simulation, but the number of levels is
restricted to 7 due to economic constraints. However it is understood that once the operation of the seven
level MLI experimental setup is verified, the 15-level (simulated) MLI is only an extension to it. The
prototype comprises of seven IGBTs (FIO 5O-12BD), in which 3 IGBT are used as level producing which
are connected with an three DC voltage sources rating V1=20V, V1=10V, V2=5V and 3 diodes are connected
to them and rest of 4 IGBT are used as to design H-Bridge to produce the sine wave with the Deadband time
of 4.2 micro seconds is kept between each complimentary IGBT switching.The Xilinx based system
generator facility, a toolbox in MATLAB R2011a, was used to generate MC-PWM pulses. Spartan based
FPGA board (Spartan 3 XC3SFO-4PQ208C) is used for gernerating pulse to the MLI..
The output voltage waveform and THD spectrum for the Modulation Index value of 0.714
corresponding to 5 levels was captured in Figure 13 and 14; For the Modulation Index value of 1.0
corresponding to 7 levels was captured in Figure 15. The successful verification of the output of the hardware
model against the simulation validates the PWM technique. Moreover, it proves the practical feasibility of
the proposed MLI system.
6. COMPARISON WITH THE CONVENTIONAL METHODS
The number of source switches (SN) is determined basedon below equaltionfor the required m
output levels:
=
( )
+ 4 (1)
The proposed topology is superior to conventional CH bridge topology in terms of number of
semiconductor switches used. However in terms of dc sources used for a given level when compared, the
proposed topology is superior to [5] and conventional topologies as shown in the Table 1. For example, for a
13 level output the proposed topology utilizes 10 switches and single dc source for any number of levels
whereas the [5] and H bridge topology requires 10 and 24 switches with six dc sources respectively.Further,
the reduction of switching devices in the current path will result in the reduction of voltage drop and
conduction losses on the devices.
7. CONCLUSION
A single phase 15 level reduced switch MLI topology is introduced and its various modes of
operation are studied. A novel SPWM modulation approach is presented and utilized in the proposed
topology, theacceptable simulation results are then verified with a FPGA IP Core Processor based Hardware
prototype.
The results for the proposed system are summarized as follows:
1. The proposed MLI uses only 8 switches to give 15 level output
2. It is seen from the simulation results that the THD for the Output voltages and the current of the
proposed system is quite low when compared with the conventional inverter [5], [8].
3. The proposed system may be extended to a 3 phase 3 line system
4. This configuration of reduced circuit complexity will be adequate for low and medium power
applications whereas typical MLIs cannot compete with a standard UPS at (lower-) 2 level output
configurations. The inverter can easily be expanded by increasing the levels with minimum number of
switches, thus, the overall cost is reduced and the inverter generates higher quality output voltage.
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