In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is
capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging
available switches and dc sources in a fashion such that the maximum combination of addition and
subtraction of the input dc sources can be obtained. To verify the viability of the proposed topology, the
circuit model is developed and simulated in Matlab-Simulink software. Experimental testing results of the
proposed nine-level inverter topology, developed in the laboratory, are presented. A low frequency
switching strategy is employed in this work. The results show that the proposed topology is capable to
produce a nine-level output voltage, capable in handling inductive load and yields acceptable harmonic
distortion content.
Space Vector Modulation Strategy for NPC ConverterIRJET Journal
This document describes a control strategy for an eight-switch neutral point clamped (NPC) converter. The NPC converter uses only two legs instead of the conventional three legs to reduce the number of switches. A simplified space vector pulse width modulation (SVPWM) algorithm is used to calculate the time durations of the voltage vectors and generate control pulses for the switches. Computer simulations are presented to verify that the control strategy can regulate the DC bus voltage and draw sinusoidal line currents with unity power factor from the AC mains.
IRJET- Bidirectional Control of Resonant Converter in Power Electronic Tracti...IRJET Journal
This document presents a bidirectional control strategy for a LLC resonant converter used in a power electronic traction transformer (PETT) for locomotive applications. The strategy allows the converter to automatically adjust the power flow direction to keep the DC output voltage constant when the train transitions between traction and regenerative braking modes. A MATLAB/Simulink model is developed to simulate the LLC resonant converter using the proposed control strategy. Simulation results demonstrate the converter maintaining a constant 1500V output voltage under different load conditions while achieving soft-switching and high efficiency through the bidirectional control approach.
Analysis of Multilevel Inverter using Bipolar and Unipolar Switching Schemes ...ijsrd.com
Cascaded H-bridge Multilevel Inverter (MLI) is most efficient topology for medium and high voltage DC-AC conversion, having less output harmonics and less commutation losses. Disadvantages are their complexity, more number of power devices, passive components and a complex control circuitry. Here a Cascaded Hybrid Multilevel Inverter is used to produce a three phase 9-level output voltages. Now a day inverter is also know as a DC-AC converter, is one of the most popular part of electrical device. This proposed inverter widely used in industries application such as speed control of induction motor. This thesis focus on three phase 9-level bipolar and unipolar switching inverter with characteristics like output voltage boosting ability and also we discus about the bipolar and unipolar switching scheme along with capacitor voltage control. The modified topology uses Cascaded H-bridge (CHB) with bidirectional and unidirectional switches producing boost up output voltage. Here a hybrid Pulse Width Modulation (PWM) technique is applied to control the power devices. This modulation technique uses a sine wave and a repeating wave, these waves are combined and a complete reference wave is generated. There is comparative study between CHB and modified topology between number of power devices used and Total Harmonic Distortions (THD). THD of modified topology is reduced and analyzed by FFT window. The results are observed by MATLAB/SIMULINK software.
Application of SVM Technique for Three Phase Three Leg Ac/Ac Converter TopologyIOSR Journals
This paper presents a simulation of a three-phase three-leg AC/AC converter topology using nine IGBTs and space vector pulse width modulation (SVM) technique. The proposed topology reduces the number of switches compared to conventional back-to-back and matrix converters. Simulation results show the converter provides sinusoidal input and output voltages with unity power factor under constant frequency and variable frequency operation. Experimental results from a 5kVA prototype verify the validity of the proposed scheme.
Fuzzy Logic Controller Based High Frequency Link AC-AC Converter For Voltage ...IJTET Journal
Abstract—In this paper, an advanced high frequency link AC-AC Push-pull cycloconverter for the voltage compensation is proposed in order to maintain the power quality in electric grid. The proposed methodology can be achieve arbitrary output voltage without using large energy storage elements. So that the system is more steadfast and less costly compared with the conventional inverter topology. Additionally, the proposed converter does not contain any line frequency transformer, which reduces the cost further. The control scheme for the push pull cycloconverter employs the fuzzy logic controller based sinusoidal pulse width modulation (SPWM) to accomplish better performance on voltage compensation, like unbalanced voltage harmonics elimination. The simulation results are given to show the effectiveness of the proposed high frequency link AC-AC converter and fuzzy logic controller based SPWM technology
Improved performance with fractional order control for asymmetrical cascaded ...journalBEEI
This document discusses improving the performance of an asymmetrical cascaded H-bridge multilevel inverter (ACHBMLI) using fractional order control. A fractional order PID (FO-PID) controller is designed for a seven-level ACHBMLI using a simplified small signal model. Simulation results show the FO-PID controller maintains the output voltage closer to the reference voltage and reduces harmonic distortion compared to a conventional PID controller. The FO-PID controller provides improved robustness over a conventional PID controller for the ACHBMLI.
Harmonic Minimization In Multilevel Inverters By Using PSOIDES Editor
Harmonic Elimination in a multilevel inverters is
an optimization problem which is solved by applying particle
swarm optimization (PSO) technique. The derived equation
for the computation of total harmonic distortion (THD) of the
output voltage of the multilevel inverter is used as the objective
function in PSO algorithm. The objective function used is to
reduce the THD of the multilevel inverter and obtain the
corresponding switching angles with the elimination of
possible lower order harmonics. In this paper a pseudo code
based algorithm is proposed to deal with inequality constraints
which will helps in accelerating the optimization process. The
proposed method is applied for seven level cascade inverter to
eliminate the 5th and 7th order harmonics to reduce the total
harmonic distortion .This proposed PSO algorithm is effective
in reducing the total harmonic distortion corresponding the
range of modulation index. The simulation results shows that
the proposed PSO method is indeed capable of obtaining
higher quality of solutions to eliminate 5th and 7th order
harmonics and to reduce the total harmonic distortion of 7-
level cascade inverter
IRJET- Comparison of Conventional Single Phase 21-Level Cascaded H-Bridge Mul...IRJET Journal
The document compares a conventional single-phase 21-level cascaded H-bridge multilevel inverter to a proposed single-phase 21-level multilevel inverter with reduced switches and sources. The conventional inverter requires 40 IGBT switches and 10 separate DC sources, while the proposed topology requires only 8 IGBT switches and 4 separate DC sources to achieve 21 voltage levels. Simulation results show the output voltage waveform and total harmonic distortion for each inverter. The proposed topology has fewer switches, reducing cost and complexity compared to the conventional design.
Space Vector Modulation Strategy for NPC ConverterIRJET Journal
This document describes a control strategy for an eight-switch neutral point clamped (NPC) converter. The NPC converter uses only two legs instead of the conventional three legs to reduce the number of switches. A simplified space vector pulse width modulation (SVPWM) algorithm is used to calculate the time durations of the voltage vectors and generate control pulses for the switches. Computer simulations are presented to verify that the control strategy can regulate the DC bus voltage and draw sinusoidal line currents with unity power factor from the AC mains.
IRJET- Bidirectional Control of Resonant Converter in Power Electronic Tracti...IRJET Journal
This document presents a bidirectional control strategy for a LLC resonant converter used in a power electronic traction transformer (PETT) for locomotive applications. The strategy allows the converter to automatically adjust the power flow direction to keep the DC output voltage constant when the train transitions between traction and regenerative braking modes. A MATLAB/Simulink model is developed to simulate the LLC resonant converter using the proposed control strategy. Simulation results demonstrate the converter maintaining a constant 1500V output voltage under different load conditions while achieving soft-switching and high efficiency through the bidirectional control approach.
Analysis of Multilevel Inverter using Bipolar and Unipolar Switching Schemes ...ijsrd.com
Cascaded H-bridge Multilevel Inverter (MLI) is most efficient topology for medium and high voltage DC-AC conversion, having less output harmonics and less commutation losses. Disadvantages are their complexity, more number of power devices, passive components and a complex control circuitry. Here a Cascaded Hybrid Multilevel Inverter is used to produce a three phase 9-level output voltages. Now a day inverter is also know as a DC-AC converter, is one of the most popular part of electrical device. This proposed inverter widely used in industries application such as speed control of induction motor. This thesis focus on three phase 9-level bipolar and unipolar switching inverter with characteristics like output voltage boosting ability and also we discus about the bipolar and unipolar switching scheme along with capacitor voltage control. The modified topology uses Cascaded H-bridge (CHB) with bidirectional and unidirectional switches producing boost up output voltage. Here a hybrid Pulse Width Modulation (PWM) technique is applied to control the power devices. This modulation technique uses a sine wave and a repeating wave, these waves are combined and a complete reference wave is generated. There is comparative study between CHB and modified topology between number of power devices used and Total Harmonic Distortions (THD). THD of modified topology is reduced and analyzed by FFT window. The results are observed by MATLAB/SIMULINK software.
Application of SVM Technique for Three Phase Three Leg Ac/Ac Converter TopologyIOSR Journals
This paper presents a simulation of a three-phase three-leg AC/AC converter topology using nine IGBTs and space vector pulse width modulation (SVM) technique. The proposed topology reduces the number of switches compared to conventional back-to-back and matrix converters. Simulation results show the converter provides sinusoidal input and output voltages with unity power factor under constant frequency and variable frequency operation. Experimental results from a 5kVA prototype verify the validity of the proposed scheme.
Fuzzy Logic Controller Based High Frequency Link AC-AC Converter For Voltage ...IJTET Journal
Abstract—In this paper, an advanced high frequency link AC-AC Push-pull cycloconverter for the voltage compensation is proposed in order to maintain the power quality in electric grid. The proposed methodology can be achieve arbitrary output voltage without using large energy storage elements. So that the system is more steadfast and less costly compared with the conventional inverter topology. Additionally, the proposed converter does not contain any line frequency transformer, which reduces the cost further. The control scheme for the push pull cycloconverter employs the fuzzy logic controller based sinusoidal pulse width modulation (SPWM) to accomplish better performance on voltage compensation, like unbalanced voltage harmonics elimination. The simulation results are given to show the effectiveness of the proposed high frequency link AC-AC converter and fuzzy logic controller based SPWM technology
Improved performance with fractional order control for asymmetrical cascaded ...journalBEEI
This document discusses improving the performance of an asymmetrical cascaded H-bridge multilevel inverter (ACHBMLI) using fractional order control. A fractional order PID (FO-PID) controller is designed for a seven-level ACHBMLI using a simplified small signal model. Simulation results show the FO-PID controller maintains the output voltage closer to the reference voltage and reduces harmonic distortion compared to a conventional PID controller. The FO-PID controller provides improved robustness over a conventional PID controller for the ACHBMLI.
Harmonic Minimization In Multilevel Inverters By Using PSOIDES Editor
Harmonic Elimination in a multilevel inverters is
an optimization problem which is solved by applying particle
swarm optimization (PSO) technique. The derived equation
for the computation of total harmonic distortion (THD) of the
output voltage of the multilevel inverter is used as the objective
function in PSO algorithm. The objective function used is to
reduce the THD of the multilevel inverter and obtain the
corresponding switching angles with the elimination of
possible lower order harmonics. In this paper a pseudo code
based algorithm is proposed to deal with inequality constraints
which will helps in accelerating the optimization process. The
proposed method is applied for seven level cascade inverter to
eliminate the 5th and 7th order harmonics to reduce the total
harmonic distortion .This proposed PSO algorithm is effective
in reducing the total harmonic distortion corresponding the
range of modulation index. The simulation results shows that
the proposed PSO method is indeed capable of obtaining
higher quality of solutions to eliminate 5th and 7th order
harmonics and to reduce the total harmonic distortion of 7-
level cascade inverter
IRJET- Comparison of Conventional Single Phase 21-Level Cascaded H-Bridge Mul...IRJET Journal
The document compares a conventional single-phase 21-level cascaded H-bridge multilevel inverter to a proposed single-phase 21-level multilevel inverter with reduced switches and sources. The conventional inverter requires 40 IGBT switches and 10 separate DC sources, while the proposed topology requires only 8 IGBT switches and 4 separate DC sources to achieve 21 voltage levels. Simulation results show the output voltage waveform and total harmonic distortion for each inverter. The proposed topology has fewer switches, reducing cost and complexity compared to the conventional design.
Interleaved High Step-Down Synchronous Convertertheijes
For low output voltage, high output current systems applications, Synchronous switching power converters give better performance than non synchronous converters. This paper presents an interleaved synchronous buck converter which has low switch voltage stress with high conversion ratio. The input current can be shared among the inductors so that high reliability and efficiency can be obtained and ripples also reduced, the converter performance can be improved. Thus converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. Capacitors switching circuits are combined with interleaved four-phase buck converter for getting a high step-down conversion ratio without adopting an extreme short duty ratio. Synchronous rectifier technology is adopted to increase the converter efficiency. A 30V input voltage, 1.8V output voltage, circuit is simulated to verify the performance. The simulation is done in MATLAB/SIMULINK R2012a.
Prof. Cuk invited talk at APEC 2011 plenary session to celebrate
35 years of his creation of this modeling and analysis method.
This talk was also recorded on video by IEEE.tv and can be viewed together. Here is a link to that video.
https://youtu.be/BLx57J2fF5w
Note: first few minutes of the video is Prof. Cuk's interview made after his presentation. This is thern followed by full 25 minutes presentation, which can be followed by the enclosed 67 slides.
This document summarizes three topologies of cascaded H-bridge multilevel inverters: the existing topology, proposed topology I, and proposed topology II. The existing topology uses two DC sources per phase. Proposed topology I uses one DC source for all three phases and transformers. Proposed topology II also uses one DC source for all phases and reduces the number of switches compared to the other topologies. MATLAB simulations were performed and results were compared in terms of voltage THD and equipment requirements. The existing topology had the best performance based on FFT analysis, but proposed topology II is best in terms of cost and switching losses when considering single DC source topologies.
Structure of 15-Level Sub-Module Cascaded H-Bridge Inverter for Speed Control...IJPEDS-IAES
This paper deals with the implementation of a single phase 15-level Sub- Multilevel Cascaded H-Bridge Inverter (SMCHBI) for variable speed industrial drive applications. It consists of sub-multilevel modules and H- bridge inverter configuration. Sub-multilevel switches synthesize stepped DC link voltage and current from the DC sources. H-bridge inverter switches renovate stepped DC link voltage and current into sinusoidal waveform. Compared with conventional Cascaded Multilevel Inverter (CMLI), the proposed system employs the reduced number of power switches, DC sources and gate driver requirements. The proposed system not only reduces the overall system cost but also reduces the voltage stress across the inverter switches. The proposed system does not required additional resonant soft switching circuits for Zero Voltage Switching (ZVS) of inverter. In the proposed method, variable frequency method is adopted for the speed control of industrial induction motor drives. A prototype model of 15-level SMCHB is developed and the performance of the systems is validated experimentally.
Solar Panel Using Active Stacked Npc Multi Level Converterirjes
In this project, the operation and the features of a new three-level converter are presented with PV
source and boost converter. The proposed topology was named three-level active-stacked neutral point clamped.
It is a derivative of the 3L-SNPC structure, having two additional active switches connected anti parallel with
the clamp diodes. The main advantage of 3L-ASNPC converter is the reduction of the average switching
frequency for all power devices. In the same time, the apparent switching frequency of the output voltage is
doubled.
Four switch three phase brushless dc motor drive for hybrid vehiclesIAEME Publication
This document summarizes a paper that proposes a four-switch brushless DC motor drive for hybrid electric vehicles. It introduces a two-input DC-DC boost converter that interfaces a photovoltaic power source and battery for energy storage. The boost converter supplies regulated voltage to a four-switch BLDC motor drive for direct current control. Speed limitation is typically an issue for four-switch topologies but is addressed by regulating the boost converter output voltage according to motor speed. The document outlines the operating modes, current regulation, and back EMF compensation strategy of the four-switch drive as well as the speed limitation challenge it aims to solve.
Soft Computing Technique for the Control of Triple-Lift Luo ConverterIJERA Editor
Positive output Luo converters are a series of new DC-DC step-up (boost) converters, which were developed from prototypes using voltage lift technique. These converters perform positive to positive DC-DC voltage increasing conversion with high power density, high efficiency and cheap topology in simple structure. They are different from other existing DC-DC step-up converters with a high output voltage and small ripples. Triple lift LUO circuit is derived from positive output elementary Luo converter by adding the lift circuit three times. Due to the time varying and switching nature of the Luo converters, their dynamic behaviour becomes highly nonlinear. The classical control methods employed to design the controllers for Luo converters depend on the operating point so that it is very difficult to select control parameters because of the presence of parasitic elements, time varying loads and variable supply voltages. Conventional controllers require a good knowledge of the system and accurate tuning in order to obtain the desired performances. A fuzzy logic controller is a soft computing technique which neither requires a precise mathematical model of the system nor complex computations. The performances of the Triple-lift Luo converter with fuzzy logic controller are evaluated under line and load disturbances using Matlab-Simulink based simulation. The results are presented and analyzed.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
This document compares three switching methods for an asymmetric cascaded H-bridge multilevel inverter: selective harmonic elimination (SHE), nearest level control (NLC), and multi-carrier pulse width modulation (PWM). SHE and NLC aim to minimize total harmonic distortion but are offline methods not suitable for closed-loop systems. Multi-carrier PWM provides appropriate harmonic performance while being an online method. Equations are presented for generating PWM signals to control the switches in each cell based on multiple carrier waves to synthesize a high number of voltage levels from asymmetric DC input voltages. Simulation results show multi-carrier PWM has advantages over SHE and NLC for use in an asymmetric multilevel inverter system.
The document presents research on asymmetrical cascaded H-bridge multilevel inverters. It summarizes the structure and operation of 5-level, 7-level symmetrical, and 7-level and 9-level asymmetrical configurations. Simulation results show that asymmetrical configurations reduce harmonics without increasing components compared to symmetrical configurations. The conclusion is that asymmetrical multilevel inverters can produce more output levels without adding components by using different progression factors.
A New Configuration of Asymmetric Multilevel Converter to Maximize the Number...IJMTST Journal
The multilevel converters are increasingly becoming popular because of its high power applications. This research paper describes about the new structure that can produce increased number of output voltage waveform using a single source and reduced number of power electronic components. In designing a multilevel converter, the power electronic switches play a very imperative role as it describes the installation area, cost, configuration complexity and may more things that play a significant role while designing. The prime function of multilevel converter is to abolish total harmonic distortion and to incorporate desired ac voltage from several separate dc sources. Each level consists of H-Bridge converter units. High efficiency, high voltage capability, lower switching losses are its prime advantages. A multilevel power converter structure can be introduced as an alternative in medium voltage and high power situations. This structure not only achieves high power ratings but also empower the use of renewable energy sources. It finds its basic application in adjustable speed drives, Static Compensator (STATCOM).
A New Multilevel Inverter with Reduced Number of SwitchesIAES-IJPEDS
In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.
Simulation Of A 4-Switch,3-Phase Inverter Fed Induction Motor (IM) Drive Systemijiert bestjournal
This document summarizes a research paper on simulating a 4-switch, 3-phase inverter driving an induction motor. It begins with an abstract describing the research goal of developing a more cost-effective induction motor drive using a 4-switch inverter instead of a conventional 6-switch inverter. It then provides details on the drive system components, the 4-switch inverter topology, a space vector pulse width modulation control approach, and simulation results showing the speed, torque and current characteristics meeting performance needs while reducing costs. The conclusion is that the 4-switch inverter fed induction motor drive is acceptable considering cost reduction without compromising operation.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Swit...Scientific Review
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through simulation and the simulation results are compared with the conventional multilevel inverter. From the result the proposed inverter offers much less total harmonic distortion.
Efficiency and Power Factor improvement of Bridgeless Soft-switched PWM Cuk C...IOSR Journals
This document summarizes a research paper that proposes a bridgeless single-phase AC-DC soft-switched PWM Cuk converter with multiplier control to improve efficiency and power factor. Key points:
1) The proposed converter removes the input diode bridge and uses an auxiliary circuit to achieve zero-voltage switching, reducing losses and improving efficiency compared to conventional Cuk converters.
2) Multiplier control is used to regulate the output voltage, further improving efficiency.
3) The bridgeless design and soft-switching results in less input current harmonics and nearly unity power factor.
4) The document outlines the circuit configuration, operating principles, design process, and simulation results of the proposed efficient and high
The International Journal of Engineering and Science (The IJES)theijes
The document compares a conventional full bridge buck DC-DC converter and an LCL-T type buck DC-DC converter through simulation. Simulation results show that the proposed 4-switch LCL-T buck converter has higher efficiency than the conventional full bridge converter. Key advantages of the LCL-T converter include reduced switching losses due to zero-voltage switching, improved electrical performance from the front-end LCL-T connection, and multi-output capability from associating one or two capacitors for resonant operation. The LCL-T converter is well-suited for low voltage, low power applications.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Cascaded H-Bridge Multilevel Inverter Using SPWM and MSPWM StrategiesIJERA Editor
This document presents a comparison of SPWM and MSPWM control techniques for cascaded H-bridge multilevel inverters with different levels (three, five, and seven). Simulations are conducted in Matlab/Simulink and Proteus. Hardware implementations are also developed using an Arduino microcontroller. The total harmonic distortion (THD) of the output voltage waveform is calculated both before and after filtering and compared for each control technique and number of levels. Increasing the number of levels and using MSPWM control are found to reduce the THD compared to other configurations. Experimental results match the simulation results for the different setups.
A Five – Level Integrated AC – DC ConverterIJTET Journal
This paper presents the implementation of a new five – level integrated AC – DC converter with high input power factor and reduced input current harmonics complied with IEC1000-3-2 harmonic standards for electrical equipments. The proposed topology is a combination of boost input power factor pre – regulator and five – level DC – DC converter. The single – stage PFC (SSPFC) approach used in this topology is an alternative solution to low – power and cost – effective applications.
A Novel Multi Port Dc/Dc Converter Topology Using Zero Voltage Switching For...IJMER
This paper proposes a novel four-port DC/DC converter topology that can interface two renewable energy sources, a bidirectional battery storage port, and an isolated load port. The topology is derived from a traditional half-bridge converter with the addition of two switches and diodes. All four main switches can achieve zero-voltage switching, reducing switching losses. MATLAB simulations and experimental results validate the circuit operation and regulation of the multiple power ports via independent duty cycle control. The proposed topology is suitable for applications integrating hybrid photovoltaic and wind energy systems with battery storage.
Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Var...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
- A new 15-level inverter is proposed for solar PV applications that generates 15 stepped output voltage levels using only 8 switches and 3 DC sources, reducing components, losses, and cost compared to existing multilevel inverters.
- The inverter is tested experimentally and shown to operate efficiently under both linear and non-linear loads while maintaining stability during dynamic conditions, making it suitable for grid-connected systems.
- A literature review finds the proposed inverter has lower total harmonic distortion than existing inverters due to its reduced number of components.
Interleaved High Step-Down Synchronous Convertertheijes
For low output voltage, high output current systems applications, Synchronous switching power converters give better performance than non synchronous converters. This paper presents an interleaved synchronous buck converter which has low switch voltage stress with high conversion ratio. The input current can be shared among the inductors so that high reliability and efficiency can be obtained and ripples also reduced, the converter performance can be improved. Thus converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. Capacitors switching circuits are combined with interleaved four-phase buck converter for getting a high step-down conversion ratio without adopting an extreme short duty ratio. Synchronous rectifier technology is adopted to increase the converter efficiency. A 30V input voltage, 1.8V output voltage, circuit is simulated to verify the performance. The simulation is done in MATLAB/SIMULINK R2012a.
Prof. Cuk invited talk at APEC 2011 plenary session to celebrate
35 years of his creation of this modeling and analysis method.
This talk was also recorded on video by IEEE.tv and can be viewed together. Here is a link to that video.
https://youtu.be/BLx57J2fF5w
Note: first few minutes of the video is Prof. Cuk's interview made after his presentation. This is thern followed by full 25 minutes presentation, which can be followed by the enclosed 67 slides.
This document summarizes three topologies of cascaded H-bridge multilevel inverters: the existing topology, proposed topology I, and proposed topology II. The existing topology uses two DC sources per phase. Proposed topology I uses one DC source for all three phases and transformers. Proposed topology II also uses one DC source for all phases and reduces the number of switches compared to the other topologies. MATLAB simulations were performed and results were compared in terms of voltage THD and equipment requirements. The existing topology had the best performance based on FFT analysis, but proposed topology II is best in terms of cost and switching losses when considering single DC source topologies.
Structure of 15-Level Sub-Module Cascaded H-Bridge Inverter for Speed Control...IJPEDS-IAES
This paper deals with the implementation of a single phase 15-level Sub- Multilevel Cascaded H-Bridge Inverter (SMCHBI) for variable speed industrial drive applications. It consists of sub-multilevel modules and H- bridge inverter configuration. Sub-multilevel switches synthesize stepped DC link voltage and current from the DC sources. H-bridge inverter switches renovate stepped DC link voltage and current into sinusoidal waveform. Compared with conventional Cascaded Multilevel Inverter (CMLI), the proposed system employs the reduced number of power switches, DC sources and gate driver requirements. The proposed system not only reduces the overall system cost but also reduces the voltage stress across the inverter switches. The proposed system does not required additional resonant soft switching circuits for Zero Voltage Switching (ZVS) of inverter. In the proposed method, variable frequency method is adopted for the speed control of industrial induction motor drives. A prototype model of 15-level SMCHB is developed and the performance of the systems is validated experimentally.
Solar Panel Using Active Stacked Npc Multi Level Converterirjes
In this project, the operation and the features of a new three-level converter are presented with PV
source and boost converter. The proposed topology was named three-level active-stacked neutral point clamped.
It is a derivative of the 3L-SNPC structure, having two additional active switches connected anti parallel with
the clamp diodes. The main advantage of 3L-ASNPC converter is the reduction of the average switching
frequency for all power devices. In the same time, the apparent switching frequency of the output voltage is
doubled.
Four switch three phase brushless dc motor drive for hybrid vehiclesIAEME Publication
This document summarizes a paper that proposes a four-switch brushless DC motor drive for hybrid electric vehicles. It introduces a two-input DC-DC boost converter that interfaces a photovoltaic power source and battery for energy storage. The boost converter supplies regulated voltage to a four-switch BLDC motor drive for direct current control. Speed limitation is typically an issue for four-switch topologies but is addressed by regulating the boost converter output voltage according to motor speed. The document outlines the operating modes, current regulation, and back EMF compensation strategy of the four-switch drive as well as the speed limitation challenge it aims to solve.
Soft Computing Technique for the Control of Triple-Lift Luo ConverterIJERA Editor
Positive output Luo converters are a series of new DC-DC step-up (boost) converters, which were developed from prototypes using voltage lift technique. These converters perform positive to positive DC-DC voltage increasing conversion with high power density, high efficiency and cheap topology in simple structure. They are different from other existing DC-DC step-up converters with a high output voltage and small ripples. Triple lift LUO circuit is derived from positive output elementary Luo converter by adding the lift circuit three times. Due to the time varying and switching nature of the Luo converters, their dynamic behaviour becomes highly nonlinear. The classical control methods employed to design the controllers for Luo converters depend on the operating point so that it is very difficult to select control parameters because of the presence of parasitic elements, time varying loads and variable supply voltages. Conventional controllers require a good knowledge of the system and accurate tuning in order to obtain the desired performances. A fuzzy logic controller is a soft computing technique which neither requires a precise mathematical model of the system nor complex computations. The performances of the Triple-lift Luo converter with fuzzy logic controller are evaluated under line and load disturbances using Matlab-Simulink based simulation. The results are presented and analyzed.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
This document compares three switching methods for an asymmetric cascaded H-bridge multilevel inverter: selective harmonic elimination (SHE), nearest level control (NLC), and multi-carrier pulse width modulation (PWM). SHE and NLC aim to minimize total harmonic distortion but are offline methods not suitable for closed-loop systems. Multi-carrier PWM provides appropriate harmonic performance while being an online method. Equations are presented for generating PWM signals to control the switches in each cell based on multiple carrier waves to synthesize a high number of voltage levels from asymmetric DC input voltages. Simulation results show multi-carrier PWM has advantages over SHE and NLC for use in an asymmetric multilevel inverter system.
The document presents research on asymmetrical cascaded H-bridge multilevel inverters. It summarizes the structure and operation of 5-level, 7-level symmetrical, and 7-level and 9-level asymmetrical configurations. Simulation results show that asymmetrical configurations reduce harmonics without increasing components compared to symmetrical configurations. The conclusion is that asymmetrical multilevel inverters can produce more output levels without adding components by using different progression factors.
A New Configuration of Asymmetric Multilevel Converter to Maximize the Number...IJMTST Journal
The multilevel converters are increasingly becoming popular because of its high power applications. This research paper describes about the new structure that can produce increased number of output voltage waveform using a single source and reduced number of power electronic components. In designing a multilevel converter, the power electronic switches play a very imperative role as it describes the installation area, cost, configuration complexity and may more things that play a significant role while designing. The prime function of multilevel converter is to abolish total harmonic distortion and to incorporate desired ac voltage from several separate dc sources. Each level consists of H-Bridge converter units. High efficiency, high voltage capability, lower switching losses are its prime advantages. A multilevel power converter structure can be introduced as an alternative in medium voltage and high power situations. This structure not only achieves high power ratings but also empower the use of renewable energy sources. It finds its basic application in adjustable speed drives, Static Compensator (STATCOM).
A New Multilevel Inverter with Reduced Number of SwitchesIAES-IJPEDS
In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.
Simulation Of A 4-Switch,3-Phase Inverter Fed Induction Motor (IM) Drive Systemijiert bestjournal
This document summarizes a research paper on simulating a 4-switch, 3-phase inverter driving an induction motor. It begins with an abstract describing the research goal of developing a more cost-effective induction motor drive using a 4-switch inverter instead of a conventional 6-switch inverter. It then provides details on the drive system components, the 4-switch inverter topology, a space vector pulse width modulation control approach, and simulation results showing the speed, torque and current characteristics meeting performance needs while reducing costs. The conclusion is that the 4-switch inverter fed induction motor drive is acceptable considering cost reduction without compromising operation.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Swit...Scientific Review
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through simulation and the simulation results are compared with the conventional multilevel inverter. From the result the proposed inverter offers much less total harmonic distortion.
Efficiency and Power Factor improvement of Bridgeless Soft-switched PWM Cuk C...IOSR Journals
This document summarizes a research paper that proposes a bridgeless single-phase AC-DC soft-switched PWM Cuk converter with multiplier control to improve efficiency and power factor. Key points:
1) The proposed converter removes the input diode bridge and uses an auxiliary circuit to achieve zero-voltage switching, reducing losses and improving efficiency compared to conventional Cuk converters.
2) Multiplier control is used to regulate the output voltage, further improving efficiency.
3) The bridgeless design and soft-switching results in less input current harmonics and nearly unity power factor.
4) The document outlines the circuit configuration, operating principles, design process, and simulation results of the proposed efficient and high
The International Journal of Engineering and Science (The IJES)theijes
The document compares a conventional full bridge buck DC-DC converter and an LCL-T type buck DC-DC converter through simulation. Simulation results show that the proposed 4-switch LCL-T buck converter has higher efficiency than the conventional full bridge converter. Key advantages of the LCL-T converter include reduced switching losses due to zero-voltage switching, improved electrical performance from the front-end LCL-T connection, and multi-output capability from associating one or two capacitors for resonant operation. The LCL-T converter is well-suited for low voltage, low power applications.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Cascaded H-Bridge Multilevel Inverter Using SPWM and MSPWM StrategiesIJERA Editor
This document presents a comparison of SPWM and MSPWM control techniques for cascaded H-bridge multilevel inverters with different levels (three, five, and seven). Simulations are conducted in Matlab/Simulink and Proteus. Hardware implementations are also developed using an Arduino microcontroller. The total harmonic distortion (THD) of the output voltage waveform is calculated both before and after filtering and compared for each control technique and number of levels. Increasing the number of levels and using MSPWM control are found to reduce the THD compared to other configurations. Experimental results match the simulation results for the different setups.
A Five – Level Integrated AC – DC ConverterIJTET Journal
This paper presents the implementation of a new five – level integrated AC – DC converter with high input power factor and reduced input current harmonics complied with IEC1000-3-2 harmonic standards for electrical equipments. The proposed topology is a combination of boost input power factor pre – regulator and five – level DC – DC converter. The single – stage PFC (SSPFC) approach used in this topology is an alternative solution to low – power and cost – effective applications.
A Novel Multi Port Dc/Dc Converter Topology Using Zero Voltage Switching For...IJMER
This paper proposes a novel four-port DC/DC converter topology that can interface two renewable energy sources, a bidirectional battery storage port, and an isolated load port. The topology is derived from a traditional half-bridge converter with the addition of two switches and diodes. All four main switches can achieve zero-voltage switching, reducing switching losses. MATLAB simulations and experimental results validate the circuit operation and regulation of the multiple power ports via independent duty cycle control. The proposed topology is suitable for applications integrating hybrid photovoltaic and wind energy systems with battery storage.
Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Var...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
- A new 15-level inverter is proposed for solar PV applications that generates 15 stepped output voltage levels using only 8 switches and 3 DC sources, reducing components, losses, and cost compared to existing multilevel inverters.
- The inverter is tested experimentally and shown to operate efficiently under both linear and non-linear loads while maintaining stability during dynamic conditions, making it suitable for grid-connected systems.
- A literature review finds the proposed inverter has lower total harmonic distortion than existing inverters due to its reduced number of components.
A three-phase bidirectional isolated dc-dc converter consists of two six-pulse two-level active converters that enable bidirectional power flow by introducing a lag phase-shift angle of one converter with respect to the other converter. This paper explains the operating modes of a three-phase bidirectional isolated dc-dc converter in detail, taking into account the transfer of energy between the dc voltage sources and high-frequency ac inductances in the three-phase bidirectional isolated dc-dc converter. The power flow of the dc-dc converter is also examined based on the operating modes.
Analysis of 7-Level Cascaded & MLDCLI with Sinusoidal PWM & Modified Referenc...IJMTST Journal
This document compares the performance of a 7-level cascaded multilevel inverter and a 7-level multilevel DC link inverter (MLDCLI) using sinusoidal PWM and modified reference PWM control techniques. Simulation results show that the 7-level MLDCLI with modified reference PWM produces the highest fundamental output voltage with the lowest total harmonic distortion. The MLDCLI topology requires fewer switches and components than other multilevel inverter topologies as the number of voltage levels increases, making it advantageous for higher level designs.
This paper introduces a new topology of multilevel inverter, which is able to operate at high performance. This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level inverters need at least twelve switches. The proposed topology has only ten switches. The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms. The detailed operation of the proposed inverter is explained. The theoretical analysis and design procedure are given. Simulation results are presented to confirm the analytical approach of the proposed circuit. A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Based Design and Validation of Asymmetrical Reduced Switch Multilevel In...IJPEDS-IAES
This document summarizes a research paper that proposes a new asymmetrical multilevel inverter topology with a reduced number of switches. The topology uses four voltage sources with levels in a specific ratio to produce 15 output levels using only 8 switches and 4 diodes, reducing complexity compared to other topologies. The operation is simulated in MATLAB and validated through an FPGA-based hardware prototype. Simulation results show the output voltage waveform and a total harmonic distortion lower than conventional inverters.
Simulation and analysis of multilevel inverter with reduced number of switchesIAEME Publication
This document summarizes a research paper that proposes a new multilevel inverter topology with reduced number of switches compared to conventional cascaded H-bridge multilevel inverters. The proposed topology is a five-level inverter that requires only six switches compared to eight switches in a conventional design. Simulation results show the performance of the new topology is validated using MATLAB/Simulink software. The paper also describes the operating modes and switching techniques used in the new multilevel inverter design, including phase disposition, alternative phase opposition disposition, and phase opposition disposition pulse width modulation strategies.
Modified T-type topology of three-phase multi-level inverter for photovoltaic...IJECEIAES
In this article, a three-phase multilevel neutral-point-clamped inverter with a modified t-type structure of switches is proposed. A pulse width modulation (PWM) scheme of the proposed inverter is also developed. The proposed topology of the multilevel inverter has the advantage of being simple, on the one hand since it does contain only semiconductors in reduced number (corresponding to the number of required voltage levels), and no other components such as switching or flying capacitors, and on the other hand, the control scheme is much simpler and more suitable for variable frequency and voltage control. The performances of this inverter are analyzed through simulations carried out in the MATLAB/Simulink environment on a threephase inverter with 9 levels. In all simulations, the proposed topology is connected with R-load or RL-load without any output filter.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
IRJET- Design and Implementation of Isolated Multi-Output Flyback ConverterIRJET Journal
This document describes the design and implementation of an isolated multi-output flyback converter. A flyback converter uses a single switch and transformer to provide isolated output voltages from an input source. The designed converter uses a toroidal transformer with multiple secondary windings to generate multiple isolated output voltages at fixed levels. Simulation results and specifications for the transformer, switch, and outputs are provided. The flyback converter provides an efficient and low-cost solution for applications requiring multiple isolated low-power DC outputs.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
Development of a Novel Three Phase Grid-Tied Multilevel Inverter TopologyIAES-IJPEDS
The conventional line-commutated ac-to-dc converters/ inverters have square-shaped line current. It contains higher-order harmonics which generates EMI and it causes more heating of the core of distribution or power transformers. PWM based inverters using MOSFET/IGBT have higher switching losses, and the power handling capability and reliability are quite low in comparison to thyristors/ SCR. A thyristor based forced commutated inverters are not suitable for PWM applications due to the problems of commutation circuits. A pure sinusoidal voltage output or waveform with low harmonic contents is most desirable for ac load using dc to ac conversion. This paper presents a new multilevel inverter topology in which three phase ac- to-dc converter circuits are used in inversion mode by controlling the switching angle. Due to natural commutation, no separate circuit is required for synchronization. In this paper simulation and analysis are done for grid-tied three-phase 6-pulse, Two three-phase, 3-pulse and 12-pulse converter. These converters are analysed for different battery voltage and different switching angle combinations in order to reduce the total harmonic distortion (THD). Three-phase harmonic filters are further added to the grid side to reduce the harmonic content in the line current. A comparative study of these converters is also presented in this paper.
Implementation of Three phase SPWM Inverter with Minimum Number of Power Elec...IJMTST Journal
In the past decades, the researchers have dealt with the conventional topology, which possesses sum switches of Multilevel Inverter is applied to PWM method. The present research work has been introduced a new method of multilevel inverter using reduced switches is applied with PWM technique. In introduction part the conventional new multilevel inverter & switching pattern are explained. In second part PWM technique of proposed work and circuits is explained. The width of this pulses are modulated in order to obtain inverter output voltage control and to reduce its harmonic content. Sinusoidal pulse width modulation or SPWM is the most common method in motor control and inverter application. Conventionally, to generate the signal, triangle wave as a carrier signal is compared with the sinusoidal wave, whose frequency is the desired frequency.
This document summarizes a research paper that proposes a non-isolated three-port SEPIC converter for standalone photovoltaic applications. The converter uses a single-input multi-output structure with a photovoltaic source as the single input. Mathematical analysis is performed and simulations are carried out in MATLAB/Simulink to verify the design. Hardware implementation and testing is also conducted, and results match the simulation analysis. The converter operates in continuous current mode to supply two loads - a resistive load and a dynamic motor load - from a single photovoltaic source.
Multilevel inverters offers less distortion and less electro-magnetic interference compared with other conventional inverters and hence, it can be used in many industrial and commercial applications. This paper analyze the performance of the modified single phase seven level symmetrical inverter using minimum number of switches. The proposed topology consists of six switches and two dc sources, and produces seven level output voltage waveform during symmetric operation. The cost and size of the propsoed inverter minimum as it uses minimum number of components, The performance of the proposed multilevel inverter is analysed for different switching angles and the corresponding simulation results are presented. The simulation of the proposed inverter is carried out using MATLAB/Simulink software.
Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter. This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/SIMULINK. Experimental results are presented to validate the effectiveness of the operation of the diode clamped multilevel inverter using field programmable gate array.
This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators with easier implementation. The analysis four various control strategies namely Common Carrier (CC), Inverted Carrier (IC), Phase Shifted (PS) and Inverted Phase Shift (IPS) for cascaded multilevel inverter fed induction motor drive has been illustrated. To validate the proposed work experimental tests has been carried out using dSPACE controller. Experimental study proves that using proposed algorithms reduction in common-mode voltage with fewer harmonics along with reduced switching loss for a cascaded multilevel inverter fed motor drive has been achieved.
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Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
Design and simulation an optimal enhanced PI controller for congestion avoida...TELKOMNIKA JOURNAL
This document describes using a snake optimization algorithm to tune the gains of an enhanced proportional-integral controller for congestion avoidance in a TCP/AQM system. The controller aims to maintain a stable and desired queue size without noise or transmission problems. A linearized model of the TCP/AQM system is presented. An enhanced PI controller combining nonlinear gain and original PI gains is proposed. The snake optimization algorithm is then used to tune the parameters of the enhanced PI controller to achieve optimal system performance and response. Simulation results are discussed showing the proposed controller provides a stable and robust behavior for congestion control.
Improving the detection of intrusion in vehicular ad-hoc networks with modifi...TELKOMNIKA JOURNAL
Vehicular ad-hoc networks (VANETs) are wireless-equipped vehicles that form networks along the road. The security of this network has been a major challenge. The identity-based cryptosystem (IBC) previously used to secure the networks suffers from membership authentication security features. This paper focuses on improving the detection of intruders in VANETs with a modified identity-based cryptosystem (MIBC). The MIBC is developed using a non-singular elliptic curve with Lagrange interpolation. The public key of vehicles and roadside units on the network are derived from number plates and location identification numbers, respectively. Pseudo-identities are used to mask the real identity of users to preserve their privacy. The membership authentication mechanism ensures that only valid and authenticated members of the network are allowed to join the network. The performance of the MIBC is evaluated using intrusion detection ratio (IDR) and computation time (CT) and then validated with the existing IBC. The result obtained shows that the MIBC recorded an IDR of 99.3% against 94.3% obtained for the existing identity-based cryptosystem (EIBC) for 140 unregistered vehicles attempting to intrude on the network. The MIBC shows lower CT values of 1.17 ms against 1.70 ms for EIBC. The MIBC can be used to improve the security of VANETs.
Conceptual model of internet banking adoption with perceived risk and trust f...TELKOMNIKA JOURNAL
Understanding the primary factors of internet banking (IB) acceptance is critical for both banks and users; nevertheless, our knowledge of the role of users’ perceived risk and trust in IB adoption is limited. As a result, we develop a conceptual model by incorporating perceived risk and trust into the technology acceptance model (TAM) theory toward the IB. The proper research emphasized that the most essential component in explaining IB adoption behavior is behavioral intention to use IB adoption. TAM is helpful for figuring out how elements that affect IB adoption are connected to one another. According to previous literature on IB and the use of such technology in Iraq, one has to choose a theoretical foundation that may justify the acceptance of IB from the customer’s perspective. The conceptual model was therefore constructed using the TAM as a foundation. Furthermore, perceived risk and trust were added to the TAM dimensions as external factors. The key objective of this work was to extend the TAM to construct a conceptual model for IB adoption and to get sufficient theoretical support from the existing literature for the essential elements and their relationships in order to unearth new insights about factors responsible for IB adoption.
Efficient combined fuzzy logic and LMS algorithm for smart antennaTELKOMNIKA JOURNAL
The smart antennas are broadly used in wireless communication. The least mean square (LMS) algorithm is a procedure that is concerned in controlling the smart antenna pattern to accommodate specified requirements such as steering the beam toward the desired signal, in addition to placing the deep nulls in the direction of unwanted signals. The conventional LMS (C-LMS) has some drawbacks like slow convergence speed besides high steady state fluctuation error. To overcome these shortcomings, the present paper adopts an adaptive fuzzy control step size least mean square (FC-LMS) algorithm to adjust its step size. Computer simulation outcomes illustrate that the given model has fast convergence rate as well as low mean square error steady state.
Design and implementation of a LoRa-based system for warning of forest fireTELKOMNIKA JOURNAL
This paper presents the design and implementation of a forest fire monitoring and warning system based on long range (LoRa) technology, a novel ultra-low power consumption and long-range wireless communication technology for remote sensing applications. The proposed system includes a wireless sensor network that records environmental parameters such as temperature, humidity, wind speed, and carbon dioxide (CO2) concentration in the air, as well as taking infrared photos.The data collected at each sensor node will be transmitted to the gateway via LoRa wireless transmission. Data will be collected, processed, and uploaded to a cloud database at the gateway. An Android smartphone application that allows anyone to easily view the recorded data has been developed. When a fire is detected, the system will sound a siren and send a warning message to the responsible personnel, instructing them to take appropriate action. Experiments in Tram Chim Park, Vietnam, have been conducted to verify and evaluate the operation of the system.
Wavelet-based sensing technique in cognitive radio networkTELKOMNIKA JOURNAL
Cognitive radio is a smart radio that can change its transmitter parameter based on interaction with the environment in which it operates. The demand for frequency spectrum is growing due to a big data issue as many Internet of Things (IoT) devices are in the network. Based on previous research, most frequency spectrum was used, but some spectrums were not used, called spectrum hole. Energy detection is one of the spectrum sensing methods that has been frequently used since it is easy to use and does not require license users to have any prior signal understanding. But this technique is incapable of detecting at low signal-to-noise ratio (SNR) levels. Therefore, the wavelet-based sensing is proposed to overcome this issue and detect spectrum holes. The main objective of this work is to evaluate the performance of wavelet-based sensing and compare it with the energy detection technique. The findings show that the percentage of detection in wavelet-based sensing is 83% higher than energy detection performance. This result indicates that the wavelet-based sensing has higher precision in detection and the interference towards primary user can be decreased.
A novel compact dual-band bandstop filter with enhanced rejection bandsTELKOMNIKA JOURNAL
In this paper, we present the design of a new wide dual-band bandstop filter (DBBSF) using nonuniform transmission lines. The method used to design this filter is to replace conventional uniform transmission lines with nonuniform lines governed by a truncated Fourier series. Based on how impedances are profiled in the proposed DBBSF structure, the fractional bandwidths of the two 10 dB-down rejection bands are widened to 39.72% and 52.63%, respectively, and the physical size has been reduced compared to that of the filter with the uniform transmission lines. The results of the electromagnetic (EM) simulation support the obtained analytical response and show an improved frequency behavior.
Deep learning approach to DDoS attack with imbalanced data at the application...TELKOMNIKA JOURNAL
A distributed denial of service (DDoS) attack is where one or more computers attack or target a server computer, by flooding internet traffic to the server. As a result, the server cannot be accessed by legitimate users. A result of this attack causes enormous losses for a company because it can reduce the level of user trust, and reduce the company’s reputation to lose customers due to downtime. One of the services at the application layer that can be accessed by users is a web-based lightweight directory access protocol (LDAP) service that can provide safe and easy services to access directory applications. We used a deep learning approach to detect DDoS attacks on the CICDDoS 2019 dataset on a complex computer network at the application layer to get fast and accurate results for dealing with unbalanced data. Based on the results obtained, it is observed that DDoS attack detection using a deep learning approach on imbalanced data performs better when implemented using synthetic minority oversampling technique (SMOTE) method for binary classes. On the other hand, the proposed deep learning approach performs better for detecting DDoS attacks in multiclass when implemented using the adaptive synthetic (ADASYN) method.
The appearance of uncertainties and disturbances often effects the characteristics of either linear or nonlinear systems. Plus, the stabilization process may be deteriorated thus incurring a catastrophic effect to the system performance. As such, this manuscript addresses the concept of matching condition for the systems that are suffering from miss-match uncertainties and exogeneous disturbances. The perturbation towards the system at hand is assumed to be known and unbounded. To reach this outcome, uncertainties and their classifications are reviewed thoroughly. The structural matching condition is proposed and tabulated in the proposition 1. Two types of mathematical expressions are presented to distinguish the system with matched uncertainty and the system with miss-matched uncertainty. Lastly, two-dimensional numerical expressions are provided to practice the proposed proposition. The outcome shows that matching condition has the ability to change the system to a design-friendly model for asymptotic stabilization.
Implementation of FinFET technology based low power 4×4 Wallace tree multipli...TELKOMNIKA JOURNAL
Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.
Evaluation of the weighted-overlap add model with massive MIMO in a 5G systemTELKOMNIKA JOURNAL
The flaw in 5G orthogonal frequency division multiplexing (OFDM) becomes apparent in high-speed situations. Because the doppler effect causes frequency shifts, the orthogonality of OFDM subcarriers is broken, lowering both their bit error rate (BER) and throughput output. As part of this research, we use a novel design that combines massive multiple input multiple output (MIMO) and weighted overlap and add (WOLA) to improve the performance of 5G systems. To determine which design is superior, throughput and BER are calculated for both the proposed design and OFDM. The results of the improved system show a massive improvement in performance ver the conventional system and significant improvements with massive MIMO, including the best throughput and BER. When compared to conventional systems, the improved system has a throughput that is around 22% higher and the best performance in terms of BER, but it still has around 25% less error than OFDM.
Reflector antenna design in different frequencies using frequency selective s...TELKOMNIKA JOURNAL
In this study, it is aimed to obtain two different asymmetric radiation patterns obtained from antennas in the shape of the cross-section of a parabolic reflector (fan blade type antennas) and antennas with cosecant-square radiation characteristics at two different frequencies from a single antenna. For this purpose, firstly, a fan blade type antenna design will be made, and then the reflective surface of this antenna will be completed to the shape of the reflective surface of the antenna with the cosecant-square radiation characteristic with the frequency selective surface designed to provide the characteristics suitable for the purpose. The frequency selective surface designed and it provides the perfect transmission as possible at 4 GHz operating frequency, while it will act as a band-quenching filter for electromagnetic waves at 5 GHz operating frequency and will be a reflective surface. Thanks to this frequency selective surface to be used as a reflective surface in the antenna, a fan blade type radiation characteristic at 4 GHz operating frequency will be obtained, while a cosecant-square radiation characteristic at 5 GHz operating frequency will be obtained.
Reagentless iron detection in water based on unclad fiber optical sensorTELKOMNIKA JOURNAL
A simple and low-cost fiber based optical sensor for iron detection is demonstrated in this paper. The sensor head consist of an unclad optical fiber with the unclad length of 1 cm and it has a straight structure. Results obtained shows a linear relationship between the output light intensity and iron concentration, illustrating the functionality of this iron optical sensor. Based on the experimental results, the sensitivity and linearity are achieved at 0.0328/ppm and 0.9824 respectively at the wavelength of 690 nm. With the same wavelength, other performance parameters are also studied. Resolution and limit of detection (LOD) are found to be 0.3049 ppm and 0.0755 ppm correspondingly. This iron sensor is advantageous in that it does not require any reagent for detection, enabling it to be simpler and cost-effective in the implementation of the iron sensing.
Impact of CuS counter electrode calcination temperature on quantum dot sensit...TELKOMNIKA JOURNAL
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
A progressive learning for structural tolerance online sequential extreme lea...TELKOMNIKA JOURNAL
This article discusses the progressive learning for structural tolerance online sequential extreme learning machine (PSTOS-ELM). PSTOS-ELM can save robust accuracy while updating the new data and the new class data on the online training situation. The robustness accuracy arises from using the householder block exact QR decomposition recursive least squares (HBQRD-RLS) of the PSTOS-ELM. This method is suitable for applications that have data streaming and often have new class data. Our experiment compares the PSTOS-ELM accuracy and accuracy robustness while data is updating with the batch-extreme learning machine (ELM) and structural tolerance online sequential extreme learning machine (STOS-ELM) that both must retrain the data in a new class data case. The experimental results show that PSTOS-ELM has accuracy and robustness comparable to ELM and STOS-ELM while also can update new class data immediately.
Electroencephalography-based brain-computer interface using neural networksTELKOMNIKA JOURNAL
This study aimed to develop a brain-computer interface that can control an electric wheelchair using electroencephalography (EEG) signals. First, we used the Mind Wave Mobile 2 device to capture raw EEG signals from the surface of the scalp. The signals were transformed into the frequency domain using fast Fourier transform (FFT) and filtered to monitor changes in attention and relaxation. Next, we performed time and frequency domain analyses to identify features for five eye gestures: opened, closed, blink per second, double blink, and lookup. The base state was the opened-eyes gesture, and we compared the features of the remaining four action gestures to the base state to identify potential gestures. We then built a multilayer neural network to classify these features into five signals that control the wheelchair’s movement. Finally, we designed an experimental wheelchair system to test the effectiveness of the proposed approach. The results demonstrate that the EEG classification was highly accurate and computationally efficient. Moreover, the average performance of the brain-controlled wheelchair system was over 75% across different individuals, which suggests the feasibility of this approach.
Adaptive segmentation algorithm based on level set model in medical imagingTELKOMNIKA JOURNAL
For image segmentation, level set models are frequently employed. It offer best solution to overcome the main limitations of deformable parametric models. However, the challenge when applying those models in medical images stills deal with removing blurs in image edges which directly affects the edge indicator function, leads to not adaptively segmenting images and causes a wrong analysis of pathologies wich prevents to conclude a correct diagnosis. To overcome such issues, an effective process is suggested by simultaneously modelling and solving systems’ two-dimensional partial differential equations (PDE). The first PDE equation allows restoration using Euler’s equation similar to an anisotropic smoothing based on a regularized Perona and Malik filter that eliminates noise while preserving edge information in accordance with detected contours in the second equation that segments the image based on the first equation solutions. This approach allows developing a new algorithm which overcome the studied model drawbacks. Results of the proposed method give clear segments that can be applied to any application. Experiments on many medical images in particular blurry images with high information losses, demonstrate that the developed approach produces superior segmentation results in terms of quantity and quality compared to other models already presented in previeous works.
Automatic channel selection using shuffled frog leaping algorithm for EEG bas...TELKOMNIKA JOURNAL
Drug addiction is a complex neurobiological disorder that necessitates comprehensive treatment of both the body and mind. It is categorized as a brain disorder due to its impact on the brain. Various methods such as electroencephalography (EEG), functional magnetic resonance imaging (FMRI), and magnetoencephalography (MEG) can capture brain activities and structures. EEG signals provide valuable insights into neurological disorders, including drug addiction. Accurate classification of drug addiction from EEG signals relies on appropriate features and channel selection. Choosing the right EEG channels is essential to reduce computational costs and mitigate the risk of overfitting associated with using all available channels. To address the challenge of optimal channel selection in addiction detection from EEG signals, this work employs the shuffled frog leaping algorithm (SFLA). SFLA facilitates the selection of appropriate channels, leading to improved accuracy. Wavelet features extracted from the selected input channel signals are then analyzed using various machine learning classifiers to detect addiction. Experimental results indicate that after selecting features from the appropriate channels, classification accuracy significantly increased across all classifiers. Particularly, the multi-layer perceptron (MLP) classifier combined with SFLA demonstrated a remarkable accuracy improvement of 15.78% while reducing time complexity.
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...University of Maribor
Slides from talk presenting:
Aleš Zamuda: Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapter and Networking.
Presentation at IcETRAN 2024 session:
"Inter-Society Networking Panel GRSS/MTT-S/CIS
Panel Session: Promoting Connection and Cooperation"
IEEE Slovenia GRSS
IEEE Serbia and Montenegro MTT-S
IEEE Slovenia CIS
11TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTING ENGINEERING
3-6 June 2024, Niš, Serbia
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
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increment is in exponential pattern. The same case goes to other conventional MLI namely the
Neutral Point Clamp (NPC) [18] and Flying Capacitor (FC) MLI [19].
The exponential increment in the number of power switches and component count to
obtain the higher number of levels is the down side of the conventional MLI. Progress on
developing a new MLI topology with high number of levels, but reduced number of component
count is active and is still carried out [20-29]. Referring to the previous researchers, the MLI
topologies with reduced number of component count can be categorized under two, namely the
topologies with H-bridge or without H-bridge. Commonly H- Bridge is used to solely to function
as polarity change. Their merits and downside has been thoroughly discussed in [15].
In this paper a new MLI topology is proposed that is capable to produce nine-level
output voltage with reduce component counts. The idea is to arrange available switches and dc
sources in a fashion such that the maximum combination of addition and subtraction of the input
dc sources can achieve. To verify the design, the circuit is developed via Matlab simulation tool.
Simulation results are recorded to analyze the performance of the circuit. This paper is
organized in different sections. In Section 2, circuit configuration of the proposed topology and
switching pulses pattern is discussed. Then its operation in different modes is explained.
Section 3 deals with the comparative study of the proposed topology with other existing
topologies. Circuit parameters and results are discussed in section 4 followed by a conclusion.
2. The Proposed Multilevel Inverter
2.1. Circuit Description
Figure 1 shows the schematic circuit topology of the proposed nine levels asymmetrical
multilevel inverter. It consists of two parts i.e. Level generator and polarity changer (H- Bridge).
The level generator produces different output levels by connecting available dc sources through
switches in different arrangements. The polarity changer converts the output of the level
generator into alternating voltage. Proposed topology requires nine switches and two
asymmetrical dc sources, defined as V1 and V2. Switches S1 − S5 are for level generator circuit
and four switches i.e. Sa1, Sa2, Sb1 and Sb2 for H-Bridge.
Polarity Changer
Sa1
Sb2
Sb1
Sa2
V1
V2
S1
S2
S3
S4
S5
Vo
+_
Level Generator
-1Vdc
-2Vdc
-3Vdc
-4Vdc
Sa1,Sa2
Sb1,Sb2
4Vdc
3Vdc
2Vdc
1Vdc
S1
S2
S3
S4
S5
0
Figure 1. Proposed nine-level inverter circuit
topology
Figure 2. Switching pulses pattern for one
complete cycle of the proposed nine-level
inverter
Asymmetrical dc sources are independent of each other and are in ratio of V1:V2 = 1:3.
In order to prevent the short circuit of the sources, simultaneous conduction of the switches (S1,
S2), (S3, S4), (S4, S5), (Sa1, Sb1), (Sa2, Sb2) must be avoided. This can be done by proper
switching of the switches. Figure 2 shows the switching pulses for one complete cycle. All the
switches operate at low frequency. The conduction period is short for all switches except the
polarity changer switches. Hence, it envisages that the power losses in the circuit are reduced
significantly.
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40
2.2. Modes of Operation
Figure 3 shows different modes of operation in the positive half cycle of the proposed
topology. The path follows by the current for different modes is indicated with the thicker line.
For one complete cycle, the circuit will be operated in nine different modes i.e. four for positive
half cycle, four for negative half cycle and one mode for zero level. In this way, each mode is
responsible for generating one output voltage level. Switching states of the switches, the
magnitude of the output voltage in per unit and path followed by the current in each mode is
tabulated in Table 1. Modes I(a)-IV(a), positive cycle modes, produces positive output levels
and Modes I(b)-IV(d), negative cycle modes, produces negative output levels. It is evident from
the table that switching sequence of the switches S1−S5 is same in both the half cycle.
Whereas the switches (Sa1, Sa2) and (Sb1, Sb2) conducts only during positive half and
negative half cycle respectively.
Sa1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Sa1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Sa1 Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Mode I(a) Mode II(a) Mode III(a)
Sa1 Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Sa1 Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Sa1
Sb2
Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Mode IV(a) Mode Zero Mode I(b)
Sa1 Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Sa1 Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Sa1 Sb1
Sa2
V1
V2
S1
S2S3
S4
S5
Vo
+_
Mode II(b) Mode III(b) Mode IV(b)
Figure 3. Different Switching state of the proposed nine-level inverter topology during positive half
cycle
Table 1. Modes of Operation: Switching sequence, current path and output voltage
Modes
Switching Sequence (ON Switches)
Current Path
Output Volt.
(per unit)Level Generator Polarity Changer
I (a) S1, S5 Sa1, Sa2 S5–V1–S1–Sa1–Sa2 1V
II (a) S2, S3 Sa1, Sa2 V2–S3–V1–S2–Sa1–Sa2 2V
III (a) S2, S4 Sa1, Sa2 V2–S4–S2– Sa1–Sa2 3V
IV (a) S1, S4 Sa1, Sa2 V2–S4–V1–S1–Sa1–Sa2 4V
Zero S2, S5 Sa1, Sa2 Sa1–Voutput –Sa2 0
Zero S2, S5 Sb1, Sb2 Sb1–Voutput –Sb2 0
I (b) S1, S5 Sb1, Sb2 S5–V1–S1–Sb1–Sb2 -1V
II (b) S2, S3 Sb1, Sb2 V2–S3–V1–S2–Sb1–Sb2 -2V
III (b) S2, S4 Sb1, Sb2 V2–S4–S2– Sb1–Sb2 -3V
IV (b) S1, S4 Sb1, Sb2 V2–S4–V1–S1–Sb1–Sb2 -4V
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3. Comparison with Other Topologies
Comparative study, based on the number of switches, diodes, dc links and total
component count, of the proposed topology with other existing topologies for nine-level output is
carried out and the results are tabulated in Table 2. The other compared topologies includes:
conventional cascaded H-bridge (CHB), Neutral Point Capacitor (NPC), Fly-Capacitor (FC),
asymmetrical CHB and the topologies presented in [17] and [28].
In [17], an asymmetrical multilevel inverter is proposed with reduce device count. For
nine level output, it utilizes 12 switches including two bidirectional switches (counted as four
switches) and 2 dc sources, which are lesser in than required by other conventional CHB, NPC
and FC inverters. However, asymmetrical CHB inverter with tertiary source combination
requires only two dc sources and eight switches with auxiliary diodes. In [28], a new
asymmetrical inverter topology is with reduce device count is presented. Proposed nine level
inverter also requires two dc sources, but number of auxiliary diodes reduces to four as the
remaining switches are unidirectional. Number of components require by the proposed topology
is 15 which is a lowest number than other comparable topologies. As the number of device
count increases reliability decreases and the cost, losses as well as complexity in the circuit
increases. Therefore, the proposed inverter depicts better performance than other topologies.
Table 2. Comparison of conventional and some existing asymmetrical inverter topology
No. of NPC FC
CHB
[17] [28] ProposedUrinary Tertiary
Switches 16 16 16 8 12 10 9
Diodes 9 16 16 8 12 10 4
DC Links 4 7 4 2 4 2 2
Total 29 42 36 18 28 22 15
4. Results and Analysis
To verify the performance of the proposed topology, simulation model based on
Figure 1 is developed in Matlab-Simulink software. Circuit is simulated at a fundamental
frequency of 50Hz. In order to obtain a ternary source arrangement with maximum output of
400V, the value of the DC sources are taken as V1 =100V and V2=300V. The inverter is
operated in open loop mode and different load conditions (R and RL load) are assumed.
Fundamental frequency switching control modulation scheme has been used [1]. In this scheme
of modulation, the reference signal is a sinusoidal voltage waveform which is compared with the
available dc levels. Level close to reference is chosen. As this is a low switching frequency
method [29]. This method leads to lower switching losses.
(b) Switching Pulses for polarity changer
switches
(a) Switching Pulses for level-generator
switches
(c) Level generator output voltage waveform.
Figure 4. Simulation results for proposed nine level inverter topology
0 0.005 0.01 0.015 0.02
S1
0 0.005 0.01 0.015 0.02
S2
0 0.005 0.01 0.015 0.02
S3
0 0.005 0.01 0.015 0.02
S4
0 0.005 0.01 0.015 0.02
S5
0 0.005 0.01 0.015 0.02
Sa1,Sa2
0 0.005 0.01 0.015 0.02
Sb1,Sb2
0 0.005 0.01 0.015 0.02
100
200
300
400
FFT window
Time (s)
Voltage(V)
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Figure 4 shows the switching pulses given to different switches of the proposed inverter.
It is clear from the figure that the switches are operated according to Table 1, thus avoid short
circuiting of the sources.
Output voltage and current waveform of the inverter and their corresponding harmonic
spectrum for resistive (R) load of 150ohm (Power Factor: P.F=1) is shown in Figure 5.
Simulation results for resistive-inductive (R-L) load at P.F=0.9 is presented in Figure 6.
(a) Output voltage waveform (b) Voltage Output Harmonic spectrum
(c) Load current waveform (d) Load Current Harmonic spectrum
Figure 5. Simulation Output results at 50Hz fundamental frequency for R = 150ohm
(a) Output voltage waveform (b) Voltage Output Harmonic spectrum
(c) Load current waveform (d) Load Current Harmonic spectrum
Figure 6. Simulation Output results at 50Hz fundamental frequency for R = 150ohm, L= 240,
P.F = 0.9
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-400
-300
-200
-100
0
100
200
300
400
FFT window
Time (s)
Voltage(V)
0 5 10 15 20
0
5
10
20
30
40
50
Harmonic order
Fundamental (50Hz) = 425.9 , THD= 9.19%
Mag(%ofFundamental)
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-3
-2
-1
0
1
2
3
FFT window
Time (s)
Current(A)
0 5 10 15 20
0
5
10
20
30
40
50
Harmonic order
Fundamental (50Hz) = 2.84 , THD= 9.19%Mag(%ofFundamental)
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-400
-300
-200
-100
0
100
200
300
400
FFT window
Time (s)
Voltage(V)
0 5 10 15 20
0
5
10
20
30
40
50
Harmonic order
Fundamental (50Hz) = 426 , THD= 9.19%
Mag(%ofFundamental)
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-3
-2
-1
0
1
2
3
FFT window
Time (s)
Current(A)
0 5 10 15 20
2
10
20
30
40
50
Harmonic order
Fundamental (50Hz) = 2.537 , THD= 2.12%
Mag(%ofFundamental)
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Asymmetrical Nine-Level Inverter Topology with Reduce Power Semicondutor… (M. S. Arif)
43
The voltage waveform shows that the proposed topology is able to generate nine level
output (four positive, four negative and one zero) with almost uniform step size. Output current
waveform with R-L load, shown in Figure 6(c), justify the operation of the proposed topology.
The output voltage without using filter has Total harmonic distortion (THD) of 9.19% and the
magnitude of each individual harmonic is less than 5%, satisfying the condition of IEEE-519 Std.
(i.e. max harmonic for each order is 5%). Whereas THD in load current is 2.12% with R-L load
(P.F=0.9).
(a) Driver circuit output to the switches S1, S2,
S3 and S4
(b) Driver circuit output to the switches S5,
Sa1 and Sb1
(c) Output Voltage waveform of the proposed
nine level inverter
(d) Output current waveform of the proposed
nine level inverter
(e) Output voltage and current waveform of
the proposed nine level inverter
(f) FFT spectrum for one complete cycle of the
output voltage
Figure 7. Experimental results of the propose nine-level inverter
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44
In order to verify the simulation result and to analyse the performance of the proposed
topology in generating desired output voltages, single phase 9 level inverter prototypes has
been implemented and tested in laboratory. IGBTs model IRGP35B60PDPBF has been used as
switches. DC sources V1= 20V and V2 = 60 are used in order to get voltage step size of 20V
each. For driving IGBTs, switching pulses were generated using digital signal controller
(DspTM320F2812). These pulses are applied between gate and emitter of IGBTs through driver
circuits. Output voltage waveforms were measured by Teledyne LeCory WAVESURFUR-3034
digital storage oscilloscope using potential probe (voltage ratio 1/50) and THD has been
recorded using power quality analyser KEW-6310 manufactured by Kyoritsu Electrical
Instruments.
Figure 7(a) and 7(b) shows the output pulses from the driver circuit give to the switches.
Output voltage and current waveform of the proposed 9-level inverter at unity power factor for a
frequency of 50Hz is shown in Figure 7(c) and Figure 7(d) respectively. FFT spectrum for one
cycle of experimental waveform is illustrated in Figure 7(f), indicating the THD of 9% for 9-level
inverter.
5. Conclusion
In this paper a new single-phase multilevel inverter topology is presented. Proposed
topology is capable of producing nine-level output voltage with reduce device counts. It can be
used in medium and high power application with unequal dc sources. Different modes of
operation are discussed in detail. On the bases of device counts, the proposed topology is
compared with conventional as well as other asymmetrical nine-level inverter topologies
presented in literature. Comparative study shows that, for nine level output, the proposed
topology requires lesser component counts then the conventional and other topologies.
Proposed circuit is modeled in Matlab/Simulink environment. Detailed Simulation analysis is
carried out and validated experimentally. Experimental prototype of the proposed nine-level
inverter is developed and tested in the laboratory. Results obtained show that topology works
properly. As the THD obtained in the output voltage without filtering is 8.95% in simulation and
9.0% in experimental testing whereas the each harmonic order is < 5%, satisfies harmonic
Standard (IEEE-519).
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