This paper introduces a new topology of multilevel inverter, which is able to operate at high performance. This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level inverters need at least twelve switches. The proposed topology has only ten switches. The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms. The detailed operation of the proposed inverter is explained. The theoretical analysis and design procedure are given. Simulation results are presented to confirm the analytical approach of the proposed circuit. A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz.

1. International Journal of Power Electronics and Drive System (IJPEDS)
Vol. 11, No. 4, December 2020, pp. 1883∼1889
ISSN: 2088-8694, DOI: 10.11591/ijpeds.v11.i4.pp1883-1889 r 1883
A high-performance multilevel inverter with reduced power
electronic devices
Amer Chlaihawi, Adnan Sabbar, Hur Jedi
Department of Electrical Engineering, University of Kufa, Iraq
Article Info
Article history:
Received Feb 20, 2020
Revised Apr 26, 2020
Accepted May 19, 2020
Keywords:
High-performance operation
Multilevel inverter (MLI)
Nearest level modulation
(NLM)
ABSTRACT
This paper introduces a new topology of multilevel inverter, which is able to operate
at high performance. This proposed circuit achieves requirements of reduced number
of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level
inverters need at least twelve switches. The proposed topology has only ten switches.
The inverter has a quasi-sine output voltage, which is formed by level generator and
polarity changer to produce the desired voltage and current waveforms. The detailed
operation of the proposed inverter is explained. The theoretical analysis and design
procedure are given. Simulation results are presented to confirm the analytical ap-
proach of the proposed circuit. A 15-level and 31-level multilevel inverters were de-
signed and tested at 50 Hz.
This is an open access article under the CC BY-SA license.
Corresponding Author:
Adnan Sabbar,
Department of Electrical Engineering,
University of Kufa, Najaf, Iraq.
Email: adnan.sabbar@uokufa.edu.iq
1. INTRODUCTION
With the rapid development of power electronics, the demand of power converters are high perfor-
mance, low cost and high power quality applications [1–3]. Reducing the number of switches in power elec-
tronics can improve the power density and leads to low voltage stress on switches [4–7]. Multilevel converters
can attain both fundamental switching frequency and high switching frequency PWM [8–10]. Therefore, mul-
tilevel inverters with separate DC sources are suited for operation at low frequency to achieve low switching
losses and high efficiency [11–13]. Inverters in such application handle high voltage and extensive power. Thus,
high-level inverters, which are composed of switching power devices integrated gate bipolar transistors (IG-
BTs), are suitable to achieve high voltage applications [14, 15]. Most conventional multilevel inverters, such as
Flying Capacitor (FC), Neutral Point Clamped (NPC), and Cascaded H-Bridge (CHB) suffer from high-voltage
stress on switch, high Electro Magnetic Interference (EMI) and poor power quality output [16–18]. In order to
solve these issues, a new topology of multilevel inverter is presented.
In last few decades, several authors have been increasingly focused on multilevel inverter topologies
with reduction in numbers of power switches [19–23]. Topology [24] is combined of IGBT and diode causing
reduction in efficiency. In addition, the losses and cost will be increased and its industrial applications will be
restricted. In [25] sub-multilevel converter blocks are connected in series. This circuit consists of capacitors
and four bi-directional switches are utilized in each unit. Thus, the installation area is increased in the proposed
topology. Most of the multilevel inverters suffer from high voltage stresses at the power switches and require
different voltage rating of the power switches. In addition, switching frequency leads to a decrease in efficiency
Journal homepage: http://ijpeds.iaescore.com

2. 1884 r ISSN: 2088-8694
due to switching losses. Therefore, the proposed topology is attractive for high-performance applications.
This work proposes a high power quality multilevel inverter with reduced in numbers of power semi-
conductor devices. The proposed topology can attain a large number of levels with asymmetric DC voltage
sources. This topology is based on the conventional inverter that utilizes level generation and polarity change.
The new circuit can be utilized for 15-level and 31-level inverter. To implement a 15-level inverter, ten IGBT
switches and three dc voltage sources are selected. The multilevel inverter generates staircase voltage waveform
with decreased electromagnetic compatibility (EMC) issues and low distortion. The new topology also utilizes
low number of power switches and includes a low-design complexity. The described topology also shows in
details the analysis of the steady-state voltage waveforms. In order to determine an appropriate characteristics
of the multilevel inverter, a design procedure has been applied. The proposed circuit was simulated and tested
at a frequency of 50 Hz. A control unit of signals are used to generate fixed values of operating frequency and
duty ratio. Collectively, these features make the new multilevel inverter advantageous in applications, such as
AC drives and FACTS devices.
2. ANALYSIS OF THE PROPOSED MULTILEVEL INVERTER TOPOLOGY
Figure 1 shows the proposed multilevel inverter circuit. The proposed topology consist of level gen-
erate and polarity change. The level generation has power switch Pi and power switch Si, which is connected
in series with the DC voltage source Vi. The circuit of polarity change is comprised H-Bridge power switches
HSi and connected in parallel with the load. In this study, IGBT transistors, which have high switching perfor-
mance, are used in the proposed topology. We focus on identifying the characteristics of the proposed inverter
to provide a flexible output voltage waveform across the load of the circuit with minimum number of switches.
,^ϭ
ǀŽ
Wϭ
>ŽĂĚ
sŝ
>ĞǀĞů'ĞŶĞƌĂƚŽƌ
WϮ
Wϯ
^Ϯ
^ϭ
^ϯ
Ϯsŝ
ϰsŝ
,^Ϯ
,^ϯ
,^ϰ
WŽůĂƌŝƚLJŚĂŶŐĞƌ
Figure 1. Proposed multilevel inverter circuit
The new topology can produce fifteen-level output during asymmetric condition. The operating modes
during asymmetric operation of the circuit to obtain alternating output voltage across the load is shown in
Figure 2. The proposed topology requires six switches and three DC voltage sources to generate positive-levels
steps output voltage at the load as shown in the left part of the inverter. A polarity changer, which is comprised
of four switches, is added to generate the negative-levels steps output voltage at the load. The switches HSi
are utilized to reverse the polarity of the output voltage of the inverter. The analysis of the proposed circuit is
based on the the ON-state and the OFF-state of the switches Pi and Si, respectively. The switches HS1 and
HS4 are ON during the positive cycle of the operation, while the switches HS2 and HS4 are OFF during the
negative cycle of the operation.
Int J Pow Elec Dri Syst, Vol. 11, No. 4, December 2020 : 1883 – 1889

3. Int J Pow Elec Dri Syst ISSN: 2088-8694 r 1885
Ϭsŝ
ǀŽ
ƚ
ϭsŝ
Ϯsŝ
ϱsŝ
ϰsŝ
ϯsŝ
ϲsŝ
ϳsŝ
Wϭ
WϮ
Wϯ
,ϭ
,ϯ
,ϭ
,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ ,ϯ
,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ ,ϭ
^ϭ
WϮ
Wϯ
^Ϯ ^ϭ ^ϯ ^ϭ ^Ϯ ^ϭ
Wϭ ^Ϯ Wϭ ^ϯ ^ϯ ^Ϯ
Wϯ Wϯ WϮ WϮ Wϭ ^ϯ
Figure 2. Operation mode of switches.
Figure 3 shows the illustrating operation of idealized steps of the circuit over a period. As can be
seen, each step for output voltage is double of the voltage source Vi. The switches Pi and Si of the inverter
can be derived according to the control unit circuit to generate pulse width modulator waveforms as shown in
Figure 4.
sŝ
Ϯsŝ
ϰsŝ
ϭ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ǀŽ
Ϯ
Figure 3. Level modulation
technique
^ϭ
^Ϯ
^ϯ
Wϭ
WϮ
Wϯ
Figure 4. Control unit of signals
for 15-level switches
To establish the design equations, the circuit behavior is analyzed in each interval. It is considered Vi
as a reference voltage in the proposed multilevel inverter. The number of DC voltage sources NV base on the
number of unit cell m in the inverter
N = 2m
, (1)
where, m = 0, 1, 2, 3...i. The steps of output voltage Dsteps can be found as
Dsteps = 2i+2
− 1. (2)
The maximum output voltage vO is the sum of DC voltage sources N
vO =
Dsteps − 1
2
Vi. (3)
The power switches of the proposed topology can be switched at any duty cycle D. It can be determined based
on the specifications of the multilevel inverter.
A high-performance multilevel inverter with reduced power electronic devices (Amer Chlaihawi)

4. 1886 r ISSN: 2088-8694
3. DESIGN PROCEDURE
A design procedure for the new multilevel inverter is presented to supply a resistive load at operating
frequency fs = 50 Hz. In the design procedure, the following design parameters Vi, vO, and D are determined.
The reference DC voltage source Vi for 15-level and 31-level were chosen to be 45 V and 20 V , respectively.
Furthermore, the duty cycle of power switches is 50%. The reference DC voltage Vi can be selected basing on
the application of the inverter. In the proposed circuit, the designer can easily adjust the value of duty cycle
to achieve the required driven voltage waveform of the power switches. For 15-level output and step voltage
45 V, the peak-to-peak output voltage of the multilevel inverter is varied from +312 to -312. For the 31-level
inverter, the reference DC voltage Vi = 20 V is applied at the proposed circuit, the peak value of voltage
stress is 312 V at duty cycle D = 50%. The peak value of the voltage stress depends on the total DC source
voltage on the power switch. The value of vGE voltage based on the characteristics of the power switch IGBT
in the inverter. Therefore, it is important to select a proper driving voltage rating for the power switch. In this
work, the voltage vGE rating of the power switch, which is utilized in the gate driver, is 20 V. The transistor
BUP306D was utilized as a IGBT power switch in circuit. The load of the proposed inverter is chosen to be a
resistive load RL = 50 Ω.
The major differences between the proposed topology and the popular multilevel inverters are the
number of power switches and the type of switching. Thus, most multilevel inverter circuits operate at least
twelve power switches. To operate fifteen-level inverter, the proposed multilevel inverter has six switches in the
level generation and four switches in the H-bridge. Furthermore, the switching behavior of IGBT transistors
in the proposed multilevel inverter can achieve high voltage applications. Therefore, the performance of the
inverter can increase the efficiency of the inverter. These features show the the advantage of the new circuit.
The specifications and parameters of the circuit are given in Table 1.
Table 1. List of parameters for multilevel inverter at fs = 50 Hz
Components Value
BUP306D
VCE = 1200 V, VGE = 20 V, IC = 23 A
Ciss = 1300 pF, Coss = 100 pF, Crss = 50 pF
R 50 Ω
Vi 45 V, 20 V
4. SIMULATION RESULTS
Based on the design methodology and the circuit operation, the proposed multilevel inverter has been
verified through MatLab simulation. The performance of the proposed topology during the asymmetric oper-
ation is analyzed. A 50 Hz PWM signal is used to supply the power switches, and the value of duty cycle is
D = 0.5. A BUP 306D IGBT power switch with anti parallel diode (1200 V, 23 A) from Siemens was used as
the power transistor in the multilevel inverter circuit. In order to make the circuit operates in high performance,
this power switch is optimized for low switching losses and high-speed operating. The proposed topology is
simulated for 15-level inverter and 31-level inverter, respectively.
4.1. 15-level multilevel inverter
To generate appropriate switching Pulse Width Modulation schemes for the power switches, the circuit
in Figure 4 is used. The fundamental frequency is utilized to generate the switching pulses in the circuit.
According to the switching states, the pulses are generated at each step to drive the power switches as shown in
Figure 5. If the pulses form accurately, the efficiency and harmonic distortion can be controlled effectively in
the proposed multilevel inverter. The switches of H-bridge are operated in a complementary mode to produce
the positive and the negative levels steps output voltage at the load. The inverter provides the AC signal with
a peak magnitude 312 V to the load, when the dc voltage source is 45 V. In order to observe the step voltage
waveform at the output resistor, the zoomed waveform of the output voltage for the multilevel inverter is shown
in Figure 6. It can be seen that the step size of the waveform is 45 V. The step level of the inverter was captured
in Figure 7. It is clear that the output voltage is close to sine waveform. The presented approach proves that the
new inverter provides low-voltage stress and small-valued components.
Int J Pow Elec Dri Syst, Vol. 11, No. 4, December 2020 : 1883 – 1889

5. Int J Pow Elec Dri Syst ISSN: 2088-8694 r 1887
Figure 5. Simulated 15-level switching pulse waveforms of multilevel inverter
Figure 6. Simulated of 15-level zoomed output voltage waveform
Figure 7. Simulated of 15-level multilevel inverter waveform
4.2. 31-level multilevel inverter
The proposed topology can be utilized for 31-level to generate AC waveform close to sine signal.
The power switches of 31-level circuit are derived by the control circuit to form switching pulses as shown in
Figure 8. The output voltage waveform in Figure 9 shows the operation of 31-level of the proposed topology. It
is clearly shows that the operation of the circuit is obtained by the level generation and change polarity circuit
to supply the AC signal to the load. The maximum value of the voltage stress was measured as 312 V for the
input voltage V = 20 V. The peak-to-peak output voltage of the multilevel inverter across the load is varied
from +185 to -185. It can be noticed that the output voltage is close to sine waveform.
A high-performance multilevel inverter with reduced power electronic devices (Amer Chlaihawi)

6. 1888 r ISSN: 2088-8694
Figure 8. Simulated 31-level switching pulse waveforms of multilevel inverter
Figure 9. Simulated 31-level multilevel inverter waveform.
5. CONCLUSION
A new switched-mode multilevel inverter, which is derived from conventional multilevel inverter, has
been introduced. This topology operates at constant duty cycle and frequency. The new topology can be
designed for 15-level and 31-level inverter. An H-bridge is added in the proposed topology to generate negative
voltage levels. It has a low number of power switches, low switch voltage stress, low DC voltage sources, and
flexible design. The new circuit is designed to supply AC signal to the load even when low-input voltage of
the inverter is available. Based on above analysis, the prototype with 50 Hz was designed and simulated. The
simulation testing results demonstrate a good agreement between the simulations and the calculations. The
proposed circuit can be used in applications that demand high performance, such as FACTS controllers and
adjustable motor drives.
REFERENCES
[1] G. Ceglia, et al., “A New Simplified Multilevel Inverter Topology for DC–AC Conversion,” IEEE Trans-
actions on Power Electronics, vol. 21, no. 5, pp. 1311-1319, Sep. 2006.
[2] A. Chlaihawi, et al., “Novel Screen Printed and Flexible Low Frequency Magneto-Electric Energy Har-
vester,” IEEE Sensors, 2016, pp. 1-3.
Int J Pow Elec Dri Syst, Vol. 11, No. 4, December 2020 : 1883 – 1889

7. Int J Pow Elec Dri Syst ISSN: 2088-8694 r 1889
[3] A. Al-Modaffer, A. Chlaihawi and H. Wahhab, “Non-Isolated Multiple Input Multilevel Output DC-
DC Converter for Hybrid Power System,” Indonesian Journal of Electrical Engineering and Computer
Science, vol. 19, no. 2, pp. 635-643, 2020.
[4] S. Kjaer, J. Pedersen, and F. Blaabjerg, “A Review of Single-Phase Grid-Connected Inverters for Photo-
voltaic Modules,” IEEE Transactions on Industry Applications, vol. 41, no. 5, Oct. 2005.
[5] Y. H. Liao, et al., “Newly-Constructed Simplified Single-Phase Multistring Multilevel Inverter Topology
for Distributed Energy Resources,” IEEE Trans. on Power Elect., vol. 26, pp. 2386-2392, 2011.
[6] A. Chaithanakulwat, “Track The Maximum Power of a Photovoltaic to Control a Cascade Five-Level
Inverter a Single-Phase Grid-Connected with a Fuzzy Logic Control,” International Journal of Power
Electronics and Drive System, vol. 10, no. 4, pp. 1863-1874, 2019.
[7] D. Cobaleda, et al., “Low-Voltage Cascade Multilevel Inverter with GaN Devices for Energy Storage
System,” IEEE International Conference on Power Electronics and Drive Systems, pp. 1-5, 2019.
[8] N. Prabaharan, A. Fathima, and K. Palanisamy, “New Hybrid Multilevel Inverter with Reduced Switch
Count Using Carrier Based Pulse Width Modulation Technique,” IEEE Energy Conversion Conference,
pp. 176-180, 2015.
[9] Y. Babkrani , A. Naddami and M. Hilal, “A Smart Cascaded H-bridge Multilevel Inverter with an Opti-
mized Modulation Techniques Increasing the Quality and Reducing Harmonics,” International Journal of
Power Electronics and Drive System, vol. 10, no. 4, pp. 1852-1862, 2019.
[10] C. Barth et al., “Design and Control of a GaN-based, 13-Level, Flying Capacitor Multilevel Inverter,”
IEEE Journal of Emerging and Selected Topics in Power Electronics, 2019.
[11] A Sawan and Aspalli, “Cascaded Multilevel Inverter Topology with Reduced number of Switches,” Inter-
national Journal Science and Research, vol. 6, no. 5, pp. 1309-1327, Sep. 2017.
[12] A. Chlaihawi, “Genetic Algorithm Error Criteria as Applied to PID Controller DC-DC Buck Converter
Parameters: an Investigation,” Materials Sci. and Engine. Conf., vol. 671, pp. 1-10, 2009.
[13] B. Xiao, et al., “Modular Cascaded H-bridge Multilevel PV Inverter with Distributed MPPT for Grid-
Connected Applications,” IEEE Trans. on Industry App., vol 51, no. 2, pp. 1722-1731, 2015.
[14] J. Rodriguez, et al., “Multilevel Converters: an Enabling Technology for High-Power Applications,”
Proceedings of IEEE, vol. 97, no. 11, pp. 1786-1817, 2009.
[15] C. Rech and J. Pinheiro, “Hybrid multilevel converters: unified analysis and design considerations,” IEEE
Transaction on Industrial Electronics, vol. 54, no. 2, pp. 1092-1104, Apr. 2007.
[16] E. Najafi, and A. Yatim, “Design and Implementation of a New Multilevel Inverter Topology,” IEEE
Transactions on Industrial Electronics, vol. 59, no. 11, pp. 4148-4154, Nov. 2012.
[17] N. Prabaharan and K. Palanisamy. “A Comprehensive Review on Reduced Switch Multilevel Inverter
Topologies, Modulation Techniques and Applications,” Renew. and Sustain. Energy Reviews, vol. 76, pp.
1248-1282, 2017.
[18] N. Rahim, K. Chaniago, and J. Selvaraj, “Single-Phase Seven-Grid-Connected Inverter for Photovoltaic
System,” IEEE Transactions on Industrial Electronics, vol. 58, no. 6, pp. 2435-2443, Jun. 2011.
[19] J. Ebrahimi, E. Babaei, and G. Gharehpetian, “A New Multilevel Converter Topology with Reduced
Number of Power Electronic Components,” IEEE Transactions on Industrial Electronics, vol. 59, no. 2,
pp. 655-667, Feb. 2012.
[20] J. Rodriguez, J. Lai, and F. Peng, “Multilevel Inverters: Survey of Topologies, Controls, and Applica-
tions,” IEEE Trans. Industrial App., vol. 49, no. 4, pp. 724-738, Aug. 2002.
[21] M. Malinowski, et al., “A Survey on Cascaded Multilevel Inverters,” IEEE Transactions on Industrial
Electronics, vol. 57, no. 7, pp. 2197–2206, Jul. 2010.
[22] Y. Liu, H. Hong, and A. Q. Huang, “Real-Time Algorithm for Minimizing THD in Multilevel Inverters
with Unequal or Varying Voltage Steps Under Staircase Modulation,” IEEE Transactions on Industrial
Electronics, vol. 56, no. 6, pp. 2249–2258, Jun. 2009.
[23] J. Rodriguez, et al., “A New Modulation Method to Reduce Common Mode Voltages in Multilevel In-
verters,” IEEE Transactions on Industrial Electronics, vol. 51, no. 10, pp. 834–839, Aug. 2004.
[24] A. Ajami, et al., “Developed Cascaded Multilevel Inverter Topology to Minimize the Number of Circuit
Devices and Voltage Stresses of Switches,” IET Power Electronics, vol. 7, no. 2, pp. 459-466, 2014.
[25] E. Babaei, “A Cascade Multilevel Converter Topology with Reduced Number of Switches,” IEEE Trans-
actions on Power Electronics, vol. 23, no. 6, Nov. 2008.
A high-performance multilevel inverter with reduced power electronic devices (Amer Chlaihawi)