IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC ...IAEME Publication
The primary motivation of the work presented in this paper is to significantly reduce power consumption in pipe lined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longer battery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipe lined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipe lined ADC have been designed in Cadence environment and simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Power Efficiency Improvement in CE-OFDM System With 0 dB IBO for Transmission...CSCJournals
Orthogonal frequency division multiplexing (OFDM) OFDM has been adopted for high speed data transmission of multimedia traffic such as HomePlug A/V and Mobile WiMax. However, OFDM also has a drawback of a high PAPR (peak-to-average-power-ratio). Due to this high PAPR amplifier usually does not act in dynamic range. One potential solution for reducing the peak-to-average power ratio (PAPR) in an OFDM system is to utilize a constant envelope OFDM (CE-OFDM) system. Furthermore, by utilizing continuous phase modulation (CPM) in a CE-OFDM system, the PAPR can be effectively reduced to 0 dB, allowing for the signal to be amplified with a power efficient non-linear power amplifier with Input Back-Off (IBO) of 0 dB. This paper describes a CE-OFDM based modem for Power Line Communications (PLC) over the low voltage distribution network. Relying on a preliminary characterization of a PLC network, a complete description of the modem is given. Also CE-OFDM is compared with conventional OFDM under HomePlug 1.0 in the presence of power amplifier nonlinearities, considering different values of IBO.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOSIDES Editor
This paper presents 1-bit full adder cell in emerging
technologies like FinFET and CNFET that operates in the
moderate inversion region for energy efficiency, robustness
and higher performance. The performance of the adder is
improved by the optimum selection of important process
parameters like oxide and fin thickness in FinFET and number
of carbon nanotubes, chirality vector and pitch in CNFET.
The optimized CNFET-based full adder (OP-CNFET) has
higher speed, lower PDP (power-delay product) and lower
power dissipation as compared to the MOSFET and FinFET
full adder cells. The OP-CNFET design also offers tight spread
in power, delay and PDP variability against process, voltage
and temperature variations. All the evaluations have been
carried out using HSPICE simulations based on 32 nm BPTM
(Berkeley Predictive Technology Model).
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture VLSICS Design
A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC) using a novel mirror telescopic operational amplifiers (opamp) with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved.
A High Accuracy, Low Power, Reproducible Temperature Telemetry Systemijsrd.com
Sense amplifiers are extensively used in memory. Sense amplifiers are one of the most vital circuits in the periphery of CMOS memories. We know that memory is the heart of all digital systems. Today all worlds are demanding high speed and low power dissipation as well as small area. We know that speed and power dissipation of memory is overall depends upon the sense amplifier we used and their performance strongly affects both memory access time, and overall memory power dissipation. So it is important to design a good sense amplifier which performs well in both speed and power dissipation. In this dissertation, an implementation of a most efficient sense amplifier is done by comparing the best known sense amplifier in today. The dissertation focuses on design, simulation and performance analysis of sense amplifiers. In this thesis, current latch sense amplifier and body bias controlled current latch sense amplifier are designed and results compared. The result shows that the body bias controlled current latch sense amplifier is performing best. The result also shows a novel sense amplifier which consumes small power at same time its speed is faster than other sense amplifiers.
Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at D...IDES Editor
In this work, the analysis and simulation work is
proposed for the low-power (reduced subthreshold leakage)
and high performance SRAM bit-cells for mobile multimedia
applications in deep-sub-micron (DSM) CMOS technology.
The sub-threshold leakage analysis of the P3 SRAM cell has
been carried out. It has been observed that due to pMOS
stacking and full supply body-biasing, there is a reduction of
70% and 86% in sub-threshold leakage current at VDD=0.8V
and VDD=0.7V respectively as compared to conventional 6T
SRAM cell. Due to this a reduction in the standby power has
been achieved w.r.t the 6T and PP SRAM design at a bearable
expense of the SVNM and the WTV.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Effect of Combustion Air Pre-Heating In Carbon Monoxide Emission in Diesel Fi...IJERA Editor
This paper describes the effect of combustion air pre- heating in Diesel fired heat Treatment Furnace. The main
heat treatment processes are Normalizing, Tempering, Hardening, Annealing, Solution Annealing and Stress
Relieving. The emission of carbon monoxide is measured with combustion air pre-heating and without preheating.
The results are then compared and it is found that the emission of CO is reduced by 29.12%. With the
Combustion air pre-heating a considerable reduction in Specific Furnace Fuel Consumption (SFFC) is obtained.
The test was caaried out at Peekay Steels Casting (P) ltd, Nallalam, Calicut.
General Terms: Heat Treatment Furnace
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC ...IAEME Publication
The primary motivation of the work presented in this paper is to significantly reduce power consumption in pipe lined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longer battery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipe lined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipe lined ADC have been designed in Cadence environment and simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Power Efficiency Improvement in CE-OFDM System With 0 dB IBO for Transmission...CSCJournals
Orthogonal frequency division multiplexing (OFDM) OFDM has been adopted for high speed data transmission of multimedia traffic such as HomePlug A/V and Mobile WiMax. However, OFDM also has a drawback of a high PAPR (peak-to-average-power-ratio). Due to this high PAPR amplifier usually does not act in dynamic range. One potential solution for reducing the peak-to-average power ratio (PAPR) in an OFDM system is to utilize a constant envelope OFDM (CE-OFDM) system. Furthermore, by utilizing continuous phase modulation (CPM) in a CE-OFDM system, the PAPR can be effectively reduced to 0 dB, allowing for the signal to be amplified with a power efficient non-linear power amplifier with Input Back-Off (IBO) of 0 dB. This paper describes a CE-OFDM based modem for Power Line Communications (PLC) over the low voltage distribution network. Relying on a preliminary characterization of a PLC network, a complete description of the modem is given. Also CE-OFDM is compared with conventional OFDM under HomePlug 1.0 in the presence of power amplifier nonlinearities, considering different values of IBO.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOSIDES Editor
This paper presents 1-bit full adder cell in emerging
technologies like FinFET and CNFET that operates in the
moderate inversion region for energy efficiency, robustness
and higher performance. The performance of the adder is
improved by the optimum selection of important process
parameters like oxide and fin thickness in FinFET and number
of carbon nanotubes, chirality vector and pitch in CNFET.
The optimized CNFET-based full adder (OP-CNFET) has
higher speed, lower PDP (power-delay product) and lower
power dissipation as compared to the MOSFET and FinFET
full adder cells. The OP-CNFET design also offers tight spread
in power, delay and PDP variability against process, voltage
and temperature variations. All the evaluations have been
carried out using HSPICE simulations based on 32 nm BPTM
(Berkeley Predictive Technology Model).
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture VLSICS Design
A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC) using a novel mirror telescopic operational amplifiers (opamp) with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved.
A High Accuracy, Low Power, Reproducible Temperature Telemetry Systemijsrd.com
Sense amplifiers are extensively used in memory. Sense amplifiers are one of the most vital circuits in the periphery of CMOS memories. We know that memory is the heart of all digital systems. Today all worlds are demanding high speed and low power dissipation as well as small area. We know that speed and power dissipation of memory is overall depends upon the sense amplifier we used and their performance strongly affects both memory access time, and overall memory power dissipation. So it is important to design a good sense amplifier which performs well in both speed and power dissipation. In this dissertation, an implementation of a most efficient sense amplifier is done by comparing the best known sense amplifier in today. The dissertation focuses on design, simulation and performance analysis of sense amplifiers. In this thesis, current latch sense amplifier and body bias controlled current latch sense amplifier are designed and results compared. The result shows that the body bias controlled current latch sense amplifier is performing best. The result also shows a novel sense amplifier which consumes small power at same time its speed is faster than other sense amplifiers.
Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at D...IDES Editor
In this work, the analysis and simulation work is
proposed for the low-power (reduced subthreshold leakage)
and high performance SRAM bit-cells for mobile multimedia
applications in deep-sub-micron (DSM) CMOS technology.
The sub-threshold leakage analysis of the P3 SRAM cell has
been carried out. It has been observed that due to pMOS
stacking and full supply body-biasing, there is a reduction of
70% and 86% in sub-threshold leakage current at VDD=0.8V
and VDD=0.7V respectively as compared to conventional 6T
SRAM cell. Due to this a reduction in the standby power has
been achieved w.r.t the 6T and PP SRAM design at a bearable
expense of the SVNM and the WTV.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Effect of Combustion Air Pre-Heating In Carbon Monoxide Emission in Diesel Fi...IJERA Editor
This paper describes the effect of combustion air pre- heating in Diesel fired heat Treatment Furnace. The main
heat treatment processes are Normalizing, Tempering, Hardening, Annealing, Solution Annealing and Stress
Relieving. The emission of carbon monoxide is measured with combustion air pre-heating and without preheating.
The results are then compared and it is found that the emission of CO is reduced by 29.12%. With the
Combustion air pre-heating a considerable reduction in Specific Furnace Fuel Consumption (SFFC) is obtained.
The test was caaried out at Peekay Steels Casting (P) ltd, Nallalam, Calicut.
General Terms: Heat Treatment Furnace
Study Utility Vehicle Makassar City Transport a High- ErgonomicsIJERA Editor
The development of technology during this was to meet the man, but it should be men must be spoilt, But if it
turns out that all that did not make people feel safe, comfortable, healthy and easy, but the planning process,
decision-making and developments have experienced a deviation orientation. Public transport Transportation in
the Makassar city should be made with implementing aspects promotes ergonomic comfort, but it does not apply
in means of transportation to the public. Issues for public vehicles on access up and down not in accordance
with The aim of the research vehicle users. is to phrases dimensions body which have an effect on to utility
vehicle, to examine the public vehicles that high-promotes ergonomic comfort. The method assessment is the
measurement dimensions body to the passengers as well as the use questionnaires and analyzed in a holistic
approach ergonomics. Results of research high security tools to public vehicles that high-security vehicle users
generally by body dimensions as a powerful than Knee-and-a-half was knee, long your feet, and your elbow
kelantai. While utilities yangbernilai ergonomics was the first and second around 24.76 cm and 49.53 cm, wide
around 24.25 cm and was hangar 104, 78 cm.
A Combined Approach for Feature Subset Selection and Size Reduction for High ...IJERA Editor
selection of relevant feature from a given set of feature is one of the important issues in the field of
data mining as well as classification. In general the dataset may contain a number of features however it is not
necessary that the whole set features are important for particular analysis of decision making because the
features may share the common information‟s and can also be completely irrelevant to the undergoing
processing. This generally happen because of improper selection of features during the dataset formation or
because of improper information availability about the observed system. However in both cases the data will
contain the features that will just increase the processing burden which may ultimately cause the improper
outcome when used for analysis. Because of these reasons some kind of methods are required to detect and
remove these features hence in this paper we are presenting an efficient approach for not just removing the
unimportant features but also the size of complete dataset size. The proposed algorithm utilizes the information
theory to detect the information gain from each feature and minimum span tree to group the similar features
with that the fuzzy c-means clustering is used to remove the similar entries from the dataset. Finally the
algorithm is tested with SVM classifier using 35 publicly available real-world high-dimensional dataset and the
results shows that the presented algorithm not only reduces the feature set and data lengths but also improves the
performances of the classifier.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This paper presents the design and performance comparison of a two stage
operational amplifier topology using CMOS and BiCMOS technology. This conventional op
amp circuit was designed by using RF model of BSIM3V3 in 0.6 μm CMOS technology and
0.35 μm BiCMOS technology. Both the op amp circuits were designed and simulated,
analyzed and performance parameters are compared. The performance parameters such as
gain, phase margin, CMRR, PSRR, power consumption etc achieved are compared. Finally,
we conclude the suitability of CMOS technology over BiCMOS technology for low power
RF design.
An Optimized Device Sizing of Two-Stage CMOS OP-AMP Using Multi-Objective Gen...ijcisjournal
A novel approach for optimizing the transistor dimensions of two stage CMOS op-amp using MultiObjective
Genetic Algorithm (MOGA) is presented. The proposed approach is used to find the optimal
dimensions of each transistor to improve op-amp performances for analog and mixed signal integrated
circuit design. The aim is to automatically determine the device sizes to meet the given performance
specifications while minimizing the cost function such as power dissipation and a weighted sum of the
active area. This strongly suggests that the approach is capable of determining the globally optimal
solutions to the problem. Exactness of performance prediction in the device sizing program (implemented
in MATLAB) maintained. Here Six parameters are considered i.e., open loop gain, Phase Margin (PM),
Area (A), Bandwidth of unity Gain (UGB), Power Consumption (P) and Slew Rate (SR). The circuit is
simulated in cadence(Virtuoso Spectre) 0.18um CMOS technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Performance Analysis of Encoder in Different Logic Techniques for High-Speed ...Achintya Kumar
In designing a system, we can replace cell components by appropriate technique based cell so that the noise margin of overall circuit is improved. In future we can also implement some techniques for sequential circuits.
Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADCAman JanGra
The analog-to-digital converter (ADC) is an essential part of systemon-
chip (SoC) products because it bridges the gap between the analog physical
world and the digital logical world. In the digital domain, low power and low
voltage requirements are becoming more important issues as the channel length
of MOSFET shrinks below 0.25 sub-micron values. SoC trends force ADCs to
be integrated on the chip with other digital circuits. These trends present new
challenges in ADC circuit design. This paper investigates high speed, low
power, and low voltage CMOS flash ADCs for SoC applications.
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational
transconductance amplifier (OTA) is one of the most important components of ADC. This paper presents a
new design of two stages OTA. The design incorporates Sleep insertion technique and leakage feedback current
approach for improving design parameters such as gain, and power as compared to earlier work. The design is
simulated in 0.18µm CMOS technology with supply voltage 1.8V.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
Review on Design and Performance Analysis of Low Power Transceiver Circuit in...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
A power efficient delta-sigma ADC with series-bilinear switch capacitor volta...TELKOMNIKA JOURNAL
In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
1. Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.647-654
Design of Two-Stage CMOS Op-Amp and Analyze the Effect of
Scaling
Amana Yadav
Department of Electronics and Communication Engineering, FET-MRIU, Faridabad, Haryana
Abstract:-
A method described in this paper is to worldwide sales is dominated by MOS market. CMOS
design a Two Stage CMOS operational amplifier technology continues to mature with minimum feature
and analyze the effect of various aspect ratios on sizes now. Designing high performance analog
the characteristics of this Op-Amp, which operates integrated circuits is becoming increasingly exigent
at 5V power supply using tsmc 0.35µm CMOS with the relentless trend toward reduced supply
technology. In this paper trade-off curves are voltages and transistor channel length. A large part of
computed between all characteristics such as Gain, the success of the MOS transistor is due to the fact that
PM, GBW, ICMRR, CMRR, Slew Rate etc. The it can be scaled to increasingly smaller dimensions,
OPAMP designed is a two-stage CMOS OPAMP. which results in higher performance. The feature size
The OPAMP is designed to exhibit a unity gain of individual transistor is shrinking from deep sum-
frequency of 14MHz and exhibits a gain of 77.25dB micrometer (DSM) to even nanometer region. As the
with a 85.850 phase margin. Design has been scale of integration improves, more transistors, faster
carried out in Mentor graphics tools. Simulation and smaller than their predecessors, are being packed
results are verified using Model Sim Eldo and into a chip. This leads to the steady growth of the
Design Architect IC. operating frequency and processing capacity per chip.
The task of CMOS operational amplifiers (Op-
Amps) design optimization is investigated in this Operational Amplifier is the most common
work. This Paper focused on the optimization of building blocks of most of the electronics system may
various aspect ratios, which gave the result of not need introduction. The design of OPAMPs
different parameter. When this task is analyzed as continues to pose a challenge as the supply voltage
a search problem, it can be translated into a multi- and transistor channel lengths scale down with each
objective optimization application in which various generation of CMOS technologies. At different aspect
Op-Amps’ specifications have to be taken into ratio, there is a tradeoff among speed, power, gain and
account, i.e., Gain, GBW (gain-bandwidth other performance parameters. The realization of a
product), phase margin and others. The results are CMOS OPAMP that combines a considerable dc gain
compared with respect to standard characteristics with high unity gain frequency has been a difficult
of the op-amp with the help of graph and table. problem. There have been several circuit approaches
Simulation results agree with theoretical to evade this problem.
predictions. Simulations confirm that the settling
time can be further improved by increasing the The aim of the design methodology in this
value of GBW, the settling time is achieved 19ns, paper is to propose straightforward yet accurate
gain is 77.25dB and a value of phase margin is equations for the design of high-gain 2 staged CMOS
73.30. It has been demonstrated that when W/L op-amp. To do this, a simple analysis with some
increases the parameters GBW increases and meaningful parameters (phase margin, gain-
settling time reduces. bandwidth, etc.) is performed. The method handles a
very wide variety of specifications and constraints. In
Keywords this paper, we formulate the CMOS op-amp design
CMOS Analog Circuit, 2 stage CM OS problem and their aspect ratios. The method we
Operational amplifier, Stability, GBW, Device Design, present can be applied to a wide variety of amplifier
Scale Length, Scaling, Differential Amp. architectures, but in this paper we apply the method to
a specific two stage CMOS op-amp. The variation in
I. Introduction the performance of the op-amp with variations in the
Over the last few years, the electronics width and length of the CMOS and the effect of
industry has exploded. The largest segment of total scaling the gate oxide thickness is discussed.
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The simulation results have been obtained by
tsmc 0.35 micron CMOS technology. Design has been
carried out in Mentor Graphics tool. Simulation results
are verified using Model Sim Eldo and Design
Architect IC. Scaling effects are analyzed through
experimental data and computer simulations. This
search technique can be successfully applied to a class
of optimization problems. After the simulation, most
of the transistors’ size still needed to be modified in
order to optimize the performance. High gain in
operational amplifiers is not the only desired figure of
merit for all kind of signal processing applications.
Simultaneously optimizing all parameters has become
mandatory now a day in operational amplifier design.
Figure 1. Block diagram of Op-Amp
In this case, the slew rate will increase for an
increase in current. However, if the widths of the The first block is a differential amplifier. It
devices are increased with the bias voltages held has two inputs which are the inverting and non-
constant. Thus, we can conclude that the selection of inverting voltage. It provides at the output a
device sizes depends on trade-offs between stability differential voltage or a differential current that,
(phase margin) and slew-rate. essentially, depends on the differential input only. The
As such, for the fastest slew-rate, the smallest channel next block is a differential to single-ended converter. It
length (350 nm) will be used, and at this length, the is used to transform the differential signal generated
device is in the short channel regime and will require by the first block into a single ended version. Some
short channel topologies. architecture doesn’t require the differential to single
ended function; therefore the block can be excluded.
Outline of paper In most cases the gain provided by the input stages is
This paper composed this work. Section II not sufficient and additional amplification is required.
discusses the 2 stage amplifier and design This is provided by intermediate stage, which is
optimization. Section III reviews the 2 stage CMOS another differential amplifier, driven by the output of
Op-amp schematic design. Its specifications are briefly the first stage. As this stage uses differential input
clarified, also gives the formula or calculation for unbalanced output differential amplifier, so it provide
designing of 2 stage CMOS Op-amp. Section IV required extra gain. The bias circuit is provided to
presents the simulation results of the proposed op- establish the proper operating point for each transistor
amp, tables and graphs for optimization technique. in its saturation region. Finally, we have the output
Section V gives the scaling and finally section VI buffer stage. It provides the low output impedance and
concludes this work. larger output current needed to drive the load of op-
amp or improves the slew rate of the op –amp. Even
II. Block diagram of two stage CMOS op-amp the output stage can be dropped: many integrated
Operational Amplifiers are the backbone for applications do not need low output impedance;
many analog circuit designs. Op-Amps are one of the moreover, the slew rate permitted by the gain stage
basic and important circuits which have a wide can be sufficient for the application. If the op-amp is
application in several analog circuit such as switched intended to drive a small purely capacitive load, which
capacitor filters, algorithmic, pipelined and sigma is the case in many switched capacitor or data
delta A/D converter, sample and hold amplifier etc. conversion applications, the output buffer is not used.
The speed and accuracy of these circuits depends on When the output stage is not used the circuit, it is an
the bandwidth and DC gain of the Op-amp. Larger the operational transconductance amplifier, OTA. The
bandwidth and gain, higher the speed and accuracy of purpose of the compensation circuit is lower the gain
the amplifier Op-amp are a critical element in analog at high frequencies and to maintain stability when
sampled data circuit, such as SC filters, modulators. negative feedback is applied to the op amp.
The general block diagram of an op-amp with an
output buffer is shown below
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A. Circuit Operation subtracted from the current from M2. The differential
The final circuit designed to meet the current from M1 and M2 multiplied by the output
required specifications is shown in Figure 2. The resistance of the first stage gives the single-ended
topology of this circuit is that of a standard CMOS op- output voltage, which constitutes the input of the
amp. It comprised of three subsections of second gain stage.
C. Second Gain Stage
The second stage is a current sink load
inverter. The purpose of the second gain stage, as the
name implies, is to provide additional gain in the
amplifier. Consisting of transistors M5 and M6, this
stage takes the output from the drain of M2 and
amplifies it through M5 which is in the standard
common source configuration. Again, similar to the
differential gain stage, this stage employs an active
device, M6, to serve as the load resistance for M5. The
gain of this stage is the transconductance of M5 times
the effective load resistance comprised of the output
resistances of M5 and M6. M6 is the driver while M7
acts as the load.
D. Bias String
Figure2. The topology chosen for this Op-Amp design.
The biasing of the operational amplifier is
circuit, namely differential gain stage, second gain achieved with only four transistors. Transistors M8
stage and bias strings. It was found that this topology and M9 form a simple current mirror bias string that
was able to successfully meet all of the design supplies a voltage between the gate and source of M7
specifications. and M6. Transistors M6 and M7 sink a certain amount
of current based on their gate to source voltage which
B. Differential Gain Stage is controlled by the bias string. M8 and M9 are diode
Transistors M1, M2, M3, and M4 form the connected to ensure they operate in the saturation
first stage of the op amp the differential amplifier with region. Proper biasing of the other transistors in the
differential to single ended transformation. Transistors circuit (M1-M5) is controlled by the node voltages
M1 and M2 are standard N channel MOSFET present in the circuit itself. Most importantly, M5 is
(NMOS) transistors which form the basic input stage biased by the gate to source voltage (VGS) set up by
of the amplifier. The gate of M1 is the inverting input the VGS of the current mirror load as are the
and the gate of M2 is the non-inverting input. A transistors M1 and M2.
differential input signal applied across the two input
terminals will be amplified according to the gain of the III. Design of the op-amp
differential stage. The gain of the stage is simply the The first aspect considered in the design was
transconductance of M2 times the total output the specifications to be met. They appear in Table 1
resistance seen at the drain of M2. The two main
resistances that contribute to the output resistance are Table1. Custom Design Specifications of the amplifier
that of the input transistors themselves and also the
output resistance of the active load transistors, M3 and Specification Names Values
M4. The current mirror active load used in this circuit Supply VDD 5V
has three distinct advantages. First, the use of active Gain ≥ 70dB
load devices creates a large output resistance in a Gain Bandwidth 10MHz
relatively small amount of die area. The current mirror Settling Time 1u Sec
topology performs the differential to single-ended Slew Rate 10V/uSec
conversion of the input signal, and finally, the load Input common Mode Range 1.5 – 2.8V
also helps with common mode rejection ratio. In this Common mode rejection ratio ≥60dB
stage, the conversion from differential to single ended Output Swing 1 – 2.8V
is achieved by using a current mirror (M3 and M4). Offset ≤10m
The current from M1 is mirrored by M3 and M4 and
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A. Design Methodology of Op-amp and for the circuit analysis in Model Sim Eldo of
Mentor Graphic Tool.Schematic used in this design is
3.1.1 Determine the necessary open-loop gain (Ao)
gm1 = gm2 = gmI, gm6 = gmII, gds2 + gds4 = GI, and gds6 +
gds7 = GII
𝑊
𝜇 𝑛 ,𝑝 𝐶𝑜𝑥 𝑉𝑒𝑓𝑓 2
𝐿
𝐼𝑑 = 2
(1)
𝑊
gm = 2𝜇 𝑛,𝑝 𝐶𝑜𝑥 𝐼𝑑 (2)
𝐿
𝐼𝑑
gm = 2 𝑉 𝑒𝑓𝑓
(3)
𝐼5
Slew rate 𝑆𝑅 = 𝐶𝐶
(4)
−𝑔𝑚 1 −2𝑔𝑚 1
First stage gain 𝐴 𝑣1 = = (5)
𝑔𝑑𝑠 2 +𝑔𝑑𝑠 4 𝐼5 (𝜆 2 + 𝜆 4 )
−𝑔𝑚 6
Second stage gain 𝐴 𝑣2 = =
𝑔𝑑𝑠 6 +𝑔𝑑𝑠 7
−𝑔𝑚 6
(6)
𝐼6 (𝜆 6 + 𝜆 7 )
Figure 3. Schematic design of 2 stage CMOS Op-
𝑔𝑚 1
Gain Bandwidth GB = (7) Amp
𝐶𝐶
−𝑔𝑚 6 Open Loop Gain: It is the ratio between output
Output pole 𝑝2= (8)
𝐶𝐿 voltage and differential input voltage. Because the
𝑔𝑚 6 output signal is much larger than the input signal, so it
RHP zero 𝑍1= (9) is commonly called as large signal voltage gain.
𝐶𝐶
𝐼5 Slew Rate: The maximum rate of change of output
Positive CMR 𝑉𝑖𝑛 (max) = 𝑉 𝐷𝐷 − − voltage per unit time. (dVo/dt) The slope of the output
𝛽3
𝑉 𝑇𝑂3 (max) + VT1 (min) (10) signal is the slew rate.
𝐼5 Rise Time: the time required by the output to go from
Negative CMR 𝑉𝑖𝑛 (min) = 𝑉𝑆𝑆 + + 10% to 90% of its final value is called the rise time.
𝛽1
𝑉 𝑇1 (max) + VDS 5 (sat) (11)
CMRR: Common Mode Rejection ratio is the ratio
2𝐼 𝐷𝑆 between differential gain and common mode gain.
Saturation voltage 𝑉 𝐷𝑆 (sat) = (12)
𝛽
IV. Simulation results
It is assumed that all transistors are in saturation for To analyze the behavior of variations in
the above relationships. aspect ratios, first discuss the results of basic design of
two stage CMOS Op-amp
The design in this project is a two-stage op amp with
an n-channel input pair. The op amp uses a dual- A. AC Analysis
polarity power supply (Vdd and Vss) so the ac signals In AC- Analysis we determine Phase margin, Gain
can swing above and below ground and also be and GB of the OP-Amp.
centered at ground. The hand calculation results Start frequency = 1Hz
provided the estimated parameters (such as transistor Stop frequency = 10 MHz
width and length, capacitance, etc.) to make the circuit
schematic (shown in figure 3) in Design Architect IC
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Figure 6. Result of Slew Rate
Figure 4. Output of AC Analysis
The slew rate achieved in this design is 10.32 V/µs.
Figure 5. Result of CMRR
Figure 7. Result of ICMR
Output: The output results of AC analysis is as follows
Gain = 77.249 dB ω-3db = 1.3 KHz
Phase margin = 85.850 ωUGB = 14.1MHz
CMRR = 80.985 dB
B. Transient Analysis
The non inverting terminal is connected to a
pulse with a rise and fall time equal to 1n sec (0.1us)
and a pulse width of 384.61us. The value of pulse
period is 769.23us. This analysis helps to determine
the slew rate of the op-amp.
Figure 8. Output Swing
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Consider all W/L of reference circuit as (W/L)1 and f
Positive Slew Rate = 10.328V/us is a multiplication factor.
Settling Time = 0.4 us (W/L)n = f * (W/L)1
Negative Slew Rate = 9.40V/us
ICMR = 0.9 – 3.237 V A. By Reducing L:
Output Swing = 0.0 - 3.28V
Table 3. Values of various parameters after reducing
V. Scaling value of L
Proportional adjustment of the dimensions of Results f =1 f = 2, f = 3, f= 4, L
an electronic device while maintaining the electrical
L=L1/2 L=L1/3 = L1/4
properties of the device, results in a device either
larger or smaller than the un-scaled device is called Gain (dB) 77.24 69.36 58.9 47.53
scaling. Scaling allows people to build more complex
machines that run faster too and it does let you design
PM 53.460 59.960 65.570 73.30
more modules.
Impact of scaling is characterized in terms of several
ω -3dB (KHz ) 1.3 4.12 15.2 63.275
indicators:
Minimum feature size
ωUGB (MHz ) 8.6 11.35 12.86 14.853
Number of gates on one chip
Power dissipation
Maximum operational frequency CMRR (dB) 80.985 78 67.29 53.49
Production cost
ICMR (V) 0.9 – 0.812 – 0.75 – 0.93 –
Implications of Scaling 3.23 3.245 3.224 3.13
1. Improved Performance Slew Rate 10.347, 10.931, 13.742, 26.078,
2. Improved Cost (V/µs) -9.527 -9.18 -9 -10.25
3. Interconnect Woes
4. Power Woes
5. Productivity Challenges Settling 0.4 0.347 0.304 0.0192
6. Physical Limits Time ( µs)
Reference Circuit L = 1.4 um Output 0.0 – 0.0 – 0.0 – 0.0 –
Swing (V) 3.28 3.287 3.282 3.253
Table 2. Values of W of reference circuit
Name Values
W1, W2 12
W3, W4 23
W5, W8 20
W6 195
W7 90
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B. By increasing W:
Table 4. Values of various parameters after
increasing value of W
Results f =1 f = 2, f = 3, f= 4,W
W=2W1 W=3W1 =4W1
Gain (dB) 77.24 78.165 78.38 78.417
PM 53.460 47.970 43.360 40.050
ω -3dB (KHz ) 1.3 1.47 1.58 1.654
ω UGB ( MHz) 8.6 10.37 11.05 11.258
CMRR(dB) 80.985 85.56 87.993 89.56
ICMR(V) 0.9 –3.23 0.8 – 3.258 0.76 – 0.73 –3.27
3.266 Figure 10.Variations in Parameters with increasing W
Slew Rate 10.347, 10.469, 10.494, 10.49, - VI. Conclusion
(V/µs) -9.527 -8.68 -8.873 8.82 This paper presented the full custom design of a two
stage CMOS Op-Amp and analyzed its behavior for
Settling 0.4 µs 0.383 µs 0.4 µs 0.36 µs various aspect ratios. Design technique for this Op-
Time Amp, its calculations and computer-aided simulation
results are given in detail. The results show that the
Output 0.0 –3.28 0.0 – 3.297 0.0 – 0.0 -3.295 designed amplifier has successfully satisfied all the
Swing (V) 3.285 specifications given in advance. Tables and graphs of
different parameters for various aspect ratios are
drawn.
Graph: Graph shows the variations in different
parameter of Op-Amp with various aspect ratios. As a summary, a tables and graphs are provided to
estimates the scaling limits for various applications
and device types. The end result is that there is no
single end point for scaling, but that instead there are
many end points, each optimally adapted to its
particular applications.
VII. Acknowledgements
With a deep sense of gratitude, I wish to
express my sincere thanks to Dr. S C Bose, Scientist
E2 (CEERI Pilani) for his helpful discussion. Also
wish to acknowledge the IC Design Group of CEERI,
Pilani for their inspiration and heartfelt support.
Figure 9.Variations in Parameters with reducing L
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