This document summarizes a research paper that aims to enhance the memory performance of silicon nitride-based charge trapping memory devices. The researchers propose a SONOS memory device structure with aluminum oxide as the blocking oxide and titanium oxide as the capping layers (STANOS). Simulations show that the STANOS structure provides better programming and erasing speeds as well as longer data retention times compared to a standard SONOS structure. The high dielectric constants of the aluminum oxide and titanium oxide layers help suppress carrier injection and tunneling leakage currents, improving the memory performance and reliability of the proposed STANOS device.

1. Enhanching memory performance in silicon
nitride-based charge trapping memory
device with Al2O3 blocking oxide and TiO2
capping layers
The 4th IEEE International Conference on
Telecommunications and Photonics (ICTP) 2021
December 22-24, 2021, Dhaka, Bangladesh
Authors:
K. M. Sayem Bin Rahmotullah || Adnan Hosen || Sheikh Rashel
Al Ahmed
Department of Electrical, Electronic and Communication Engineering
Pabna University of Science and Technology
Pabna 6600, Bangladesh.

2. Outline
 SONOS – Non Volatile Memory Devices
 Introduction
 Objectives
 Device Architecture
 Simulation
 Results
 Conclusions
2

3. A non-volatile memory is a memory that
can hold its information without the need
for an external voltage supply. SONOS
structure refers the semiconductor-
oxide-nitride-oxide-semiconductor
layers.
3
SONOS – Non Volatile Memory Devices
To enhance the memory characteristics, many researchers have proposed
various structure of SONOS with some changes utilizing different high-k
dielectrics as blocking oxide, charge trapping layer, double top oxide layer,
double blocking oxide layer, double trapping layer which are given
 Better programming /erasing speed
 Better retention

4. 4
Introduction
 The memory performances such as programming and erasing speeds, and data retention
of the NVM devices with high-k materials can be enhanced significantly using
HfO2, Al2O3, ZrO2, HfSiO4, Ta2O5

5. 5
Objectives
To enhance the programming / erasing speed
and data retention with low-cost and low power
consumption using high-k dielectric materials

6. 6
Device Architecture
(a) Schematic diagram (a) Energy level diagram
Programmin
g
Erasin
g

7.  Device modeling using SILVACO TCAD
 Investigation of different ONO stack with
programming/erasing speed
 Device optimization
 Effects of thickness, gate voltages, and different
temperatures
7
Simulation
Materials K
(Dielectric
Constant)
Eg
(Energy Band
Gap)
CBO
(Conduction
Band Offset)
VBO
(Valance
Band Offset)
Al2O3 9 8 2.1 4.8
TiO2 86 3.5 0 2.4
Thickness Tunnel Oxide Nitride Oxide
Layer
Blocking Oxide Layer
SONOS 5nm 15nm 10nm
STANOS 5nm 15nm 6nm with 4nm Capping
layer
STANOS 3nm 12nm 6nm with 4nm Capping
layer

8. 8
Results (1)
Programming Speed
 STANOS provides better
performances

9. 9
Results (2)
Programming Speed

10. 10
Results (3)
Erasing Speed

11. 11
Results (4)
Retention performance

12. 12
Results (5)
Temperature performance

13. The main goal of the simulation work is to enhance the memory
performance of the proposed STANOS memory device. It is revealed
that Al2O3 having higher barrier height provides better blocking
ability. On the other hand, the capping layer fiercely suppresses the
carrier injection to enhance both the P/E characteristics. Since the
scaling up of the tunnel oxide layer has faced much problem, this
high-k capping layer may be the solution of the scaling problem. By
using the high-k capping layer of TiO2 tunneling leakage current
mitigates and gives the device reliability. Therefore, the proposed
STANOS structure shows the speeding performance as well as
retention characteristics.
13
Conclusions

14. That’s all here.
Thanks