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Printed Vacuum Electronics
(CNT – based)
6th
May 09
2
May 2009
Objective and PST know-how
Goal:
Demonstrate the feasibility of printed vacuum CNT-devices and assess the potential
integration of a vacuum electronics-based diode in printed electronics technology
Status:
• The emitting current is exponentially dependent on the gap between the cathode and the anode
• Interconnection scheme design to reduce the parasitic capacitance
• Miniaturization down to sub-µm scale to reduce the parasitic capacitive between the cathode
and the anode
• Cathode/anode materials chosen to have high thermal and electrical conductivity
• Growth at low temperature of high purity CNTs needed compatible with the substrate
PST Key Know-how
• To growth uniform and high quality CNTs @ low-temperature by PE/MW CVD on a plethora of
different substrates (from copper to poly-silicon and glass), done in DSI-Singapore
• To growth CNTs in holes patterned with down-to 100nm, in DSI
• 1st
demonstration of Vacuum diode with voltage threshold down to 15V, in DSI/NUS
• Nano-Imprint and moulds to pattern devices at the nanoscale, in PST Italy => allowing Printed
Vacuum Electronics
3
May 2009
Process flow – nanoscale printed diode/triodeProcess flow – nanoscale printed diode/triode
Substrate
Cathode
Substrate
Cathode
1. Deposition of cathode layer 4. Deposition of gate followed
by lift-off
5. Etching of the dielectric
6. Etching of protecting layer 7. CNT growth
11. Wafer to wafer bonding under
vacuum
2(a). NIL and deposition of the
catalyst followed by lift-off
2(b). FCVA deposition of catalyst
islands
3. Deposition and curing of the
above mentioned layers
Substrate
Cathode
Dielectric
Barrier
Substrate
Cathode
Dielectric
BarrierBarrier
Substrate
Cathode
Dielectric
Gate Gate
Barrier
Substrate
Cathode
Dielectric
Gate Gate
BarrierBarrier
Dielectric
Substrate
Cathode
Dielectric
Gate Gate
Barrier
Dielectric
Substrate
Cathode
Dielectric
Gate Gate
BarrierBarrier
Substrate
Cathode
Gate Gate
Barrier
Dielectric
Barrier
Dielectric
Substrate
Cathode
Gate Gate
Barrier
Dielectric
Barrier
Dielectric
Barrier
Dielectric
Barrier
Dielectric
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Cathode
Catalyst
Substrate
Anode
DielectricDielectric
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Gate Gate
Substrate
Anode
DielectricDielectric
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Gate Gate
Etch stop layer
12. Deep glass etching to reveal
area of anode, gate and cathode
for electrical testing
Substrate
Anode
DielectricDielectric
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Anode
DielectricDielectric
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Anode
DielectricDielectric
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Barrier
Dielectric
Barrier
Dielectric
Cathode
Gate Gate
Substrate
Anode
Substrate
Anode
8. Deposition of anode layer
Substrate
Anode
Dielectric
Gate Gate
Substrate
Anode
Dielectric
Gate Gate
9. Deposition of gate followed by
lift-off
10. Etching of dielectric
Substrate
Anode
DielectricDielectric
Gate Gate
Substrate
Anode
DielectricDielectric
Gate Gate
Substrate: SiO2 Barrier: Cr
Cathode: Ti Dielectric: SiO2
Catalyst: Co Gate, Anode: Gold
Top View
CNT height target: 1µm
Single device size:
1. 6µm by 6µm (4 emitters)
2. 3µm by 3µm (4 emitters)
3. 8µm by 8µm (9 emitters)
Cathode
Gate
Anode
Etch stop layer
Etch stop layer
Etch stop layer
Cathode
Gate
Anode
Etch stop layer
Etch stop layer
Etch stop layer
4
May 2009
Complete Mask design – Mold readyComplete Mask design – Mold ready
Process step 9: Gate pattern
for bonding
Process step 10: Via opening
pattern for bonding
Process step 2: NIL pattern
Process step 1and 8: Cathode/Anode
pattern
Process step 4: Gate pattern
(circular and square)
Process step 8: Anode pattern
(diode structure)
Process step 12: Electrode pad
opening pattern
Process step 5: Via etching pattern
(circular and square)
Process step 12: Electrode pad
opening pattern (diode structure)
Anode substrate
anode
cathode
5
May 2009
Raman Shift (cm-1
)
Metal on
substrate
Measured Rs Thickness (nm) Remarks
Cu / SiO2 ~150.9 mΩ/sq 100* E-beam evap
(Nanocluster)
Cu / Si ~182.6 mΩ/sq 100* E-beam evap
(Nanocluster)
Ti / SiO2 ~34.84 Ω/sq 60 E-beam evap
(Nanocluster)
Ti / Si ~43.6 mΩ/sq 60 E-beam evap
(Nanocluster)
Au / Ti /
SiO2
~1.79 Ω/sq 40 (Au)*
10 (Ti)*
E-beam evap
(Nanocluster)
AAO 20 nm cylindrical pores
CNTs grown from bottom penetrate the
pores
CNT FE vacuum Key Achievements (Q1 09)
• Demonstrated the ability to shorten CNTs in holes by using
oxygen plasma etching
• Studied the sheet resistance of different combinations of metals
for multilayer: electrode / barrier / catalyst
• First attempts of growth of CNTs in nano-porous AAO sheets are
encouraging for the fabrication of fully-printed diode devices
• Setup a characterization bench using Raman Spectroscopy to test
the quality of the grown CNTs
6
May 2009
CNT FE vacuum Key Achievements (Q1 09)
• Experimental growth parameters for good quality CNTs grown in
holes have been reached.
• First CNT field emission tests have started for the silicon platform
diode demonstrator.
• CNTs have successfully been grown on a metal electrode.
• Raman characterization of the CNTs is on-going and shows
improvements in grown CNT quality.
Well aligned, high quality
CNTs grown on a copper
electrode
Current density vs. applied electric field for a dense
CNT forest field emission
Raman spectroscopy of CNT grown
in holes
Vertically aligned CNTs in holesVertically aligned CNTs in holes
7
May 2009
CNT vacuum electronics @ NUS, Phy.
Dep.
Anode: Indium tin oxide (ITO) glass covered with conductive phosphor layer
Spacer: Transparency of thickness d =100 µm with hole (diameter ~0.55cm)
Cathode: Cu substrate
CNT on Cu: -2 µm length MWCNT grown on Cu using PECVD @ 350C
CNT vacuum e-gun
MWCNT
High Voltage Field emission
vacuum chamber
3×10−7
Torr
CNT Emitter on glass demonstrated
8
May 2009
Best result achieved
5000 A/cm2
9
May 2009
Printed CNT vacuum electronics – applications
General Applications (GHz – THz)
– Triodes, rectifiers, pentodes, tetrodes, microwave tubes
Printed Electronics (RFID, RF powered - SMART sensors)
– Quasi-vacuum rectification diode working on RF-field (13.56 MHz) with printed antenna
Other Possible Applications
– High voltage (power management)
– High speed (high performance consumer electronics)
– Low power & low dissipation (portable market)
– Energy Harvesting
9
May 2009
Printed CNT vacuum electronics – applications
General Applications (GHz – THz)
– Triodes, rectifiers, pentodes, tetrodes, microwave tubes
Printed Electronics (RFID, RF powered - SMART sensors)
– Quasi-vacuum rectification diode working on RF-field (13.56 MHz) with printed antenna
Other Possible Applications
– High voltage (power management)
– High speed (high performance consumer electronics)
– Low power & low dissipation (portable market)
– Energy Harvesting

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Cnt vacuum electronics 9 may 09

  • 1. Printed Vacuum Electronics (CNT – based) 6th May 09
  • 2. 2 May 2009 Objective and PST know-how Goal: Demonstrate the feasibility of printed vacuum CNT-devices and assess the potential integration of a vacuum electronics-based diode in printed electronics technology Status: • The emitting current is exponentially dependent on the gap between the cathode and the anode • Interconnection scheme design to reduce the parasitic capacitance • Miniaturization down to sub-µm scale to reduce the parasitic capacitive between the cathode and the anode • Cathode/anode materials chosen to have high thermal and electrical conductivity • Growth at low temperature of high purity CNTs needed compatible with the substrate PST Key Know-how • To growth uniform and high quality CNTs @ low-temperature by PE/MW CVD on a plethora of different substrates (from copper to poly-silicon and glass), done in DSI-Singapore • To growth CNTs in holes patterned with down-to 100nm, in DSI • 1st demonstration of Vacuum diode with voltage threshold down to 15V, in DSI/NUS • Nano-Imprint and moulds to pattern devices at the nanoscale, in PST Italy => allowing Printed Vacuum Electronics
  • 3. 3 May 2009 Process flow – nanoscale printed diode/triodeProcess flow – nanoscale printed diode/triode Substrate Cathode Substrate Cathode 1. Deposition of cathode layer 4. Deposition of gate followed by lift-off 5. Etching of the dielectric 6. Etching of protecting layer 7. CNT growth 11. Wafer to wafer bonding under vacuum 2(a). NIL and deposition of the catalyst followed by lift-off 2(b). FCVA deposition of catalyst islands 3. Deposition and curing of the above mentioned layers Substrate Cathode Dielectric Barrier Substrate Cathode Dielectric BarrierBarrier Substrate Cathode Dielectric Gate Gate Barrier Substrate Cathode Dielectric Gate Gate BarrierBarrier Dielectric Substrate Cathode Dielectric Gate Gate Barrier Dielectric Substrate Cathode Dielectric Gate Gate BarrierBarrier Substrate Cathode Gate Gate Barrier Dielectric Barrier Dielectric Substrate Cathode Gate Gate Barrier Dielectric Barrier Dielectric Barrier Dielectric Barrier Dielectric Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Cathode Catalyst Substrate Anode DielectricDielectric Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Gate Gate Substrate Anode DielectricDielectric Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Gate Gate Etch stop layer 12. Deep glass etching to reveal area of anode, gate and cathode for electrical testing Substrate Anode DielectricDielectric Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Anode DielectricDielectric Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Anode DielectricDielectric Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Barrier Dielectric Barrier Dielectric Cathode Gate Gate Substrate Anode Substrate Anode 8. Deposition of anode layer Substrate Anode Dielectric Gate Gate Substrate Anode Dielectric Gate Gate 9. Deposition of gate followed by lift-off 10. Etching of dielectric Substrate Anode DielectricDielectric Gate Gate Substrate Anode DielectricDielectric Gate Gate Substrate: SiO2 Barrier: Cr Cathode: Ti Dielectric: SiO2 Catalyst: Co Gate, Anode: Gold Top View CNT height target: 1µm Single device size: 1. 6µm by 6µm (4 emitters) 2. 3µm by 3µm (4 emitters) 3. 8µm by 8µm (9 emitters) Cathode Gate Anode Etch stop layer Etch stop layer Etch stop layer Cathode Gate Anode Etch stop layer Etch stop layer Etch stop layer
  • 4. 4 May 2009 Complete Mask design – Mold readyComplete Mask design – Mold ready Process step 9: Gate pattern for bonding Process step 10: Via opening pattern for bonding Process step 2: NIL pattern Process step 1and 8: Cathode/Anode pattern Process step 4: Gate pattern (circular and square) Process step 8: Anode pattern (diode structure) Process step 12: Electrode pad opening pattern Process step 5: Via etching pattern (circular and square) Process step 12: Electrode pad opening pattern (diode structure) Anode substrate anode cathode
  • 5. 5 May 2009 Raman Shift (cm-1 ) Metal on substrate Measured Rs Thickness (nm) Remarks Cu / SiO2 ~150.9 mΩ/sq 100* E-beam evap (Nanocluster) Cu / Si ~182.6 mΩ/sq 100* E-beam evap (Nanocluster) Ti / SiO2 ~34.84 Ω/sq 60 E-beam evap (Nanocluster) Ti / Si ~43.6 mΩ/sq 60 E-beam evap (Nanocluster) Au / Ti / SiO2 ~1.79 Ω/sq 40 (Au)* 10 (Ti)* E-beam evap (Nanocluster) AAO 20 nm cylindrical pores CNTs grown from bottom penetrate the pores CNT FE vacuum Key Achievements (Q1 09) • Demonstrated the ability to shorten CNTs in holes by using oxygen plasma etching • Studied the sheet resistance of different combinations of metals for multilayer: electrode / barrier / catalyst • First attempts of growth of CNTs in nano-porous AAO sheets are encouraging for the fabrication of fully-printed diode devices • Setup a characterization bench using Raman Spectroscopy to test the quality of the grown CNTs
  • 6. 6 May 2009 CNT FE vacuum Key Achievements (Q1 09) • Experimental growth parameters for good quality CNTs grown in holes have been reached. • First CNT field emission tests have started for the silicon platform diode demonstrator. • CNTs have successfully been grown on a metal electrode. • Raman characterization of the CNTs is on-going and shows improvements in grown CNT quality. Well aligned, high quality CNTs grown on a copper electrode Current density vs. applied electric field for a dense CNT forest field emission Raman spectroscopy of CNT grown in holes Vertically aligned CNTs in holesVertically aligned CNTs in holes
  • 7. 7 May 2009 CNT vacuum electronics @ NUS, Phy. Dep. Anode: Indium tin oxide (ITO) glass covered with conductive phosphor layer Spacer: Transparency of thickness d =100 µm with hole (diameter ~0.55cm) Cathode: Cu substrate CNT on Cu: -2 µm length MWCNT grown on Cu using PECVD @ 350C CNT vacuum e-gun MWCNT High Voltage Field emission vacuum chamber 3×10−7 Torr CNT Emitter on glass demonstrated
  • 8. 8 May 2009 Best result achieved 5000 A/cm2
  • 9. 9 May 2009 Printed CNT vacuum electronics – applications General Applications (GHz – THz) – Triodes, rectifiers, pentodes, tetrodes, microwave tubes Printed Electronics (RFID, RF powered - SMART sensors) – Quasi-vacuum rectification diode working on RF-field (13.56 MHz) with printed antenna Other Possible Applications – High voltage (power management) – High speed (high performance consumer electronics) – Low power & low dissipation (portable market) – Energy Harvesting
  • 10. 9 May 2009 Printed CNT vacuum electronics – applications General Applications (GHz – THz) – Triodes, rectifiers, pentodes, tetrodes, microwave tubes Printed Electronics (RFID, RF powered - SMART sensors) – Quasi-vacuum rectification diode working on RF-field (13.56 MHz) with printed antenna Other Possible Applications – High voltage (power management) – High speed (high performance consumer electronics) – Low power & low dissipation (portable market) – Energy Harvesting

Editor's Notes

  1. <number> 12/29/18