The document describes the design and simulation of a 2-input NOR gate in 0.25um CMOS technology. The goal is to minimize propagation delay and area. Various transistor widths and lengths are analyzed to determine the optimal sizing. Shared diffusion is used to reduce parasitic capacitance and area. The final design has a propagation delay of 0.65ns and passes DRC and LVS checks.

1. Mini Project-1
Lakshmi Yasaswi Kamireddy
651771619
Graduate Student
Problem Description:
The purpose of this project is to design and simulate a CMOS 2 input NOR gate in the standard 0.25u
CMOS technology. This project mainly focusses on minimizing the propagation delay and the area.
Design:
Any function implemented using static CMOS configuration has the structure as shown in Figure 1.The
pull up network consists of pmos and the pull down network consists of nmos. The transistors in both pull
up and pull down act as switch .So, if a transistor is on then it acts as a short circuit and if it is off it acts as
an open circuit. The connections of pmos and nmos are made in such a way that the functionality of the
function being implemented is met .Pull up network (PUN) is to make a rising transition i.e, from 0 to 1 or
to maintain a constant 1 at the output .When the pull up network is on it provides a path between ouput
and Vdd and hence an output Vdd which is considered as logic 1 is seen at the output. On the other hand
a pull down network (PDN) is to make a falling transition 1 to 0 or to maintain a 0 at the output .When the
pull down network is on it provides a path between the output and the ground and hence the output is
pulled down to ground and hence the voltage level 0 is seen at the output.
Figure 1 Figure 2
We know that the functionality of NOR gate is f=(A+B)’.To get a one at the output both A and B have to
be 0. So the pull up network should be on only if both the inputs are 0 i.e, the pmos in the PUN have to
be connected in series. When either A or B or both A,B are 1 the output goes to zero ,which means the
nmos in the PDN have to be connected in parallel combination. Figure 2 shows the basic CMOS
implementation.
After deciding how to connect the mosfets in the PDN and PUN it is straight forward implementation of
these transistors. But, one thing to notice is that we know that the mobility of holes is not as good as
compared to the electrons and hence there will be a difference in the resistance of the nmos and pmos.
That means there will be higher resistance in the pun than in pdn. This means that it takes longer for the
0 to reach 1 i.e the rise time will increase and hence the propagation delay. Generally, the resistance of

2. the pmos is considered to be 2 to 3 times that of the resistance of the nmos for a static inverter. When a
design of any functionality using CMOS implementation is made, the (W/L) value for each pmos and nmos
is calculated to make the propagation delay from low to high and high to low equal and also equivalent to
that of a static inverter. Using the equivalent inverter concept the sizing for nmos and pmos for the NOR
gate is calculated as below.
Worst case for PUN: Both the transistors are in series so (L/W)peq=(L/W)Ap+(L/W)Bp
Rpeq=Rpo/(W/L)peq
tpLH=0.69RpeqCL
Worst case for PDN: Any one transistor is on. (W/L)neq=(W/L)An or (W/L)Bn
Rneq=Rpno/(W/L)neq
tpHL=0.69RneqCL
Taking Rpo=2Rno
To make tpLH=tpHL
0.69Rn0CL=0.69(Rp0/2)CL
0.69RneqCL=0.69RpeqCL
Which implies Rpeq=Rp0/2=Rp0/(W/L)peq
So,(W/L)peq=2
(L/W)peq=(L/W)Ap+(L/W)Bp=1/2
Considering similar characteristic on the both the pmos we get
(L/W)Ap=(L/W)Bp=1/4
Which shows that (W/L)Ap=(W/L)Bp=4
Considering 0.69Rn0CL=0.69(Rp0/2)CL
0.69RneqCL=0.69RpeqCL
Rn0=Rneq=Rn0/(W/L)neq
Which implies that (W/L)neq=1
(W/L)neq=(W/L)An=(W/L)Bn=1

3. Figure 3
Considering Rp0=3Rn0 will give the (W/L) value of the pmos in the PUN equal to 6 and the nmos PDN will
have (W/L) as 1 itself.
One might think as tpLH and tpHL are inversely proportional to (W/L) having higher (W/L) will reduce the
them more. But it is not true because of the presence of parasitic capacitances at the drain and source
terminal. The gate terminal also has parasitic terminal but it has not effect in calculation of the
propagation delay. It only effects the total load capacitance if there is a fan out.If we have higher (W/L)
one disadvantage is the area will increase which not we desire as we want to minimize the area. So (W/L)
=6 is a good change (sacrificing area) only if it can create very significant effect on the delay. In the case
of NOR the propagation delay gets worse which can be shown as follows.
(W/L)=6 for pmos implies Resistance of the pmos =R/6 say R is resistance when the (W/L)=1.At the same
time the parasitic capacitances are proportional to the (W/L) value .The circuit with capacitance will be as
follows
(a)
CC
C
6C
6C
6C
6C
C
(W/L)=4
(W/L)=4
(W/L)=1 (W/L)=1
Drain capacitance of Ap=CdAp=6C
Source Capacitance of Ap=CsAp=6C
Drain Capacitance of Bp=CdBp=6C
Source Capacitance of Bp=CsBp=6C
Drain capacitance of An=CdAn=6C
Source Capacitance of An=CsAn=6C
Drain Capacitance of Bn=CdBn=6C
Source Capacitance of Bn=CsBn=6C
They are constantly
connected to Vdd or
ground so do not
contribute for the delay
as they always charged
or discharged

4. Equivalent circuit for tpLH in worst case is
(b)
Equivalent circuit for tpHL worst case
(c)
When the same analysis is made for (W/L)p =4 we get
(d)
Vdd
Vdd
tpLH=(R/6*12C)+((R/6+R/6)*8C)=14RC/3=4.66RC
6C+6C=12C
6C+C+C=8C
R/6
R/6
out
out
6C+C+C=8CR
tpHL=8RC
4C+4C=8C
4C+C+C=6C
R/4
R/4
out
tpLH=(R/4*8C)+((R/4+R/4)*6C)=5R
C
tpHL=6RC

5. (e)
Figure 4
So we see that though there is reduction in tpLH when the sizing (W/L)Ap=6,(W/L)Bp =6 ,(W/L)An=1,
(W/L)Bn=1 ,but tpHL increases more than the decrease as compared to (W/L)Ap=4, (W/L)Bp=4, (W/L)An=1,
(W/L)Bn=1. So, it is not a good decision to take the former sizing because it is disadvantageous in terms of
both area and delay.
It can also be seen that though it is made sure that the tpHL and tpLH are equal whie calculating the sizing
it is not true and will have a difference due the existence of these capacitances.
From the above discussion it can be decided that (W/L)p=4 and (W/L)n=1 .
Using this sizing a schematic is designed taking Wn=Ln=250nm(least possible channel length in the 0.25u
CMOS technology) and Wp=1000nm Lp=250nm.
Before proceeding to layout if a rough draft of the layout as shown in Figure 5 is taken a look at it can be
observed that in the pun the drain of first transistor and the source of the second transistor can be
combined and use a shared diffusion instead of two diffusions. Even in the pdn we use shared diffusion
for the two sources of the nmos connected with the output.
This has two advantages one is the reduction in area .The second is the used of shared diffusion helps in
reducing the parasitic capacitance .This is because when a diffusion is shared instead of two capacitances
(one for each terminal) we have only one capacitance and hence the propagation delay decreases as
compared to the isolated diffusion design .A rough picture of shared diffusion design is as shown in Figure
6.
Calculating the tpHL with shared diffusion tpHL=(R/4*4C)+(R/4+R/4)*5C=3.5RC.
Calculating the tpLH with shared diffusion tpLH=5RC.
This shows that designing the layout in this way is very efficient. To get the minimum possible area the
DRC rules are keenly followed.
Initially the gate length of nmos and pmos is taken as 250nm(5lambda) .But when an ActX region is placed
it has a design rule that it has to be mimimum of 10lambdaX10lambda .And it has to be covered on all
sides with atleast 5lambda.So this makes the minimum width of active region for nmos as
20lambda(10lambda+5lambda+5lambda).So the minimum channel length can be 20 lambda as (W/L)n=1.
Now as the length of gate is 20 lambda ,width of the pmos will be 80lambda (4x20) as (W/L)p=4.
Finally with these measurements the layout is designed following every possible minimal space that satisfy
the design rules .Once the layout is made the DRC check has been performed with 0 errors. Then pins are
created and LVS is checked with the schematic(that has been modified for the length and width obtained
from layout) and the extracted cell view.
out
4C+C+C=6CR

6. Figure 5
Then the LVS was checked for the test schematic and the extracted layout. Once this is done post layout
simulation is performed on the test schematic using the analog_extracted(with capacitances) and
schematic(without capacitances) in the config file as done in Lab4.
out
Vdd
gnd
B
A

7. Figure 6
gnd
Vdd
A B
out

8. Schematic:
With (W/L)=1 for both nmos and pmos –Bad design
With the (W/L)p=2 and (W/L)n=1 – tpHL and tpLH are not equal

9. Final Schematic along with changes from layout
Test schematic with the given vdd=2 and load capacitance as 10fF

10. Layout of 2 i/p NOR with shared diffusion capacitance to reduce area.
Extracted view

11. Results:
DRC check for layout
LVS check for with extracted and schematic
LVS check for schematic od test circuit and extracted

12. Parasitic capacitances
Output for the bad design W/L=1 for both nmos and pmos. The worst case propagation delay is 16.2-
15.14=1.08ns.
Initial nor –with L= 250nm and (W/L)n=1 (W/L)p=2 The worst case propagation delay is 0.51ns

13. Output for new nor implementation with L=1um and (W/L)n=1 ,(W/L)p=4.The worst case propagation
delay is 15.83-15.3=0.53ns.
Output with parasitic cpacitances .Propagation delay is 0.65ns

14. Conclusions:
The two input NOR gate is implemented successfully to reduce propagation delay and area. The
propagation delay reduced from 1.08ns to 0.53ns .The area minimization was obtained by using shared
diffusion and following Design rules carefully to optimize the area of the layout. The design passed LVS
and DRC successfully. The parasitic capacitances were also calculated using the Build Analog option. The
design showed an increase in propagation delay from 0.53ns to 0.65ns when simulated with parasitic
capacitances.