this ppt is about the Design of 101 sequence detector without overlapping for mealy FSM and Perform cost analysis

1. Department of Electrical & Electronics Engineering
Raghu Engineering College (Autonomous)
CASE STUDY
ON
DIGITAL ELECTRONICS
BACHELOR OF TECHNOLOGY
IN
ELECTRICAL AND ELECTRONICS ENGINEERING
Under the Supervision of
Mr.D. Bhaskar Rao
ASST.PROFESSER
Mr P.Eswar sai 18981A0237
Mr P.Mohan 18981A0238
Ms P.Supriya 18981A0239
Mr.P.Nithesh kumar 18981A0240
Mr.P.Sanjay Kumar 18981A0241
By
Head of the department
Dr.P.SASI KIRAN
Professor

2. CASE STUDY ON
• Design of 101 sequence detector without overlapping for mealy FSM
and Perform cost analysis

3. WHAT IS A SEQUENCE DETECTOR?
• sequence detector is a sequential state machine which takes an input
string of bits and generates an output 1 whenever the target
sequence has been detected.In a Mealy machine, output depends on
the present state and the external input (x). Hence in the diagram,
the output is written outside the states, along with inputs.

4. • Sequence detector is of two types:
1.Overlapping
2. Non-Overlapping
• In an overlapping sequence detector the last bit of one
sequence becomes the first bit of next sequence.However,
in non-overlapping sequence detector the last bit of one
sequence does not become the first bit of next sequence.In
this post, we’ll discuss the design procedure for non-
overlapping 101 Mealy sequence detector. Examples:
• For non overlapping case:
Input :0110101011001
Output:0000100010000
• For overlapping case
Input :0110101011001

5. MEALY FSM BLOCK DIAGRAM

6. STEP 1 : DEVELOP THE STATE DIAGRAM:-
• The state diagram of a Mealy machine for a 101 sequence
detector is:

7. STEP 2: CODE ASSIGNMENT:-
Rule 1 : States having the same next states for a given
input condition should have adjacent assignments.
Rule 2:States that are the next states to a single state must
be given adjacent assignments.
Rule 1 given preference over Rule 2.

8. • The state diagram after the code assignment is:

9. STEP 3: MAKE PRESENT STATE/ NEXT STATE
TABLE-
• We’ll use D-Flip Flops for design purpose.

10. STEP 4: DRAW K-MAPS FOR Dx, Dy AND
OUTPUT (Z) –

11. STEP 5: FINALLY IMPLEMENT THE CIRCUIT-

12. THE COST ANALYSIS OF A IC’S IS :-
• Cost Evaluation for Fully Customized ASICs The ideal 3-D
fabrication gives the freedom that transistors can be built on
their optimal layers.
• In this case, we first use our early design estimation
methodology and the proposed cost model to demonstrate how
the cost of fully customized AS ICs can be reduced by 3-D
fabrication.
• In this section, we use the IBM common platform foundry cost
model as an example to perform a series of analysis for logic
circuitry

13. COST OF ICS WITH DIFFERENT NUMBER OF MANUFACTURING
COMPANIES

14. THE SCHEME OF A COST-DRIVEN FOR IC DESIGN FLOW

15. THE COST OF A DIFFERENT IC’S :-

16. THE COST OF A DIFFERENT IC’S :-
Number of the ic description cost
7400 Quad two-input AND gate (four
AND gates)
22/-
7402 Quad two-input AND gate (four
AND gates)
45/-
7432 Quad two-input AND gate (four
AND gates)
13/-
4077 Quad two-input AND gate (four
NAND gates)
15/-
4081 Quad two-input XNOR gate
(four XNOR gates)
16/-
4011 Quad two-input XOR gate (four
XOR gates)
21/-

17. Cost analysis for nand gate
s.no Ic name company Cost per ic
1 DM74LS00 SHEIJKEY 21 /-
2 SN74HC00N CLOUDAILINDIA 25/-
3 7400IC JRE”S 22.5 /-
4 IC74AHCT00 SUN ROBOTICS 14.9/-
5 74VHC00N SHEIJKEY 27.8/-
6 74HC10N SHEIJKEY 23.5 /-
7 7410 IC DESTIAY REASERCH 47.5 /-
8 MC7400BCP REE52 49.9 /-
9 TF CHIN CD7400BE NAMEVIDHI WORLD DC PVT,LT 39.96
10 INVENTO 7400IC INVENTO SALES 29.9

18. Cost analysis for and gate
s.no Ic name company Cost per ic
1 TC7402HCAP SHEIJKEY 31/-
2 7402IC GURU ELECTRONICS 12/-
3 74S02QUAD SUN ROBOTIC 39.8/-
4 CD74001BE INVENTO SCALS 28/-
5 74LS02QUADE ROBOMART GURU ELECTRONICS 20/-
6 IC 7402 TECHNICAL HUT 33.8/-
7 7402 IC HOBBYTRONIC 23.8/-
8 CD400BEDIPIMOS AK ELECTRONIC 47/-
9 CD4078 8 INPUT NOR CHIPS N BOARDS 20/-
10 TISN74LSO2I GURU ELECTRONICS 49/-

19. • To overcome the barriers in technology scaling,3D ic’s is emerging as an attractive option for
future ic design.
• However fabrication cost is one of the important consideration for a wide adoption.
• To facilitate the system level cost analysis ,we study the design estimation method at the ear4ly
design stage and propose a cost analysis.
• Based on the cost analysis we design the circuits with ic’s.
CONCLUSION :