Design of very large scale analog integrated circuit (analog VLSI) is very much complex and requires
much compromising nature to achieve application specific objective. With maximizing the efforts to reduce
power consumption and to reduce W/L ratio, the analog integrated circuit industry is constantly
developing smaller power supplies. Now days, challenges of analog integrated circuit designer are to
make block of small power supplies with little or no reduction in performance. The CMOS OTA is
designed in 25.5nm CMOS technology with 1.0V power supply to observe the configurations. In design of
CMOS OTA TANNER EDA TOOL is used. Coding and simulation is done in T-Spice and layout is
prepared in L-Edit. D.C analysis, A.C analysis, slew rate and analysis of transient response have been
done in T-Spice. Waveforms are observed in W-Edit.
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
DIFFERENTIAL AMPLIFIER using MOSFET, Modes of operation,
The MOS differential pair with a common-mode input voltage ,Common mode rejection,gain, advantages and disadvantages.
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
DIFFERENTIAL AMPLIFIER using MOSFET, Modes of operation,
The MOS differential pair with a common-mode input voltage ,Common mode rejection,gain, advantages and disadvantages.
Report contains digital and analog design flow procedures in detail, working, Simulation and Synthesize mapped output. Full custom Schematic and layout design by using virtuoso encounter cadence tool.
Describes ARM7-TDMI Processor Instruction Set. Explains classes of ARM7 instructions, syntax of data processing instructions, branch instructions, load-store instructions, coprocessor instructions, thumb state instructions.
Introduction to Real-Time Operating Systemscoolmirza143
shared by Mansoor Mirza
Understanding Real-Time Operating Systems
Types of Real-Time Operating System
Requirements for Real-Time Operating System
Difference between General Purpose Operating System (GPOS) and Real-Time Operating System (RTOS)
Conversion Linux kernel to support Real-Time operations
Patching the linux kernel
Major changes in patched kernel
Hands-on labs
Conversion of Linux kernel to support real time
Code a real time application (Audio Feedback removal)
Defined instruction set architecture, discussed different types of instructions in the MIPS architecture, e.g., arithmetic, logical, shift etc. Discussed different types of registers in MIPS, R-format, I-format and j-format instructions have been explained with examples. Further assembly language code for conditional operations e.g., if..else, swap operation, loop operation are demonstrated.
Audio Version available in YouTube Link : www.youtube.com/Aksharam
subscribe the channel
Computer Architecture and Organization
V semester
Anna University
By
Babu M, Assistant Professor
Department of ECE
RMK College of Engineering and Technology
Chennai
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
In this project, we compare the working of the four 8- bit multipliers like Wallace tree multiplier, Array multiplier, Baugh-Wooley multiplier and Vedic multiplier by simulating each of them separately. This is a very important criterion because in the fabrication of chips and the high-performance system requires components which are as small as possible.
If you any doubts regarding project.......then to a mail(saikiranpanjala@gmail.com)
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Report contains digital and analog design flow procedures in detail, working, Simulation and Synthesize mapped output. Full custom Schematic and layout design by using virtuoso encounter cadence tool.
Describes ARM7-TDMI Processor Instruction Set. Explains classes of ARM7 instructions, syntax of data processing instructions, branch instructions, load-store instructions, coprocessor instructions, thumb state instructions.
Introduction to Real-Time Operating Systemscoolmirza143
shared by Mansoor Mirza
Understanding Real-Time Operating Systems
Types of Real-Time Operating System
Requirements for Real-Time Operating System
Difference between General Purpose Operating System (GPOS) and Real-Time Operating System (RTOS)
Conversion Linux kernel to support Real-Time operations
Patching the linux kernel
Major changes in patched kernel
Hands-on labs
Conversion of Linux kernel to support real time
Code a real time application (Audio Feedback removal)
Defined instruction set architecture, discussed different types of instructions in the MIPS architecture, e.g., arithmetic, logical, shift etc. Discussed different types of registers in MIPS, R-format, I-format and j-format instructions have been explained with examples. Further assembly language code for conditional operations e.g., if..else, swap operation, loop operation are demonstrated.
Audio Version available in YouTube Link : www.youtube.com/Aksharam
subscribe the channel
Computer Architecture and Organization
V semester
Anna University
By
Babu M, Assistant Professor
Department of ECE
RMK College of Engineering and Technology
Chennai
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
In this project, we compare the working of the four 8- bit multipliers like Wallace tree multiplier, Array multiplier, Baugh-Wooley multiplier and Vedic multiplier by simulating each of them separately. This is a very important criterion because in the fabrication of chips and the high-performance system requires components which are as small as possible.
If you any doubts regarding project.......then to a mail(saikiranpanjala@gmail.com)
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC ...IAEME Publication
The primary motivation of the work presented in this paper is to significantly reduce power consumption in pipe lined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longer battery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipe lined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipe lined ADC have been designed in Cadence environment and simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...VLSICS Design
A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach IJERA Editor
Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.
AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM ...VLSICS Design
This paper present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211miliwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
GridMate - End to end testing is a critical piece to ensure quality and avoid...ThomasParaiso2
End to end testing is a critical piece to ensure quality and avoid regressions. In this session, we share our journey building an E2E testing pipeline for GridMate components (LWC and Aura) using Cypress, JSForce, FakerJS…
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
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Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
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- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
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Generative AI Deep Dive: Advancing from Proof of Concept to Production
Design and simulation of cmos ota
1. International Journal of Managing Public Sector Information and Communication Technologies (IJMPICT)
Vol. 5, No. 2, June 2014
DOI : 10.5121/ijmpict.2014.5202 11
DESIGN AND SIMULATION OF CMOS OTA
WITH 1.0 V, 55db GAIN & 5PF LOAD
Dhaval Modi1
and Jayesh Patel2
1
Department of Electronics & Communication Engineering, G.P. PALANPUR,
Gujarat, India
2
Department of Electronics & Communication Engineering, G.P. PALANPUR,
Gujarat, India
ABSTRACT
Design of very large scale analog integrated circuit (analog VLSI) is very much complex and requires
much compromising nature to achieve application specific objective. With maximizing the efforts to reduce
power consumption and to reduce W/L ratio, the analog integrated circuit industry is constantly
developing smaller power supplies. Now days, challenges of analog integrated circuit designer are to
make block of small power supplies with little or no reduction in performance. The CMOS OTA is
designed in 25.5nm CMOS technology with 1.0V power supply to observe the configurations. In design of
CMOS OTA TANNER EDA TOOL is used. Coding and simulation is done in T-Spice and layout is
prepared in L-Edit. D.C analysis, A.C analysis, slew rate and analysis of transient response have been
done in T-Spice. Waveforms are observed in W-Edit.
KEYWORDS
DRC, Net list, Slew Rate, Transconductance Amplifier
1. INTRODUCTION
The importance of analog circuits using low supply voltage is enormously increasing in last
decades. Especially large component densities demands lower power consumption [2]
. The power
consumption can be minimized either by reducing the supply voltage or gate oxide thickness
(Tox). If Tox is reduced, tolerance of the CMOS device for high gate voltage is also reduced.
Therefore reasonable method for minimizing power consumption is to reduce power supply.
CMOS elements are useful building blocks for the design of many analog and analog-digital
signal processing systems. Two important characteristics of CMOS devices are high noise
immunity and low static power consumption. Because of these characteristics, the vast majority
of modern integrated circuit manufacturing is on CMOS processes.
Operational Transconductance Amplifiers are important building block in many analog
systems. These analog systems often require low power, fast settling time and high
dynamic range. The CMOS Operational Transconductance Amplifier (OTA) is a unique
device with characteristics particularly suited to applications viz. multiplexing,
amplitude modulation, analog multiplication, gain control, switching circuitry and
comparators.
2. International Journal of Managing Public Sector Information and Communication Technologies (IJMPICT)
Vol. 5, No. 2, June 2014
12
2. DESIGN OF OTA
2.1. Low voltage and low power amplifier design
In low-voltage design, the main consideration is to maintain the output swing as higher as
possible. This can be achieved when no cascading transistors can be used in the output stage. For
minimum power consumption, the number of current branches should be minimized. So the
current mirror amplifier is best suited for low-power low-voltage amplifier [1]
.
2.2. Current Mirror Amplifier
The circuit in which output current is forced to equal the input current is said to be a current
mirror circuit. It is special case of constant current bias. An advantage of current mirror circuits
is that it takes fewer components, simple to design and easy to fabricate.
2.3. Parameter require for designing CMOS OTA
1) Slew rate
2) Common-mode input range (ICMR)
3) Common-mode rejection ratio (CMRR)
4) Power supply rejection ratio (PSRR)
5) Voltage Gain
2.4. Design Specification
Vdd = -Vss = 1.0 V, SR ≥ 10V/µs, CL=5pF, a small signal differential voltage gain of 55db,
-1.5≤ ICMR ≤ 2V and Pdiss ≤ 1mW
Figure 1. Design of CMOS OTA
2.5 MATLAB Code for extraction of designing parameter
Vdd = input ('enter the value of Vdd = ');
SR = input ('enter the value of slew rate SR =');
CL = input ('enter the value of slew rate CL=');
3. International Journal of Managing Public Sector Information and Communication Technologies (IJMPICT)
Vol. 5, No. 2, June 2014
13
I5 = SR*CL
Pdiss = input ('enter the value of power diss. Pdiss');
Vss = input ('enter the value of Vss = -Vdd =');
........................................
........................................
Yn = input ('enter the value of Yn =');
Yp = input ('enter the value of Yp =');
.......................................
Rout = 2/((Yn + Yp)*I5);
Vin = input ('enter the value of Vin = ');
.....................................
Vsg3 = Vdd - Vin + Vtn
Kp = input ('enter the value of Kp = ');
Kn = input ('enter the value of Kn = ');
W3/L3 = I5 / (Kp*(Vsg3-0.7)*(Vsg3-0.7))
Av = input ('enter the value of Av = ');
W1/L1 = ((Av)^2*(Yn+Yp)^2*I5/2)/(2*Kn);
Vgs = sqrt((I5/Kn* W1/L1))+0.7;
Vds5 = Vin-Vss-Vgs;
W5/L5 = sqrt((2*I5)/Kn*(Vds5)^2);
3. LAYOUT AND VERIFICATION CONSIDERATION
Layout should be verified with design rule viz. Design Rule Check (DRC) and Layout Versus
Schematic (LVS).
Figure 2. Layout of CMOS OTA in 25.5nm
4. International Journal of Managing Public Sector Information and Communication Technologies (IJMPICT)
Vol. 5, No. 2, June 2014
14
3.1 Layout Versus Schematic (LVS) Summary (Extracted code from layout)
2 1 C=5.0147962p
* C7 PLUS MINUS (49.5 -45 91 -11.5)
M6 5 3 4 11 NMOS L=2n W= 56n AD=45.25p PD=28n AS=21p PS=14n
* M6 DRAIN GATE SOURCE BULK (23 -73.5 25 -70.5)
M5 4 3 3 11 NMOS L=2n W=56n AD=21p PD=14n AS=45.25p PS=28n
* M5 DRAIN GATE SOURCE BULK (13 -73.5 15 -70.5)
M4 6 10 5 11 NMOS L=2n W=58n AD=222p PD=86n AS=111p PS=43n
* M4 DRAIN GATE SOURCE BULK (30 -48.5 32 -11.5)
M3 5 9 7 11 NMOS L=2n W=58n AD=111p PD=43n AS=222p PS=86n
* M3 DRAIN GATE SOURCE BULK (22 -48.5 24 -11.5)
M2 3 7 7 8 PMOS L=2n W=51n AD=48p PD=22n AS=96p PS=44n
* M2 DRAIN GATE SOURCE BULK (22 5 24 21)
M1 6 7 3 8 PMOS L=2n W=51n AD=96p PD=44n AS=48p PS=22n
* M1 DRAIN GATE SOURCE BULK (30 5 32 21)
* Total Nodes: 11
* Total Elements: 7
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
.END
Table 1. Summary of transistors in figure 1
Sr.No
Transistor
Variable
W(n) L(n) W/L ratio
1 W1/L1 51 2 25.5
2 W2/L2 51 2 25.5
3 W3/L3 58 2 29
4 W4/L4 58 2 29
5 W5/L5 56 2 28
6 W6/L6 56 2 28
4. SIMULATION RESULT
4.1. Simulation in T-spice
T-Spice Pro is part of a complete integrated circuit design tool suite for layout, verification and
simulation offered by Tanner EDA.
1) T-Spice: Analog / digital circuit simulator
2) W-Edit: Waveform viewer
AC Analysis
Perform AC analysis to characterize the circuit’s dependence on small-signal input frequency.
.ac {lin|oct|dec} num start stop [sweep info] [analysis name=name]
DC Analysis
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Perform DC transfer analysis to study the voltage or current at one set of points in a circuit as a
function of the voltage or current at another set of points.
.dc info [sweep] info [sweep] info
4.2. Different Types of Simulation
4.2.1. DC characteristic
.DC VID -2.5V 2.5V 0.5V
.TF V(5) VID
.PRINT DC V(5)
.END
Figure 3. DC Characteristic of CMOS OTA
4.2.2. Slew Rate
VIN2 1 0 PWL (0,-3V 10US,-3V 10.505US, 3V 25US, 3V 25.505US,-3V 1S,-3V)
VIN1 2 0 PWL (0,-3V 10US,-3V 10.505US, 3V 25US, 3V 25.505US,-3V 1S,-3V)
.TRAN .1NS 40US
.PRINT V (5) V (1)
.PROBE
.END
From waveform of slew rate = (10-(-10))/.5µs = 40 V/µs
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Figure 4. Slew Rate Analysis
4.2.3. AC characteristic
.AC DEC 5 0.1HZ 1MegHZ
.TF V(5) VID
.PRINT AC V(5) VP(5) VID
.PROBE
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Figure 5. AC Characteristic of CMOS OTA
5. FUTURE WORK
The OTA layout con be further optimized to take up less space and also to get better symmetry.
We will make layout of viz. Telescopic, Folded-Cascode and Two-stage CMOS OTA. We will
compare their characteristics like gain, Speed, Power, Noise and Swing [1]
.
6. APPLICATIONS
IC CA3080A
IC CA3080A is especially suited for many low frequencies, low-power four-quadrant multiplier
applications. The basic multiplier circuit is particularly useful for waveform generation, double
balanced modulation, and other signal processing applications, where low-power consumption is
essential and accuracy requirements are moderate. We can make the astable multi vibrator,
monostable multi vibrator and peak detector [11].
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IC OPA2662
It is dual, wide band Operational Transconductance Amplifier. The OPA2662 is a versatile driver
device for ultra wide-band systems, including high-resolution video, RF and IF circuitry,
communications and test equipment [11]
.
CMOS OTA is used in following application like,
1) LED and LASER diode driver
2) High current video buffer or line driver
3) RF output stage driver
4) High density disk drives
7. CONCLUSION
Simulations show the output is reliable up to about 10MHz, which is sufficient to find the 3dB
bandwidth of the OTA. Structure of CMOS OTA is simple and is used as compare to ordinary
op-amp because its output is a current. We can retrieve information about gain margin and phase
margin. According to that we can retrieve information about pole and stability of the design.
ACKNOWLEDGEMENT
Author would like to thanks his head of electronics and communication department for providing
facilities and co-author for their continuous support, help and encouragement for this research
work.
REFERENCES
[1] CMOS Analog Circuit Design By Phillip E. Allen and Doiglas R. Holberg
[2] Design of Fully Different CMOS Amplifier For Cliping Amplifier By Behnam Karmani
[3] Operational Transcondunce Amplifier By WikiSource
[4] S.S. Rajput and S.S. Jamuar, “Low Voltage Analog Circuit Design Techniques,” IEEE Circuits and
Systems Magazine, vol. 2, no. 1, pp. 24-42, First Quarter, 2002.
[5] M. Steyaert, V. Peluso, J. Bastos, P. Kinget, W. Sansen, K. U. Leuven, “Custom Analog Low Power
Design: The Problem of Low Voltage and Mismatch,” IEEE 1997 Custom Integrated Circuits
Conference, pp. 285-292.
[6] S. Chatterjee, Y. Tsivides, P. Kinget, “0.5-V Analog Circuit Techniques and Their Application in
OTA and Filter Design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2373-2387,
December 2005.
[7] S. Chatterjee, Y. Tsivides, P. Kinget, “A 0.5-V Bulk-Input Fully Differential Operational
Transconductance Amplifier,”
[8] Shankar, J. Silva-Martinez, E. Sanchez-Sinencio, “A Low Voltage Operational Transconductance
Amplifier using Common Mode Feedforward for High Frequency Switched Capacitor Circuits,” IEEE
International Symposium on Circuits and Systems, Vol. 1, pp. 643-646, May 2001
[9] N. Mohieldin, E. Sanchez-Sinencio, J. Silva-Martinex, “A Fully Balanced Pseudo-Differential OTA
with Common-Mode Feedforward and Inherent Common-Mode Feedback Detector,” IEEE Journal of
Solid-State Circuits, vol. 38, no. 4, April 2003
[10]Shouli Yan and Edgar Sanchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A
Tutorial,” IEICE Transactions on Analog Integrated Circuits and Systems, vol. E00-A, no. 2,
February, 2000
[11]Datasheet of IC CA3080A and OPA 2662
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Authors
Dhaval Modi received the B.Tech degree in electronics and Communication
engineering from Nirma University, Ahmedabad, India in 2009 and M.E. degree
in Communication System Engineering from L.D. College of Engineering,
Gujarat, India in 2011. His area of research includes analog VLSI and making
various applications using different algorithms.
Jayesh Patel received the B.E. degree in electronics and Communication
engineering from Gujarat University, Ahmedabad, India in 2006 and M.E.
degree in Communication System Engineering from L.D. College of
Engineering, Gujarat, India in 2009. Currently he is working with technical
education board, Gandhinagar, Gujarat since 2011.