This document summarizes a research paper that proposes a new high-speed, low power consumption D flip-flop circuit for use in phase frequency detectors and frequency dividers in phase locked loops. The proposed D flip-flop circuit was designed in UMC 180nm CMOS technology and simulated using CADENCE. Simulation results showed the proposed circuit has faster operation and lower power consumption compared to a conventional D flip-flop circuit. The proposed D flip-flop was also used to design frequency divider circuits for divide ratios of 2 and 64, which were also simulated to validate the design.

1. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
INTERNATIONAL JOURNAL OF ELECTRONICS AND
17 – 19, July 2014, Mysore, Karnataka, India
COMMUNICATION ENGINEERING TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 8, August (2014), pp. 185-193
© IAEME: http://www.iaeme.com/IJECET.asp
Journal Impact Factor (2014): 7.2836 (Calculated by GISI)
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185
IJECET
© I A E M E
A HIGH-SPEED, LOW POWER CONSUMPTION D FLIP-FLOP FOR HIGH
SPEED PHASE FREQUENCY DETECTOR AND FREQUENCY DIVIDER
Vishwanath Muddi1, Prof. Sanjay Eligar2
1, 2Dept. of ECE BVBCET Hubli, India
ABSTRACT
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
Keywords: Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge Pump (CP), Low
Pass Filter (LPF), Voltage Controlled Oscillator (VCO), Frequency Divider, True signal phase clock
(TSPC).
1. INTRODUCTION
D flip-flop is an important part of the modern digital circuits. Phase locked loop with an
excellent performance is widely studied in recent years. Frequency divider and PFD are
indispensable modules of PLL, which uses D flip-flop as an integral part [1]. Edge Triggered D flip
flops are often implemented in integrated high speed operations using dynamic logic. This means
that the digital output is stored on parasitic device capacitance while the device is not transitioning.
This design of dynamic flip flops also enables simple resetting since the reset operation can be
performed by simply discharging one or more internal nodes. The conventional D flip-flop which
uses E-TSPC logic has higher operating frequencies but it features static power dissipation. However
this causes small increase in power dissipation, since at the frequencies of interest dynamic power

2. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
consumption is dominant. In the proposed circuit dynamic power consumption was reduced by
lowering internal switching and speed is increased by shortening input to output path.
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2. PHASE LOCKED LOOP (PLL)
This section consists of details circuit architectures of Phase locked loop, Phase frequency
Detector (PFD) and Frequency divider.
Phase locked loop is mostly used in wireless communication and data recovery circuits. At
present for above mentioned application a low voltage low area and high performance integrated
circuits are used which complicates the implementation of such type of integrated circuit [1].
Fig. 1: Basic block diagram of a PLL
A PLL is a negative feedback control system circuit. As the name implies, the purpose of a
PLL is to generate a signal in which the phase is the same as the phase of a reference signal. This is
done after many iterations of comparing the reference and feedback signals.
The overall goal of the PLL is to match the reference and feedback signals in phase, this is the lock
mode. After this, the PLL continues to compare the two signals but since they are in lock mode, the
PLL output is constant.
A basic form of a PLL consists of five main blocks:
1. Phase Frequency Detector (PFD) 2. Charge Pump (CP) 3. Low Pass Filter (LPF) 4. Voltage
Controlled Oscillator (VCO) 5. Divide by ‘N’Counter.
Some applications of Phase locked loop are:
1. Frequency Synthesis
2. Clock Generation
3. Carrier Recovery (Clock Recovery)
4. Skew Reduction
5. Jitter and Noise Reduction
2.1 PHASE FREQUENCY DETECTOR
The “Phase frequency Detector” (PFD) is one of the main part in PLL circuits. It compares
the phase and frequency difference between the reference clock and the feedback clock. Depending
upon the phase and frequency deviation, it generates two output signals “UP” and “DOWN”. Figure
shows a traditional PFD circuit.

3. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
187
Fig. 2: Block Diagram of PFD using NAND gate
2.2 FREQUENCY DIVIDER
The output of the VCO is fed back to the input of PFD through the frequency divider circuit.
The frequency divider in the PLL circuit forms a closed loop. It scales down the frequency of the
VCO output signal. A simple D flip flop (DFF) acts as a frequency divider circuit. The schematic of
a simple DFF based divide by 2 frequency divider circuit is shown in the Fig. 3.
Fig. 3: Block Diagram of Frequency Divider
3. CONVENTIONAL D FLIP-FLOP
This section consists of details circuits of Conventional D Flip-Flop.
Fig. 4: Circuit Diagram of Conventional D Flip Flop

4. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
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Fig.4 shows the circuit diagram of a rising edge triggered D-type flip-flop (DFF) which is
constructed with the TSPC principle [6]. The circuit consists of 12 transistors, in 5 simple stages.
When the clock signal is low, the first stage acts as a transparent latch to receive the input signal,
while the output node of the second stage is being precharged. During this cycle, the third and fourth
stages simply keep the previous output state. When the clock signal switches from low to high, the
first stage ceases to be transparent and the second stage starts evaluation. At the same time, the third
stage becomes transparent and transmits the sampled value to the output. Note that the final stage
(inverter) is only used to obtain the non-inverted output level.
The conventional D flip-flop which uses E-TSPC logic has higher operating frequencies but
it features static power dissipation However this causes small increase in power dissipation, since at
the frequencies of interest dynamic power consumption is dominant.
4. DESIGN OF PROPOSED D FLIP-FLOP
This section consists of details circuits of Proposed D Flip-Flop.
Fig. 5: Circuit Diagram of Proposed D Flip Flop
Circuit schematic of proposed D flip-flop is as shown in fig. 5. This flip-flop modifies the
TSPC flip-flop to satisfy the required function of D flip flop [3]. The operation of the proposed D
flip flop is as follows. When input clock and reset signal are low, node A is connected to VDD
through m1,mr1 and charges the node A to VDD. At the rising edge of the clock signal, node B is
connected to ground through m3 and m4.Once the node A is charged to VDD,the node B is not
effected by input clock signal. Because the charges at node the A turn off the m3 and this prevents
the node B from being pulled up. Therefore, the node B is disconnected from input node. When the
reset signal is applied, node A is disconnected from VDD by mr1 and is connected to ground by mr2.
As soon as the node A is discharged, the node B is pulled up through m2. The mr1 is added to
prevent the short circuit that occurs whenever the reset is applied.
When the clock signal is low while the reset high, a current path is made from VDD to
ground if mr1 is not provided. This increases the short circuit power consumption. Moreover, the
reset time is increased because m1 charges the node A to VDD while the mr2 discharges node A to
ground. Discharging node A quickly means the fast reset operation.

5. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
5. SIMULATION RESULTS AND WAVEFORMS
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The both types of D Flip-Flop are simulated on CADENCE on 180nm CMOS Technology
with 1.8V supply voltage.
The Fig.6 shows Schematic of Conventional D Flip-Flop.
Fig. 6: Schematic of Conventional D Flip-Flop
The Fig.7 shows the Simulation result of Conventional D Flip-Flop.
Fig. 7: Simulation Result of Conventional D Flip-Flop

6. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
The Fig.8 shows the Schematic of Proposed D Flip-Flop.
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Fig. 8: Schematic of Proposed D Flip-Flop
The Fig.9 shows the Simulation result of Proposed D Flip-Flop.
Fig. 9: Simulation Result of Proposed D Flip-Flop

7. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
Table 1 shows Simulation parameters of Conventional D Flip-Flop.
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Table 1: Simulation parameters of Conventional D Flip-Flop
PARAMETER M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11
LENGTH
(nM)
180 180 180 180 180 180 180 180 180 180 180 180
WIDTH 1.26
uM
1.26
uM
1.26
uM
1.26
uM
1.26
uM
1.26
uM
450
nM
450
nM
450
nM
450
nM
450
nM
450
nM
Vds -21uV -21uV -27uv -1.6v -1.6v -6.8v 1.8v .33v 1.47v .14v 87nV 1.8V
Vth(V) -.53 -.53 -.53 -.53 -.53 -.53 .42 .62 .43 .48 .48 .46
Pd 3.5u 3.5u 3.5u 3.5u 3.5u 3.5u 1.88u 1.88u 1.88u 1.88u 1.88u 1.88u
Ps 3.5u 3.5u 3.5u 3.5u 3.5u 3.5u 1.88u 1.88u 1.88u 1.88u 1.88u 1.88u
Ad .6174p 6174p 6174p 6174p 6174p 6174p .22p .22p .22p .22p .22p .22p
As 6174p 6174p 6174p 6174p 6174p 6174p .22p .22p .22p .22p .22p .22p
Table 2 show Simulation parameters of Proposed D Flip-Flop.
Table 2: Simulation parameters of Proposed D Flip-Flop
PARAMETER M3 M6 M4 MR2 M1 M5 MR1 M2
LENGTH 180 nM 180 nM 180 nM 180 nM 180 nM 180 nM 180 nM 180 nM
WIDTH .42 um .42 um .42 um .42 um 3.36 um 3.36 um 3.36 um 3.36 um
Vds 1.056V 14.18 nV .7436V .06404V -.03381V -1.8V -1.702V -1.298uV
Vth .5242V .4838V .4560 .4818V -.5348V -.5229V -.5166V -.5350V
Pd 2u 2u 2u 2u 7.7u 7.7u 1.9u 7.7u
Ps 2u 2u 2u 2u 7.7u 7.7u 1.9u 7.7u
Ad .224p .224p .224p .224p 1.646p 1.646p .2254p 1.646p
As .224p .224p .224p .224p 1.646p 1.646p .2254p 1.646p
Table 3 shows Comparative Analysis of D Flip-Flop
Table 3: Comparative Analysis of D Flip-Flop
Parameters Conventional D Flip-
Flop
Proposed D Flip-
Flop
Supply Voltage 1.8v 1.8v
Delay(sec) 5.7e-007 2.38e-008
Current 450uA 540nA
Power
Consumption(Watts)
150uW 310nW

8. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
The Fig.8 show Schematic of Frequency Divider (Divide by 2 counter)
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Fig. 8: Block Diagram of Frequency Divider
The Fig.9 show Simulation results of Frequency Divider (Divide by 2 counter)
Fig. 9: Simulation Results of Frequency Divider
The Fig.10 show Schematic of Frequency Divider (Divide by 64 counter)
Fig. 10: Block Diagram of Frequency Divider
The Fig.11 show Simulation results of Frequency Divider (Divide by 64 counter)

9. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
193
Fig. 11: Simulation Results of Frequency Divider
6. CONCLUSION
Minimization of power consumption is essential for high performance VLSI systems. This
paper compares the performance of Conventional and Proposed D Flip flop in UMC 180nm CMOS
technology. The supply voltage was 1.8V. As can be seen from the simulation results Conventional
D Flip consumes maximum amount of power. In the proposed circuit dynamic power consumption
was reduced by lowering internal switching and speed was increased by shortening input to output
path. Therefore, in order to have low power consumption we used Proposed D Flip flop. Frequency
divider has been implemented. A divide counter is required in the feedback loop to scales down the
frequency of the VCO output signal.
7. REFERENCES
Journal Papers
1. Prof. R .H. Talwekar, Prof. (Dr.) S.S Limayeemph, “A High- Speed, Low Power
Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector
in 180 nm CMOS Technology”, International Journal of VLSI design Communication
Systems (VLSICS), Vol. 3, No. 5, October 2012, pp. 157 – 162.
2. Patrik Larsson, “High-speed Architecture for Programmable Frequency Divider and a Dual-
Modulus Prescaler”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 5,
MAY 1996.
3. Won-Hyo Lee, Sung-Dao Lee and Jun-Dong cho ,“A high speed , low power phase frequency
detector and charge pump circuits for high frequency PLL”, IEICE TRANS FUNDAMENTAL,
vol E82-A,NO.11 November 1999.
4. Ko-Chi Kuo, Feng-Ji Wu, “A 2.4 GHz/5-GHz Low Power Pulse Swallow Counter in 0.18μm
CMOS technology”.1-4244-0387-1/06/$20.00©2006 IEEE.
5. Nesreen Ismail, “A Simple CMOS PFD for High Speed Applications”, European Journal of
Scientific Research ISSN 1450-216X Vol.33 No.2 (2009), pp.261-269 © EuroJournals
Publishing, Inc. 2009 http://www.eurojournals.com/ejsr.htm.
Books
6. S.M.Kang, and Y.Leblebici,CMOS Digital Integrated Circuits: Analysis and Design,
(McGraw-Hill Publication,3rd Edition, 2003).
7. BehzadRazavi, Design of analog cmos integrated circuits, (McGraw-Hill, 2001).