Discrete cosine transform (DCT) is a widely used tool in image and video compression applications. Recently, the high-throughput DCT designs have been adopted to fit the requirements of real-time application.
Operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic. DA-based DCT core with an error-compensated adder-tree (ECAT). The proposed ECAT operates shifting and addition in parallel by unrolling all the words required to be computed. Furthermore, the error-compensated circuit alleviates the truncation error for high accuracy design. Based on low-error ECAT, the DA-precision in this work is chosen to be 9 bits instead of the traditional 12 bits. Therefore, the hardware cost is reduced, and the speed is improved using the proposed ECAT.
Lifting Scheme Cores for Wavelet TransformDavid Bařina
The thesis focuses on efficient computation of the two-dimensional discrete wavelet transform. The state-of-the-art methods are extended in several ways to perform the transform in a single loop, possibly in multi-scale fashion, using a compact streaming core. This core can further be appropriately reorganized to target the minimization of certain platform resources. The approach presented here nicely fits into common SIMD extensions, exploits the cache hierarchy of modern general-purpose processors, and is suitable for parallel evaluation. Finally, the approach presented is incorporated into the JPEG 2000 compression chain, in which it has proved to be fundamentally faster than widely used implementations.
Lifting Scheme Cores for Wavelet TransformDavid Bařina
The thesis focuses on efficient computation of the two-dimensional discrete wavelet transform. The state-of-the-art methods are extended in several ways to perform the transform in a single loop, possibly in multi-scale fashion, using a compact streaming core. This core can further be appropriately reorganized to target the minimization of certain platform resources. The approach presented here nicely fits into common SIMD extensions, exploits the cache hierarchy of modern general-purpose processors, and is suitable for parallel evaluation. Finally, the approach presented is incorporated into the JPEG 2000 compression chain, in which it has proved to be fundamentally faster than widely used implementations.
Satellite Image Resolution Enhancement Technique Using DWT and IWTEditor IJCATR
Now a days satellite images are widely used In many applications such as astronomy and
geographical information systems and geosciences studies .In this paper, We propose a new satellite image
resolution enhancement technique which generates sharper high resolution image .Based on the high
frequency sub-bands obtained from the dwt and iwt. We are not considering the LL sub-band here. In this
resolution-enhancement technique using interpolated DWT and IWT high-frequency sub band images and the
input low-resolution image. Inverse DWT (IDWT) has been applied to combine all these images to generate
the final resolution-enhanced image. The proposed technique has been tested on satellite bench mark images.
The quantitative (peak signal to noise ratio and mean square error) and visual results show the superiority of
the proposed technique over the conventional method and standard image enhancement technique WZP.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
A Dual Tree Complex Wavelet Transform Construction and Its Application to Ima...CSCJournals
This paper discusses the application of complex discrete wavelet transform (CDWT) which has significant advantages over real wavelet transform for certain signal processing problems. CDWT is a form of discrete wavelet transform, which generates complex coefficients by using a dual tree of wavelet filters to obtain their real and imaginary parts. The paper is divided into three sections. The first section deals with the disadvantage of Discrete Wavelet Transform (DWT) and method to overcome it. The second section of the paper is devoted to the theoretical analysis of complex wavelet transform and the last section deals with its verification using the simulated images.
A Review on Image Compression using DCT and DWTIJSRD
Image Compression addresses the matter of reducing the amount of data needed to represent the digital image. There are several transformation techniques used for data compression. Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) is mostly used transformation. The Discrete cosine transform (DCT) is a method for transform an image from spatial domain to frequency domain. DCT has high energy compaction property and requires less computational resources. On the other hand, DWT is multi resolution transformation. The research paper includes various approaches that have been used by different researchers for Image Compression. The analysis has been carried out in terms of performance parameters Peak signal to noise ratio, Bit error rate, Compression ratio, Mean square error. and time taken for decomposition and reconstruction.
REVERSIBLE WAVELET AND SPECTRAL TRANSFORMS FOR LOSSLESS COMPRESSION OF COLOR ...cscpconf
Recent years have seen tremendous increase in the generation, transmission, and storage of
color images. A new lossless image compression method for progressive-resolution
transmission of color images is carried out in this paper based on spatial and spectral
transforms. Reversible wavelet transforms are performed across red, green, and blue color sub
bands first. Then adaptive spectral transforms like inter band prediction method is applied on
associated color sub bands for image compression. The combination of inverse spectral
transform (ST-1) and inverse reversible wavelet transforms (RWT-1) finally reconstructs the
original RGB color channels exactly. Simulation of the implemented method is carried out using
MATLAB 6.5
Comparison between JPEG(DCT) and JPEG 2000(DWT) compression standardsRishab2612
This topic comes under the Image Processing.In this comparison between JPEG and JPEG 2000 compression standard techniques is made.The PPT comprises of results, analysis and conclusion along with the relevant outputs
Lut optimization for distributed arithmetic based block least mean square ada...Ieee Xpert
Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter
Satellite Image Resolution Enhancement Technique Using DWT and IWTEditor IJCATR
Now a days satellite images are widely used In many applications such as astronomy and
geographical information systems and geosciences studies .In this paper, We propose a new satellite image
resolution enhancement technique which generates sharper high resolution image .Based on the high
frequency sub-bands obtained from the dwt and iwt. We are not considering the LL sub-band here. In this
resolution-enhancement technique using interpolated DWT and IWT high-frequency sub band images and the
input low-resolution image. Inverse DWT (IDWT) has been applied to combine all these images to generate
the final resolution-enhanced image. The proposed technique has been tested on satellite bench mark images.
The quantitative (peak signal to noise ratio and mean square error) and visual results show the superiority of
the proposed technique over the conventional method and standard image enhancement technique WZP.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
A Dual Tree Complex Wavelet Transform Construction and Its Application to Ima...CSCJournals
This paper discusses the application of complex discrete wavelet transform (CDWT) which has significant advantages over real wavelet transform for certain signal processing problems. CDWT is a form of discrete wavelet transform, which generates complex coefficients by using a dual tree of wavelet filters to obtain their real and imaginary parts. The paper is divided into three sections. The first section deals with the disadvantage of Discrete Wavelet Transform (DWT) and method to overcome it. The second section of the paper is devoted to the theoretical analysis of complex wavelet transform and the last section deals with its verification using the simulated images.
A Review on Image Compression using DCT and DWTIJSRD
Image Compression addresses the matter of reducing the amount of data needed to represent the digital image. There are several transformation techniques used for data compression. Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) is mostly used transformation. The Discrete cosine transform (DCT) is a method for transform an image from spatial domain to frequency domain. DCT has high energy compaction property and requires less computational resources. On the other hand, DWT is multi resolution transformation. The research paper includes various approaches that have been used by different researchers for Image Compression. The analysis has been carried out in terms of performance parameters Peak signal to noise ratio, Bit error rate, Compression ratio, Mean square error. and time taken for decomposition and reconstruction.
REVERSIBLE WAVELET AND SPECTRAL TRANSFORMS FOR LOSSLESS COMPRESSION OF COLOR ...cscpconf
Recent years have seen tremendous increase in the generation, transmission, and storage of
color images. A new lossless image compression method for progressive-resolution
transmission of color images is carried out in this paper based on spatial and spectral
transforms. Reversible wavelet transforms are performed across red, green, and blue color sub
bands first. Then adaptive spectral transforms like inter band prediction method is applied on
associated color sub bands for image compression. The combination of inverse spectral
transform (ST-1) and inverse reversible wavelet transforms (RWT-1) finally reconstructs the
original RGB color channels exactly. Simulation of the implemented method is carried out using
MATLAB 6.5
Comparison between JPEG(DCT) and JPEG 2000(DWT) compression standardsRishab2612
This topic comes under the Image Processing.In this comparison between JPEG and JPEG 2000 compression standard techniques is made.The PPT comprises of results, analysis and conclusion along with the relevant outputs
Lut optimization for distributed arithmetic based block least mean square ada...Ieee Xpert
Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter Lut optimization for distributed arithmetic based block least mean square adaptive filter
New Approach: Dominant and Additional Features Selection Based on Two Dimensi...CSCJournals
Modality reduction by using the Eigentransform method can not efficiently work, when number of training sets larger than image dimension. While modality reduction by using the first derivative negative followed by feature extraction using Two Dimensional Discrete Cosine Transform has limitation, which is feature extraction achieved of face sketch feature is included non-dominant features. We propose to select the image region that contains the dominant features. For each region that contains dominant features will be extracted one frequency by using Two Dimensional-Discrete Cosine Transform. To reduce modality between photographs as training set and face sketches as testing set, we propose to bring the training and testing set toward new dimension by using the first derivative followed by negative process. In order to improve final result on the new dimension, it is necessary to add the testing set pixels by using the difference of photograph average values as training sets and the corresponding face sketches average as testing sets. We employed 100 face sketches as testing and 100 photographs as training set. Experimental results show that maximum recognition is 93%.
There is a long history of relating to the recognition of facial expressions of emotion that can be traced back to Darwin in the late 1800’s. Darwin considered that facial expressions of emotion was an innate, adaptive, and physiological response which could provide evidence of an individual’s internal mental state. There were various early ways of measuring internal mental states that included attempts at accuracy in the measurement of the facial muscle movement
The discrete Fourier transform has many applications in science and engineering. For example, it is often used in digital signal processing applications such as voice recognition and image processing.
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM
based digital down convertor for Software Defined Radios. The proposed DDC is implemented using
optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase
decomposition structure is used to improve the hardware complexity of the overall design. The proposed
model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the
system performance in terms of speed and area. The DDC model is designed and simulated with Simulink
and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II
Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum
frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed
design is consuming very less resources available on target device to provide cost effective solution for
SDR based wireless applications.
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPSVLSICS Design
With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆) converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both
continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation mplemented in <0.18µm.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Pipelined Compression in Remote GPU Virtualization Systems using rCUDA: Early...Carlos Reaño González
Paper presented at the 2nd International Workshop on Deployment and Use of Accelerators (DUAC). Co-located with the 51st International Conference on Parallel Processing (ICPP). August 29, 2021 (virtual event). More information at: https://duac2022.wordpress.com/
A Simulation of Wideband CDMA System on Digital Up/Down ConvertersEditor IJMTER
In this paper, I present FPGA implementation of a digital down converter (DDC) and
digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in
nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx
System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the
circuits are verified on the Spartan - 3 FPGA
Giga bit per second Differential Scheme for High Speed InterconnectVLSICS Design
The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the
receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Google Calendar is a versatile tool that allows users to manage their schedules and events effectively. With Google Calendar, you can create and organize calendars, set reminders for important events, and share your calendars with others. It also provides features like creating events, inviting attendees, and accessing your calendar from mobile devices. Additionally, Google Calendar allows you to embed calendars in websites or platforms like SlideShare, making it easier for others to view and interact with your schedules.
Building a Raspberry Pi Robot with Dot NET 8, Blazor and SignalR - Slides Onl...Peter Gallagher
In this session delivered at Leeds IoT, I talk about how you can control a 3D printed Robot Arm with a Raspberry Pi, .NET 8, Blazor and SignalR.
I also show how you can use a Unity app on an Meta Quest 3 to control the arm VR too.
You can find the GitHub repo and workshop instructions here;
https://bit.ly/dotnetrobotgithub
2. Introduction To VLSI
Acronym of VLSI
Very-Large-
Scale
Integration
A VLSI contains more
than a million or so
switching devices or
logic gates
Early in the first decade
of the 21st century, the
actual number of
transistors has
exceeded 100 million
A piece of silicon (a
chip) is typically about 1
centimeter on a side
3. HDL (Hardware Descriptive Language)
HDL is a specialized computer language used to
describe the structure, design and operation
of electronic circuits, and most
commonly, digital logic circuits.
The two most widely-used and well-supported
HDL varieties used in industry are ”Verilog(verify
logic)” and ”VHDL( (Very High Speed Integrated
Circuit) Hardware Description Language)”.
4. VLSI APPLICATIONS:
VLSI is an implementation technology for electronic circuitry -
analogue or digital.
It is concerned with forming a pattern of interconnected
switches and gates on the surface of a crystal of
semiconductor.
Microprocessors
personal computers
microcontrollers
Memory - DRAM / SRAM
Special Purpose Processors - ASICS (CD players, DSP
applications)
Optical Switches
Has made highly sophisticated control systems mass-
producable and therefore cheap.
5. INTRODUCTION TO XILINX ISE
The ISE® Design Suite is the Xilinx® design
environment, which allows you to take your
design from design entry to Xilinx device
programming.
6. WHY XILINX ISE?
The ISE Design Suite: Logic Edition allows you to
go from design entry, through implementation and
verification, to device programming from within
the unified environment of the ISE Project
Navigator or from the command line.
8. VERILOG MODULE:
Verilog, standardized as IEEE
1364, is a hardware description
language (HDL) used to model
electronic systems.
It is most commonly used in the
design and verification of digital
circuits at the register-transfer
level of abstraction.
It is also used in the verification
of analog circuits and mixed-
signal circuits.
9. OVERVIEW OF PROJECT
Data compression
Compression techniques
Introduction to DA-DCT
ECAT ARCHITECTURE
DA-Butterfly-Matrix
10. DATA COMPRESSION
Despite the many advantages of digital
representation of signals compared to the analog
counterpart, they need a very large number of bits for
storage and transmission.
For Example, a high-quality audio signal requires
approximately 1.5 megabits per second for digital
representation and storage.
11. A television-quality low-resolution color video of 30
frames per second with each frame containing 640 x
480 pixels (24 bits per color pixel) needs more than
210 megabits per second of storage.
As a result, a digitized one-hour color movie would
require approximately 95 gigabytes of storage. The
storage requirement for upcoming high-definition
Television (hdtv) of resolution 1280 x 720 at 60
frames per second is far greater.
16. DCT(DISCRETE COSINE TRANSFORM):
Discrete cosine transform (DCT) is a
widely used tool in image and video
compression applications.
Recently, the high-throughput DCT
designs have been adopted to fit the
requirements of real-time application.
17. STEPS INVOLVED IN COMPRESSION OF
THE IMAGE
Dividing the image
into pixels and
level shifting
them.
DCT is performed
on the pixels
resulting in DCT
blocks.
Quantization is
done on these
blocks.
Quantized
matrices are
arranged in zigzag
order to
differentiate low
frequency
components and
high frequency
components.
The encoder block
encodes the
quantized data
Zero run and
huffman coding
techniques are
used to encode
the data in
encoder block.
18. REDUNDANCY CODING
To remove the unnecessary data while coding is
called as Redundancy Coding.
Types of Redundancies
Coding
redundancy
Inter pixel
redundancy
Psycho-visual
redundancy
19. DISCRETE COSINE TRANSFORMATION
The forward and inverse 2-D DCT can be written as:
where x(ij) is the image pixel data, and Z(u,v) is the transport data
21. The 8 x 8 DCT coefficient matrix can be written as:
Even rows of C are even-symmetric and odd rows are
odd-symmetric.
22. By exploiting this symmetry in the rows of C and
separating even and odd rows we can get 1D-DCT as
follows:
23. For 2-D DCT computation of a 8x8 2-D data, first row-
wise 8x1 1-D DCT is taken for all rows followed by column-
wise 8x1 1-D DCT to all columns. Intermediate results of 1-D
DCT are stored in transposition memory.
26. ECAT ARCHITECTURE
Error-Compensated Adder Tree
ECAT Architecture For Distributed Arithmetic Based DCT
• DA-based architecture and the proposed ECAT to achieve a high-speed,
small area and low-error design.
• It is proposed to compensate for the truncation error in high-speed applications.
• Reduces the shifting and addition computation time .
27. Two Types
MP
P (MSBs)
TP
T (LSBs)
• P-bit words operate the shifting and addition in parallel
• The output Y will obtain the P-bit MSBs using a rounding operation called
Post Truncation (Post-T).
• TP is usually truncated to reduce in parallel shifting and addition operations,
known as the Direct truncation (Direct-T).
29. Proposed ECAT Architecture
• Full - Adder
• Cell with three inputs (a, b, c)
• Two outputs, a sum (s) and a carry-out (co)
• Half - Adder
• Two inputs (a &b)
• Two outputs, a sum (s) and a carry-out (co)
Proposed ECAT architecture of shifting and addition operators
30. PROPOSED 8*8 1-D DCT CORE DESIGN
xm Denotes the input data.
Zn Denotes the transform output.
Above equation can be divided into even and odd parts: Ze and Zo
36. Device Utilization Summary:
Timing Summary:
Speed Grade: -4
• Minimum period: No path found
• Minimum input arrival time before clock: 23.566ns
• Maximum output required time after clock: 4.283ns
• Maximum combinational path delay: No path found
37. ADVANTAGES
The main advantage of compression is that it reduces
the data storage requirements.
It also offers an attractive approach to reduce the
communication cost in transmitting high volumes of
data
This significantly aids in reducing the cost of
communication due to the data rate reduction.
Hence the audience can experience rich-quality
signals for audio-visual data representation.
38. we can receive toll-quality audio at the other side of
the globe at a much better price compared to a
decade ago.
A single 6 MHz broadcast television channel can
carry HDTV signals.
Because of the reduced data rate offered by the
compression techniques, computer network and
Internet usage is becoming more and more image and
graphic friendly, rather than being just data- and text-
centric phenomena.
39. SECONDARY ADVANTAGES
Data compression has great implications in
database access.
Data security can also be greatly enhanced by
encrypting the decoding parameters and
transmitting them separately from the compressed
database files.
An extra level of security can be achieved by
making the compression and decompression
processes totally transparent to unauthorized users.
40. The rate of input-output operations in a computing
device can be greatly increased due to shorter
representation of data.
Data compression obviously reduces the cost of
backup and recovery of data in computer systems by
storing the backup of large database files in
compressed form.
The advantages of data compression will enable
more multimedia applications with reduced cost.
41. DISADVANTAGES
Data compression depending on the application
area and sensitivity of the data.
The extra overhead incurred by encoding and
decoding processes is one of the most serious
drawbacks of data compression, which discourages its
usage in some areas.
This extra overhead is usually required in order to
uniquely identify or interpret the compressed data.
Data compression generally reduces the reliability of
the data records.
42. Transmission of very sensitive compressed data
(e.g., medical information) through a noisy
communication channel (such as wireless media) is
risky because the burst errors introduced by the
noisy channel can destroy the transmitted data.
Disruption of data properties, since the
compressed data is different from the original data.
In many hardware and systems implementations,
the extra complexity added by data compression can
increase the system’s cost and reduce the system’s
efficiency.
43. FUTURE SCOPE
This work can be extended
in order to increase the
accuracy by increasing the
level of transformations.
This work can improve by
implementing JPEG 2000
Image compression
standard in which ordinary
DCT transformation part
can be replaced by our
Distributed Arithmetic
Discrete Cosine Transform
(DA DCT) Design.
This can be used as a part
of the block in the full
fledged application, i.e., by
using these DA DCT, the
applications can be
developed such as
compression,
watermarking, etc.
The 8-Point Distributed
Arithmetic Discrete Cosine
Transform (DA DCT) Design
can be made to 16, 32-
point Distributed
Arithmetic Discrete Cosine
Transform (DA DCT) by
making minor
modifications to the code.
44. CONCLUSION
This paper presents an efficient architecture
for computing the 2-D DCT with distributed
arithmetic. The proposed architecture requires
less hardware than conventional architectures
which use the original DCT algorithm or the
even-odd frequency decomposition method.
45. The modules of the transpose memory and parallel
Distributed Arithmetic 2-D DCT architecture were
designed and synthesized. The paper contributed
with specific simplifications in the multiplier stage, by
using shift and add method, which lead to hardware
simplification and speed up over architecture.