This document discusses generics and packages in VHDL. Generics are used to pass parameters into VHDL designs and allow modeling of parameterized designs. Packages allow sharing of common declarations across designs and provide a mechanism to encapsulate functions and types. The document provides examples of using generics to model designs with variable port sizes and a package example with a function declaration and body that is used in another design.

1. Generics

2. Generics
● Used to pass information into a design description
from an environment
– E.g. rise and fall delays ,size of ports
● Used to construct parameterized models

3. entity AND_GATE is
generic (N:NATURAL);
port (A:in BIT_VECTOR (1 to N);
Z:out BIT);
end AND_GATE;
Architecture EXAMPLE of AND_GATE is
begin
process(A)
variable AND_OUT :BIT;
begin
AND_OUT :=„1‟;
for K in 1 to N loop
AND_OUT :=AND_OUT and A(K);
Exit when AND_OUT =„0‟;
end loop;
Z<=AND_OUT;
end process;
end EXAMPLE;

4. ● Here the size of the input port has
been modeled as a generic.
● An entire class of AND gates with a
variable number of inputs has the
same behavioral model

5. ● The value of the generic may be specified in
1.Entity declaration
2.Component declaration
3.Component instantiation

6. ● The value of a generic may be specified in the
entity declaration .
– This is the default value
– It can be overridden by others

7. X

10. Example: 32-bit Shift Register, sync rst
entity SER_PAR_SH_REG is port (
CLK, RST, Serial_Din : in std_logic;
Data : out std_logic_vector(31 downto 0) );
end entity SER_PAR_SH_REG;
architecture behavioral of SER_PAR_SH_REG is
Signal Internal_Data : std_logic_vector(31 downto 0);
begin
process (CLK)
begin
if CLK’event and CLK = ‘1’ then
if RST = ‘1’ then
Internal_Data <= x”00000000”;
else
Internal_Data <= Serial_Din & Internal_Data(31 downto 1);
end if;
end if;
end process;
Data <= Internal_Data;
end behavioral;
MUST use internal
signal, because it is
used on BOTH sides
of the equation.
THIS statement is the
actual Shift Register
Then must set
external signal
equal to internal
signal
MUST use library statements!!

11. ● Convert the 32-bit Shift Register into a
N-bit Shift Register using generics.

12. Example : 16-bit Loadable Counter, async reset
entity CNTR_16_async is port (
CLK, RST, Load : in std_logic;
Input_Data : in std_logic_vector(15 downto 0);
Count : out std_logic_vector(15 downto 0) );
end entity CNTR_16_async ;
architecture behavioral of CNTR_16_async is
Signal Internal_Count : std_logic_vector(15 downto 0) := X”0000”;
begin
process (CLK, RST)
begin
if RST = ‘1’ then
Internal_Count <= X”0000”;
elsif CLK’event and CLK = ‘1’ then
if Load = ‘1’ then
Internal_Count <= Input_Data;
else
Internal_Count <= Internal_Count + 1;
end if;
end if;
end process;
Count <= Internal_Count;
end behavioral;
MUST use library statements!!
MUST use internal
signal, because it is
used on BOTH sides
of the equation.
THIS statement is the
actual Counter
THIS statement is the
parallel load
The async Reset
Then must set
external signal
equal to internal
signal

13. Example : 16-bit Loadable Counter, async reset
entity CNTR_16_async is port (
CLK, RST, Load : in std_logic;
Input_Data : in std_logic_vector(15 downto 0);
Count : out std_logic_vector(15 downto 0) );
end entity CNTR_16_async ;
architecture behavioral of CNTR_16_async is
Signal Internal_Count : std_logic_vector(15 downto 0) := X”0000”;
begin
process (CLK, RST)
begin
if RST = ‘1’ then
Internal_Count <= X”0000”;
elsif CLK’event and CLK = ‘1’ then
if Load = ‘1’ then
Internal_Count <= Input_Data;
else
Internal_Count <= Internal_Count + 1;
end if;
end if;
end process;
Count <= Internal_Count;
end behavioral;
MUST use library statements!!
MUST use internal
signal, because it is
used on BOTH sides
of the equation.
THIS statement is the
actual Counter
THIS statement is the
parallel load
The async Reset
Then must set
external signal
equal to internal
signal

14. LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY unicntr IS
GENERIC(n : Positive := 8); --size of counter/shifter
PORT(clock, serinl, serinr : IN Std_logic; --serial inputs
mode : IN Std_logic_vector(2 DOWNTO 0); --mode control
datain : IN Std_logic_vector((n-1) DOWNTO 0); --parallel inputs
dataout : OUT Std_logic_vector((n-1) DOWNTO 0); --parallel outputs
termcnt : OUT Std_logic); --terminal count output
END unicntr;
Design a universal register which can be used as a straightforward storage
register, a bi-directional shift register, an up counter and a down counter.
The register can be loaded from a set of parallel data inputs and the
mode is controlled by a 3-bit input. The 'termcnt' (terminal count) output
goes high when the register contains zero.
Example : Universal Register

15. ARCHITECTURE v1 OF unicntr IS
SIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0);
BEGIN
main_proc : PROCESS
BEGIN
WAIT UNTIL (clock=‘1’ and clock’event);
CASE mode IS
--reset
WHEN "000" => int_reg <= (OTHERS => '0');
--parallel load
WHEN "001" => int_reg <= datain;
--count up
WHEN "010" => int_reg <= int_reg + 1;
--count down
WHEN "011" => int_reg <= int_reg - 1;
--shift left
WHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl;
--shift right
WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);
--do nothing
WHEN OTHERS => NULL;
END CASE;
END PROCESS;

16. det_zero : PROCESS(int_reg) --detects when count is 0
BEGIN
termcnt <= '1';
FOR i IN int_reg'Range LOOP
IF int_reg(i) = '1' THEN
termcnt <= '0';
EXIT;
END IF;
END LOOP;
END PROCESS;
--connect internal register to dataout port
dataout <= int_reg;
END v1;

17. Packages

18. Packages
● A package provides a convenient mechanism to
store and share declarations that are common
across many design units.
● A package is represented by
1. a package declaration, and optionally,
2. a package body.

19. Package declaration
● A package declaration contains a set of
declarations that may possibly be shared by many
design units.
● It defines the interface to the package, that is, it
defines items that can be made visible to other
design units, for example, a function declaration.

20. Package declaration

21. Package declaration - Example

22. Package declaration
● Items declared in a package declaration can be
accessed by other design units by using the library
and use context clauses.

23. Package body
● A package body primarily contains the behavior of
the subprograms and the values of the deferred
constants declared in a package declaration.

24. Package body
● The package name must be the same as the name of
its corresponding package declaration.
● A package body is not necessary if its associated
package declaration does not have any subprogram
or deferred constant declarations.

25. Package body

26. Package example
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package mymux is
function MUX(signal in1,in2,sel:in std_logic)
return std_logic;
end myMUX;
package body mymux is
function MUX(signal in1,in2,sel:in std_logic)
return std_logic is
begin
return ((in1 and (not sel)) or (in2 and sel));
end MUX;
end myMUX;

27. --Use of package
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mymux.all;
entity FullAdd is
Port ( A,b,Ci : in std_logic;
sum, carry : out std_logic);
end FullAdd;
architecture Behavioral of FullAdd is
signal x,y,cbar:std_logic;
begin
cbar<= not ci;
m1: x<=MUX (ci,cbar,b);
m2: y<=MUX (cbar,ci,b);
m3: sum<=MUX (x,y,a);
end Behavioral;

28. References
● [1]. “Digital Systems Design Using VHDL” by
Charles H Roth, Jr., Thomson Learining,
Brooks/Cole.
● [2]. “VHDL Primer” by J Bhasker, PHI, Third
edition.