The document describes the design and simulation of three-phase three-level diode clamped and improved inverter configurations feeding an asynchronous motor drive. It discusses the operation of different multilevel inverter topologies including diode clamped and improved inverters. The topologies are analyzed under single phase one leg voltage circuit analysis. A split-single phase asynchronous motor model is used as the load. Simulation results of the inverter-motor drive systems using Matlab/Simulink are presented, including rotor currents, stator currents, rotor speed, electromagnetic torque, and three-phase output voltages. The number of circuit components in each inverter topology is also compared.
Switched Diode Inductor Current and Capacitor Voltage Accumulator Based Dual ...theijes
In the distributed generation systems, energy sources such as wind energy, fuel cells (FCs), photovoltaic cells (PVs), batteries, etc all, play a vital role to decrease the energy crises in this current scenario. By utilizing the principles of electronic interfaces, the alternative and renewable energy sources are interconnected. To achieve the aim of integration, a multi input converter (MIC) is a perfect choice. This paper introduces the application of a switched diode inductor current and capacitor voltage accumulator (SDICVA) on conventional boost converter. This paper aims to obtain two different kinds of dual input boost converters one is based on the serial SDICVA and the other based on the parallel SDICVA with low component stresses, high voltage gains, low ripples, high conversion efficiencies and simple PWM control. The simulations are done in MATLAB/SIMULINK
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
To overcome the problem of mismatched voltage levels between parallel-connected low voltage photovoltaic (PV)
arrays and the higher grid voltage, a hybrid boost three level dc-dc converter is developed based on three level inverter with
the traditional single phase diode clamping. Only one inductor, two capacitors in series, and those power switches and diodes,
which are easy to be integrated, are used for establish the topology with transformerless high voltage gain. The operation
principle of the topology is analyzed, and then the pulse width modulation (PWM) control method is obtained according to
the switching functions about the output pulse voltages of both half-bridges. Therefore, the converter can not only operate
with high voltage gain, but also make the duty cycles of power switches closer to 0.5. A feedforward closed loop control
operation is proposed such that even in varying input the converter is capable of giving a constant output. Finally an
experimental is set up in the laboratory for open loop control operation. All experimental results verify the feasibility of the
circuit and validity of the PWM control method.
High Gain Interleaved Cuk Converter with Phase Shifted PWMtheijes
DC-DC converters with ripple on input source current inject harmonics to the power system which in turn cause harmful to other connected devices. These converters with high efficiency and low input current ripple are essential in most common applications. Cuk converter provide reduction in the ripple of input and output current compared to other traditional converters which can be used for either step up or step down applications. Generally, a conventional cuk converter in continuous conduction mode brings in large current ripple on input side which in turn injects harmonics to the source. This undesirable input current ripple is mitigated by employing the interleaved cuk converter (ICC). Simulation results of ICC shows that the input ripple current has been reduced significantly from 7.5A to 1A compared to conventional cuk converter. The energy-transfer-capacitor in basic cuk converters is splitted into two capacitors. The rectifier diode is replaced by two diodes that form with the two capacitors a switched-capacitor circuit, which appears connected between the input and output inductances of the original converter. A hybrid circuit, presenting a higher DC voltage ratio than the classical Cuk circuit can be obtained. A high gain interleaved cuk converter is designed and simulated in MATLAB/SIMULINK for 40V with an input of 20V.
Metal Halide HID lamps are becoming popular because of its high efficacy. The
operating characteristic of Metal Halide (MH) HID lamps is complex as it has several stage
of operation. The objective of this paper is to design an electric control system for metal
halide high intensity discharge (HID) lamps using half bridge inverter. The LCC resonant
mode is used to provide the sufficient voltage and current to the MH lamp during its
ignition and normal running condition. An adaptive control method is used to regulate the
lamp power. A close loop current control method is used. In this close loop Type-3 regulator
is used as a compensator. The variation in lamp power with and without loop is discussed.
The stability of the close loop is also analysed. PSIM Simulation Software is used to do this
analysis.
Switched Diode Inductor Current and Capacitor Voltage Accumulator Based Dual ...theijes
In the distributed generation systems, energy sources such as wind energy, fuel cells (FCs), photovoltaic cells (PVs), batteries, etc all, play a vital role to decrease the energy crises in this current scenario. By utilizing the principles of electronic interfaces, the alternative and renewable energy sources are interconnected. To achieve the aim of integration, a multi input converter (MIC) is a perfect choice. This paper introduces the application of a switched diode inductor current and capacitor voltage accumulator (SDICVA) on conventional boost converter. This paper aims to obtain two different kinds of dual input boost converters one is based on the serial SDICVA and the other based on the parallel SDICVA with low component stresses, high voltage gains, low ripples, high conversion efficiencies and simple PWM control. The simulations are done in MATLAB/SIMULINK
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
To overcome the problem of mismatched voltage levels between parallel-connected low voltage photovoltaic (PV)
arrays and the higher grid voltage, a hybrid boost three level dc-dc converter is developed based on three level inverter with
the traditional single phase diode clamping. Only one inductor, two capacitors in series, and those power switches and diodes,
which are easy to be integrated, are used for establish the topology with transformerless high voltage gain. The operation
principle of the topology is analyzed, and then the pulse width modulation (PWM) control method is obtained according to
the switching functions about the output pulse voltages of both half-bridges. Therefore, the converter can not only operate
with high voltage gain, but also make the duty cycles of power switches closer to 0.5. A feedforward closed loop control
operation is proposed such that even in varying input the converter is capable of giving a constant output. Finally an
experimental is set up in the laboratory for open loop control operation. All experimental results verify the feasibility of the
circuit and validity of the PWM control method.
High Gain Interleaved Cuk Converter with Phase Shifted PWMtheijes
DC-DC converters with ripple on input source current inject harmonics to the power system which in turn cause harmful to other connected devices. These converters with high efficiency and low input current ripple are essential in most common applications. Cuk converter provide reduction in the ripple of input and output current compared to other traditional converters which can be used for either step up or step down applications. Generally, a conventional cuk converter in continuous conduction mode brings in large current ripple on input side which in turn injects harmonics to the source. This undesirable input current ripple is mitigated by employing the interleaved cuk converter (ICC). Simulation results of ICC shows that the input ripple current has been reduced significantly from 7.5A to 1A compared to conventional cuk converter. The energy-transfer-capacitor in basic cuk converters is splitted into two capacitors. The rectifier diode is replaced by two diodes that form with the two capacitors a switched-capacitor circuit, which appears connected between the input and output inductances of the original converter. A hybrid circuit, presenting a higher DC voltage ratio than the classical Cuk circuit can be obtained. A high gain interleaved cuk converter is designed and simulated in MATLAB/SIMULINK for 40V with an input of 20V.
Metal Halide HID lamps are becoming popular because of its high efficacy. The
operating characteristic of Metal Halide (MH) HID lamps is complex as it has several stage
of operation. The objective of this paper is to design an electric control system for metal
halide high intensity discharge (HID) lamps using half bridge inverter. The LCC resonant
mode is used to provide the sufficient voltage and current to the MH lamp during its
ignition and normal running condition. An adaptive control method is used to regulate the
lamp power. A close loop current control method is used. In this close loop Type-3 regulator
is used as a compensator. The variation in lamp power with and without loop is discussed.
The stability of the close loop is also analysed. PSIM Simulation Software is used to do this
analysis.
Modeling and Analysis of Transformerless High Gain Buck-boost DC-DC ConvertersIAES-IJPEDS
This paper proposes a transfomerless switched capacitor buck boost converter model, which provides higher voltage gain and higher efficiency when compared to the conventional buck boost converter. The averaged model based on state- space description is analyzed in the paper. The simulation results are presented to confirm the capability of the converter to generate high voltage ratios. The comparison between the proposed model and the traditional model is also provided to reveal the improvement. The proposed converter is suitable for for a wide application which requires high step-up DC-DC converters such as DC micro-grids and solar electrical energy.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Design and Development of Digital control based Asymmetric Multilevel Inverte...idescitation
Multilevel inverter is an effective topology for
increasing power demand and reducing harmonics of AC
waveforms. This paper presents an efficient seven-level
asymmetric cascaded multilevel inverter suited for renewable
energy applications. A digital control method employing flip-
flops has been proposed which reduces Total Harmonic
Distortion (THD) and switching losses compared to the
conventional PWM technique. Various performance
parameters namely THD, switching loss, first-order distortion
factor (DF1) and second-order distortion factor (DF2) is
analyzed and a simulation model of the proposed digital
control is developed in MATLAB/SIMULINK. Hardware
prototype will be built to validate the results.
Fuzzy Control Based Quadrupler Boost ConverterIJSRD
A voltage quadruple boost converter is presented. This converter is used to obtain higher voltage gain and reduces the voltage stress across the switches and diodes. These voltage multipliers are used in high voltage, low current applications such as for accelerating purpose in a cathode ray tube and also this converter topology is advanced than previous dc-dc converters. Voltage quadruple converter uses parallel-input series-output connection. Comparing with two phase interleaved boost converter one can see that two more capacitors and two more diodes are added so that during the energy transfer period partial inductor stored energy is stored in one capacitor and partial inductor stored energy together with the other capacitor store energy is transferred to the output to achieve much higher voltage gain. However, the proposed voltage gain is twice that of the interleaved two-phase boost converter. Simulation of the converter is carried out using MATLAB/SIMULINK software. The converter is simulated using fuzzy logic control and also the experimental setup was done.
Analysis and characterization of different high density on chip switched capa...Aalay Kapadia
Power converter is a key component in micro-scale energy harvesting systems. Micro-scale energy harvesting has become an increasingly viable and promising area for powering ultra-low power systems. Switched-capacitor (SC) power converters that use capacitors as energy storage elements offer much better power density than switched-inductor counterparts and are thus attractive in low-power area-constrained applications. Switched-capacitor (SC) converters have shown tremendous promise in this regard due to favorable device utilization and scaling trends, and the emergence of high-density silicon-compatible capacitor technologies. With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. This project first reviews various design techniques for implementing high density On-chip Switched-capacitor (SC) power converters and secondly suggests the best technique to solve aspects of power converter design: Area Density, Power Consumption & Efficiency.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Soft Switched Multi-Output Flyback Converter with Voltage DoublerIJPEDS-IAES
A novel multi-output voltage doubler circuit with resonant switching
technique is proposed in this paper. The resonant topology in the primary
side of the flyback transformer switches the device either at zero voltage or
current thus optimizing the switching devices by mitigating the losses. The
voltage doubler circuit introduced in the load side increases the voltage by
twice the value thereby increasing the load power and density. The proposed
Multi-output Isolated Converter removes the need for mutiple SMPS units
for a particular application. This reduces the size and weight of the
converters considerably leading to a greater payload. This paper aims at
optimizing the proposed converter with some design changes. The results
obtained from the hardware prototype are given in a comprehensive manner
for a 3.5W converter operating at output voltages of 5V and 3.3V at 50 kHz
switching frequency. The converter output is regulated with the PI controller
designed with SG3523 IC. The effects of load and line regulation for ±20%
variations are analyzed in detail.
Comparison of PI and PID Controlled Bidirectional DC-DC Converter SystemsIJPEDS-IAES
This paper deals with comparison of responses of the PI and the PID
controlled bidirectional DC-DC converter systems. A coupled inductor is
used in the present work to produce high gain. Open loop and closed loop
controlled systems with PI and PID controllers are designed and simulated
using Matlab tool. The principles of operation and simulation case studies are
discussed in detail. The comparison is made in terms of rise time, fall time,
peak overshoot and steady state error.
Transformer less Boost Converter Topologies with Improved Voltage Gain Operat...IJMER
In this project, a new step up converter proposed in a recent work is analyzed, designed, simulated with MATLAB Simulink. Conventional dc–dc boost converters are unable to provide high step-up voltage gains due to the effect of power switches, rectifier diodes, and the equivalent series resistance of inductors and capacitors. This paper proposes transformer less dc–dc converters to achieve high step-up voltage gain without an extremely high duty ratio. In the proposed converters, two inductors with the same level of inductance are charged in parallel during the switch-on period and are discharged in series during the switch-off period. The structures of the proposed converters are very simple.
PWM Switched Voltage Source Inverter with Zero Neutral Point Potentialijsrd.com
A three phase three-level pulse width modulation
(PWM) switched voltage source inverter with zero neutral
point potential is designed. It consists of three single-phase
inverter modules and each module is composed of a
switched voltage source and inverter switches. The major
advantage is that the peak value of the phase output voltage
is twice as high as that of the conventional neutral-pointclamped
PWM inverter. Thus, the proposed inverter is
suitable for applications with low voltage sources such as
batteries, fuel cells, or solar cells. Furthermore, three-level
output waveforms of the inverter can be achieved without
the switch voltage unbalance problem. Since the average
neutral point potential of the inverter is zero, a common
ground between the input stage and the output stage is
possible. Therefore, it can be applied to a transformer-less
power conditioning system. The SVS inverter is tested by a
PSIM simulation and hardware is implemented and verified.
Analysis and hardware implementation of five level cascaded H Bridge inverterIJERA Editor
The cascaded multilevel inverter (CMLI) has gained much attention in recent years due to its advantages in high
voltage and high power with low harmonics applications. A standard cascaded multilevel inverter requires n DC
sources for 2n+1levels at the output, where n is the number of inverter stages. This paper presents a topology to
control cascaded multilevel inverter that is implemented with multiple DC sources to get 2"+1_ 1 levels. Without
using Pulse Width Modulation (PWM) technique, the firing circuit can be implemented using Microcontroller
which greatly reduces the Total Harmonic Distortion (THD) and switching losses. To develop the model of a
cascaded hybrid multilevel inverter, a simulation is done based on MATLAB/SIMULINK software and
hardware implementation was also done. Their integration makes the design and analysis of a hybrid multilevel
inverter more complete and detailed.
Modeling and Analysis of Transformerless High Gain Buck-boost DC-DC ConvertersIAES-IJPEDS
This paper proposes a transfomerless switched capacitor buck boost converter model, which provides higher voltage gain and higher efficiency when compared to the conventional buck boost converter. The averaged model based on state- space description is analyzed in the paper. The simulation results are presented to confirm the capability of the converter to generate high voltage ratios. The comparison between the proposed model and the traditional model is also provided to reveal the improvement. The proposed converter is suitable for for a wide application which requires high step-up DC-DC converters such as DC micro-grids and solar electrical energy.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Design and Development of Digital control based Asymmetric Multilevel Inverte...idescitation
Multilevel inverter is an effective topology for
increasing power demand and reducing harmonics of AC
waveforms. This paper presents an efficient seven-level
asymmetric cascaded multilevel inverter suited for renewable
energy applications. A digital control method employing flip-
flops has been proposed which reduces Total Harmonic
Distortion (THD) and switching losses compared to the
conventional PWM technique. Various performance
parameters namely THD, switching loss, first-order distortion
factor (DF1) and second-order distortion factor (DF2) is
analyzed and a simulation model of the proposed digital
control is developed in MATLAB/SIMULINK. Hardware
prototype will be built to validate the results.
Fuzzy Control Based Quadrupler Boost ConverterIJSRD
A voltage quadruple boost converter is presented. This converter is used to obtain higher voltage gain and reduces the voltage stress across the switches and diodes. These voltage multipliers are used in high voltage, low current applications such as for accelerating purpose in a cathode ray tube and also this converter topology is advanced than previous dc-dc converters. Voltage quadruple converter uses parallel-input series-output connection. Comparing with two phase interleaved boost converter one can see that two more capacitors and two more diodes are added so that during the energy transfer period partial inductor stored energy is stored in one capacitor and partial inductor stored energy together with the other capacitor store energy is transferred to the output to achieve much higher voltage gain. However, the proposed voltage gain is twice that of the interleaved two-phase boost converter. Simulation of the converter is carried out using MATLAB/SIMULINK software. The converter is simulated using fuzzy logic control and also the experimental setup was done.
Analysis and characterization of different high density on chip switched capa...Aalay Kapadia
Power converter is a key component in micro-scale energy harvesting systems. Micro-scale energy harvesting has become an increasingly viable and promising area for powering ultra-low power systems. Switched-capacitor (SC) power converters that use capacitors as energy storage elements offer much better power density than switched-inductor counterparts and are thus attractive in low-power area-constrained applications. Switched-capacitor (SC) converters have shown tremendous promise in this regard due to favorable device utilization and scaling trends, and the emergence of high-density silicon-compatible capacitor technologies. With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. This project first reviews various design techniques for implementing high density On-chip Switched-capacitor (SC) power converters and secondly suggests the best technique to solve aspects of power converter design: Area Density, Power Consumption & Efficiency.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Soft Switched Multi-Output Flyback Converter with Voltage DoublerIJPEDS-IAES
A novel multi-output voltage doubler circuit with resonant switching
technique is proposed in this paper. The resonant topology in the primary
side of the flyback transformer switches the device either at zero voltage or
current thus optimizing the switching devices by mitigating the losses. The
voltage doubler circuit introduced in the load side increases the voltage by
twice the value thereby increasing the load power and density. The proposed
Multi-output Isolated Converter removes the need for mutiple SMPS units
for a particular application. This reduces the size and weight of the
converters considerably leading to a greater payload. This paper aims at
optimizing the proposed converter with some design changes. The results
obtained from the hardware prototype are given in a comprehensive manner
for a 3.5W converter operating at output voltages of 5V and 3.3V at 50 kHz
switching frequency. The converter output is regulated with the PI controller
designed with SG3523 IC. The effects of load and line regulation for ±20%
variations are analyzed in detail.
Comparison of PI and PID Controlled Bidirectional DC-DC Converter SystemsIJPEDS-IAES
This paper deals with comparison of responses of the PI and the PID
controlled bidirectional DC-DC converter systems. A coupled inductor is
used in the present work to produce high gain. Open loop and closed loop
controlled systems with PI and PID controllers are designed and simulated
using Matlab tool. The principles of operation and simulation case studies are
discussed in detail. The comparison is made in terms of rise time, fall time,
peak overshoot and steady state error.
Transformer less Boost Converter Topologies with Improved Voltage Gain Operat...IJMER
In this project, a new step up converter proposed in a recent work is analyzed, designed, simulated with MATLAB Simulink. Conventional dc–dc boost converters are unable to provide high step-up voltage gains due to the effect of power switches, rectifier diodes, and the equivalent series resistance of inductors and capacitors. This paper proposes transformer less dc–dc converters to achieve high step-up voltage gain without an extremely high duty ratio. In the proposed converters, two inductors with the same level of inductance are charged in parallel during the switch-on period and are discharged in series during the switch-off period. The structures of the proposed converters are very simple.
PWM Switched Voltage Source Inverter with Zero Neutral Point Potentialijsrd.com
A three phase three-level pulse width modulation
(PWM) switched voltage source inverter with zero neutral
point potential is designed. It consists of three single-phase
inverter modules and each module is composed of a
switched voltage source and inverter switches. The major
advantage is that the peak value of the phase output voltage
is twice as high as that of the conventional neutral-pointclamped
PWM inverter. Thus, the proposed inverter is
suitable for applications with low voltage sources such as
batteries, fuel cells, or solar cells. Furthermore, three-level
output waveforms of the inverter can be achieved without
the switch voltage unbalance problem. Since the average
neutral point potential of the inverter is zero, a common
ground between the input stage and the output stage is
possible. Therefore, it can be applied to a transformer-less
power conditioning system. The SVS inverter is tested by a
PSIM simulation and hardware is implemented and verified.
Analysis and hardware implementation of five level cascaded H Bridge inverterIJERA Editor
The cascaded multilevel inverter (CMLI) has gained much attention in recent years due to its advantages in high
voltage and high power with low harmonics applications. A standard cascaded multilevel inverter requires n DC
sources for 2n+1levels at the output, where n is the number of inverter stages. This paper presents a topology to
control cascaded multilevel inverter that is implemented with multiple DC sources to get 2"+1_ 1 levels. Without
using Pulse Width Modulation (PWM) technique, the firing circuit can be implemented using Microcontroller
which greatly reduces the Total Harmonic Distortion (THD) and switching losses. To develop the model of a
cascaded hybrid multilevel inverter, a simulation is done based on MATLAB/SIMULINK software and
hardware implementation was also done. Their integration makes the design and analysis of a hybrid multilevel
inverter more complete and detailed.
PWM control techniques for three phase three level inverter drivesTELKOMNIKA JOURNAL
In this paper two very efficient pulse width modulation techniques were discussed named Sin pulse width modulation and space vector pulse width modulation. The basic structure of the three-level inverter neutral-point clamped is introduced and the basic idea about space vector pulse width modulation for three-level voltage source inverter has been discussed in detail. Nearest three vectors space vector pulse width modulation control algorithm is adopted as the control strategy for the three phase three level NPC inverter in order to compensate the neutral-point shifting. Mathematical formulation for calculating switching sequence has determined. Comparative analysis proving superiority of the space vector pulse width modulation technique over the conventional pulse width modulation, and the results of the simulations of inverter confirm the feasibility and advantage of the space vector pulse width modulation strategy over sin pulse width modulation in terms of good utilization of dc-bus voltage, low current ripple and reduced switching frequency. Space vector pulse width modulation provides advantages better fundamental output voltage and useful in improving harmonic performance and reducing total harmonic distortion.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Diode Free T-Type Five Level Neutral Point Clamped Inverter for Low Voltage D...IJTET Journal
Abstract—The multilevel inverter is used as a solution to increase the inverter operating voltage above the voltage limits of classical semiconductors. A Diode Free T-Type Five Level NPC inverter for Low Voltage DC System is proposed in this paper. The T-Type inverter topology is more efficient and conventional than I-type inverter topology. Considerable suppression of the harmonic current is the ultimate goal of multilevel inverter. Losses like Semiconductor loss, conduction loss are mainly due to IGBT & diode in the current path. So the proposed system is designed with cool MOSFET without diode. The middle bidirectional switch is replaced by two pair of MOSFET. Hence the five level NPC inverter is more significant for low and medium power range DC source and for Renewable energy system.
A REVIEW ON EVALUATION OF PV MODELS BASED ON AN INTEGRATION USING A NEW CONFI...ijiert bestjournal
The effect of linear imbalances and nonlinear loads on the voltage balance of the neutral-point- clamped converters is described in this paper. The Neutral-Point-Clamped inverters are used in the multilevel inverters for high power application s. In this paper a three level NPC inverter that couple accommodate with solar photovoltaic (PV) and battery storage in grid connected system. The three level space vector modulation technique (SVPWM) is proposed. The SVPWM correct the ac voltage under unbalance dc voltage condition .SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The control scheme has capability to control the power delivery between the solar PV,battery,and grid,it simulta neously provides maximum power point tracking (MPPT) operation for the solar PV. The res ults of matlab modeling of the system detail the comparative operation of inverter topologies wh ich are the conventional two level inverters and multilevel inverter topology to reduce total ha rmonic distortions in grid voltage and electromagnetic interference. Three-level NPC volta ge source inverter that can integrate both renewable energy and battery storage on the dc side of the inverter has been presented. The effectiveness of the proposed methodology is invest igated by the simulation of several scenarios,including battery charging and discharging with dif ferent levels of solar irradiation.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Asymmetrical Cascaded Multi Level Inverter using Control Freedom Pulse width ...IAES-IJPEDS
In this paper, the suggested topologies are gained by cascading a full bridge inverter with dissimilar DC sources. This topology has several new patterns adopting the fixed switching frequency, multicarrier control freedom degree with mixture conceptions are established and simulated for the preferred three-phase cascaded multilevel inverter. In outstanding switching arrangement terminations, there are convinced degrees of freedom to produce the nine level AC output voltages with terminated switching positions for producing altered output voltages. These investigations focus on asymmetrical cascaded multilevel inverter engaging with carrier overlapping pulse width modulation (PWM) topologies. These topologies offer less amount of harmonics present in the output voltage and superior root mean square (RMS) values of the output voltages associated with the traditional sinusoidal pulse width modulation. This research studies carries with it MATLAB/SIMULINK based simulation and experimental results obtained using appropriated prototype to prove the validity of the proposed concept.
This paper introduces a new topology of multilevel inverter, which is able to operate at high performance. This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level inverters need at least twelve switches. The proposed topology has only ten switches. The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms. The detailed operation of the proposed inverter is explained. The theoretical analysis and design procedure are given. Simulation results are presented to confirm the analytical approach of the proposed circuit. A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz.
Simulation Of A 4-Switch,3-Phase Inverter Fed Induction Motor (IM) Drive Systemijiert bestjournal
This paper investigates the performance of a 4 - switch,3 - phase inverter (4S3P) fed cost effective induction motor (IM)drive system for high performance industrial drive systems. In the proposed approach,instead of a conventional 6 - switch,3 - phase inverter (6S3P) a 4 - switch,3 - phase inverter is utilized. This reduces the cost of the inverter,the switching losses,and the complexity of the control algorithms and interface circuits to generate 6PWM logic signals. The Simulation results of the proposed 4S3P inverter fed drive is also made in terms of speed response &total harmonic distortion (THD) in terms of stator current and inverter current. The proposed inverter fed IM drive is fou nd acceptable considering its cost reduction and other advantageous features. A general space vector pulse width modulation (SVPWM) method for control of four - switch three - phase inverters is presented.
Reduction of common mode voltage for cascaded multilevel inverters using phas...nooriasukmaningtyas
Demand of cascaded multilevel inverters in industries of electric drives and
renewable energy is increasing due to their large-scale capacity and high
voltage. The modulation technique of inverters significantly affects the
power quality of the inverter output voltage. This paper proposes a new
method of carrier wave modulation using the phase shift keying technique for
cascaded multilevel inverters. The phase of a constant frequency carrier wave
is changed at an accurate time by an input sinusoidal control signal. This
modulation technique is simply implemented and only needs a small
memory. It also helps reduce the common mode voltage of inverters in order
to suppress the output voltage harmonics. Moreover, the ability to reduce
switching count also helps the inverters decrease switching loss. The
simulated and experienced results on a cascaded 9-level 3-phase inverter and
an F28379D DSP kit have validated the performance of the proposed
technique compared with that of the APOD and POD methods.
A comparison of single phase standalone square waveform solar inverter topolo...IJECEIAES
In stand-alone photovoltaic installations the photovoltaic inverter allows transforming the DC power produced by the photovoltaic modules into an AC power. Depending on the shape of the AC output voltage generated by the inverter there exist three main types of stand-alone PV inverters: pure sine waveform inverters, modulated sine waveform inverters and square waveform inverters and each type of these inverters is also divided into different topologies. In this paper we will be interested and study the square waveform stand-alone inverter topologies which are the half bridge and the full bridge inverter topologies.
Abstract: The output voltage of an inverter has in general non-sinusoidal shape. The required AC output quantity – frequency and voltage – is created by a sequence of segments properly cut out from the input variable quantity, which is a DC-voltage. The required output quantities, AC voltage amplitude and frequency, are created either from rectangular pulses or by the pulse-width- modulation (PWM). Power source with a non-sinusoidal voltage applied to a electric equipment brings some undesirable effects. For example, it can cause additional losses in the windings and ferromagnetic circuits of transformers. In AC motors the additional losses are higher and operating characteristics of motors are worse. In photovoltaic power sources, the use of inverters must be carefully considered, because a wide range of harmonics can be generated. This would greatly decline the quality of produced and transmitted electric energy. Demand for high-voltage, high power converters capable of producing of producing high-quality waveform while utilizing low voltage devices and reduced switching frequency has led to the multilevel inverter development with regard to semiconductor power switch voltage limit. In this paper an overview is presented of different Multilevel inverter techniques to reduce the total harmonic distortion of output voltage in a inverter.
Modern trend in power generation is the use of two-stage configuration i.e., allocating a single PV cell
to a converter to produce grid voltage of adequate requirement and then to convert DC to AC voltage for grid
cnnection. Usually, the first stage is a DC-DC boost type converter which is responsible for extracting maximum
power from panel and boosting PV voltage to a value higher than peak of grid voltage. A converter is proposed,
which is derived from an active network based converter, is chosen as the first stage and a five level inverter is
used as the second stage of the configuration. Thus, in overall, the converter used is having high gain and reduced
switching stress. The Inverter used is having the advantage of low filter requirement, reduced stress, EMI and
reduced THD level. A closed loop control of the converter is done to maintain constant output voltage under
varying input voltage. MATLAB R2014a version software is used to simulate the model. The prototype of the
two stage configuration was developed and tested in the laboratory and results were verified using PIC 16F877A.
GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
Neha Bajwa, Vice President of Product Marketing, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
Goodbye Windows 11: Make Way for Nitrux Linux 3.5.0!SOFTTECHHUB
As the digital landscape continually evolves, operating systems play a critical role in shaping user experiences and productivity. The launch of Nitrux Linux 3.5.0 marks a significant milestone, offering a robust alternative to traditional systems such as Windows 11. This article delves into the essence of Nitrux Linux 3.5.0, exploring its unique features, advantages, and how it stands as a compelling choice for both casual users and tech enthusiasts.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
UiPath Test Automation using UiPath Test Suite series, part 5DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 5. In this session, we will cover CI/CD with devops.
Topics covered:
CI/CD with in UiPath
End-to-end overview of CI/CD pipeline with Azure devops
Speaker:
Lyndsey Byblow, Test Suite Sales Engineer @ UiPath, Inc.
Enchancing adoption of Open Source Libraries. A case study on Albumentations.AIVladimir Iglovikov, Ph.D.
Presented by Vladimir Iglovikov:
- https://www.linkedin.com/in/iglovikov/
- https://x.com/viglovikov
- https://www.instagram.com/ternaus/
This presentation delves into the journey of Albumentations.ai, a highly successful open-source library for data augmentation.
Created out of a necessity for superior performance in Kaggle competitions, Albumentations has grown to become a widely used tool among data scientists and machine learning practitioners.
This case study covers various aspects, including:
People: The contributors and community that have supported Albumentations.
Metrics: The success indicators such as downloads, daily active users, GitHub stars, and financial contributions.
Challenges: The hurdles in monetizing open-source projects and measuring user engagement.
Development Practices: Best practices for creating, maintaining, and scaling open-source libraries, including code hygiene, CI/CD, and fast iteration.
Community Building: Strategies for making adoption easy, iterating quickly, and fostering a vibrant, engaged community.
Marketing: Both online and offline marketing tactics, focusing on real, impactful interactions and collaborations.
Mental Health: Maintaining balance and not feeling pressured by user demands.
Key insights include the importance of automation, making the adoption process seamless, and leveraging offline interactions for marketing. The presentation also emphasizes the need for continuous small improvements and building a friendly, inclusive community that contributes to the project's growth.
Vladimir Iglovikov brings his extensive experience as a Kaggle Grandmaster, ex-Staff ML Engineer at Lyft, sharing valuable lessons and practical advice for anyone looking to enhance the adoption of their open-source projects.
Explore more about Albumentations and join the community at:
GitHub: https://github.com/albumentations-team/albumentations
Website: https://albumentations.ai/
LinkedIn: https://www.linkedin.com/company/100504475
Twitter: https://x.com/albumentations
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionAggregage
Join Maher Hanafi, VP of Engineering at Betterworks, in this new session where he'll share a practical framework to transform Gen AI prototypes into impactful products! He'll delve into the complexities of data collection and management, model selection and optimization, and ensuring security, scalability, and responsible use.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Essentials of Automations: The Art of Triggers and Actions in FMESafe Software
In this second installment of our Essentials of Automations webinar series, we’ll explore the landscape of triggers and actions, guiding you through the nuances of authoring and adapting workspaces for seamless automations. Gain an understanding of the full spectrum of triggers and actions available in FME, empowering you to enhance your workspaces for efficient automation.
We’ll kick things off by showcasing the most commonly used event-based triggers, introducing you to various automation workflows like manual triggers, schedules, directory watchers, and more. Plus, see how these elements play out in real scenarios.
Whether you’re tweaking your current setup or building from the ground up, this session will arm you with the tools and insights needed to transform your FME usage into a powerhouse of productivity. Join us to discover effective strategies that simplify complex processes, enhancing your productivity and transforming your data management practices with FME. Let’s turn complexity into clarity and make your workspaces work wonders!
GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...Neo4j
Leonard Jayamohan, Partner & Generative AI Lead, Deloitte
This keynote will reveal how Deloitte leverages Neo4j’s graph power for groundbreaking digital twin solutions, achieving a staggering 100x performance boost. Discover the essential role knowledge graphs play in successful generative AI implementations. Plus, get an exclusive look at an innovative Neo4j + Generative AI solution Deloitte is developing in-house.
GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...
D05432435
1. IOSR Journal of Engineering (IOSRJEN) www.iosrjen.org
ISSN (e): 2250-3021, ISSN (p): 2278-8719
Vol. 05, Issue 04 (April. 2015), ||V3|| PP 24-35
International organization of Scientific Research 24 | P a g e
Design And Simulation of Three-Phase Diode Clamped And
Improved Inverter Fed Asynchronous Motor
Drive With Three-Level Configurations
1
G. C. Diyoke, 1
I. K. Onwuka, 2
O.A. Okoye
1
Department of Electrical and Electronics Engineering,
2
Department of Mechanical Engineering,
Michael Okpara University of Agriculture, Umudike, Umuahia, Abia State, Nigeria.
Abstract: - This paper presents the study of Three-phase Three-Level inverter topology fed Asynchronous
motor drive. Three-level configurations are realized by Diode clamped and Improved multilevel inverter
topologies. The poor quality of voltage and current of a conventional inverter fed induction machine is due to
the presence of harmonics and hence there is significant level of energy losses. The Multilevel inverter
configurations are used to reduce the harmonics by means of synthesizing the output waveforms. The inverters
modes of operations are discussed under single phase one leg voltage circuit analysis. The three-phase
asynchronous motor is analysed under a split-single phase asynchronous motor. The higher levels can be
modulated by comparing a sinusoidal reference signal and multiple triangular carrier signals by means of pulse
width modulation technique. The simulation of three-phase three-level inverters fed induction motor model are
done using Matlab/Simulink. The results of rotor currents, stator currents, rotor speed, electromagnetic torque
and three-phase output voltages are plotted. Furthermore, the numbers of circuit component counts in different
inverter topologies are obtained.
Keywords: Asynchronous motor, Multilevel Inverter, Pulse width modulation, Speed, Three-phase, Torque.
I. INTRODUCTION
Nowadays, there are many applications for multilevel inverter topologies, such as Flexible AC Transmission
Systems (FACTS), High Voltage Direct Current (HVDC) transmission, electrical drives such as speed control of
three-phase water pump, conveyor systems, machine tools, and Dispersed Generation (DG) systems. A
multilevel inverter is a power electronic device built to synthesize a desired AC voltage from several levels of
DC voltages. Such inverters have been the subject of research in the recent years where the DC levels were
considered to be identical in that all of them were capacitors, batteries, solar cells, etc. In Recent Years, industry
has begun to demand higher power equipment, which now reaches the megawatt level. Controlled ac drives in
the megawatt range are usually connected to the medium-voltage network. Today, it is hard to connect a single
power semiconductor switch directly to medium voltage grids. For these reasons, a new family of multilevel
inverters has emerged as the solution for working with higher voltage levels [1], [2]. Multilevel inverters include
an array of power semiconductors and capacitor voltage sources, the output of which generate voltages with
staircase waveforms. The commutation of the switches permits the addition of the capacitor voltages, which
reach high voltage at the output, while the power semiconductors must withstand only reduced voltages. Fig. 1
shows a schematic diagram of one phase leg of inverters with different numbers of levels, for which the action
of the power semiconductors is represented by an ideal switch with several positions.
Fig. 1 One phase leg of an inverter with (a) two-level, (b) three-level, and (c) n-level.
2. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 25 | P a g e
A two-level inverter generates an output voltage with two values (levels) with respect to the negative terminal of
the capacitor and the voltages are zero and VC (see Fig. 1(a)), while the three-level inverter generates three
voltages as zero,VC, 2VC (see fig. 1(b)) and n-level inverter generates zero, VC, 2VC, 3VC… (n-1) VC (see fig.
1(c)).
Considering that m is the number of steps of the phase voltage with respect to the negative terminal of the
inverter, then the number of steps in the voltage between two phases of the load is K
K=2m-1 (1)
and the number of steps p in the phase voltage of a three-phase load in wye connection is
p=4m-3 (2)
The term multilevel starts with the least member which is three-level inverter as introduced by Nabae I t. [3]. By
increasing the number of levels in the inverter, the output voltages have more steps generating a staircase
waveform, which has a reduced harmonic distortion with high switching losses. However, a high number of
levels increases the control complexity and introduces voltage imbalance problems. Three different topologies
have been proposed for multilevel inverters: diode-clamped (neutral-clamped) [3]; capacitor-clamped (flying
capacitors) [1], [4]; and cascaded H-bridge with separate dc sources [1], [5]. In addition, several modulation and
control strategies have been developed or adopted for multilevel inverters including the following: multi-carrier
sinusoidal pulse width modulation (PWM), multilevel selective harmonic elimination, and space-vector
modulation (SVM).
II. THREE-PHASE MULTILEVEL INVERTER TOPOLOGIES
A. Diode-clamped multilevel inverter:
The most commonly used multilevel topology is the diode clamped inverter, in which the diode is used as the
clamping device to clamp the dc bus voltage so as to achieve steps in the output voltage. One phase of a three-
level diode clamped inverter is shown in Fig. 2.
Fig. 2 One Phase of three-Level diode clamped inverter topology
As it is shown in the circuit above, in this type of multilevel we have only one DC-source and the DC-
bus is split into n-level by n-1 capacitors. Here n= 3 and we have two capacitors. Fig. 2(A) represents half-wave
circuit topology for three-level diode clamped inverter. Consequently, the output phase voltage has the
following:
Vdc
2
, 0, -
Vdc
2
,. To explain how the staircase voltage is synthesized in fig. 2(A) above, the neutral point
0 is considered as the output phase voltage reference point. There are two switch combinations to synthesize two
level voltages across Va and 0. Firstly, for voltage level Va0 =
Vdc
2
, turn on all upper switches 𝑆1 and 𝑆2,
secondly, for voltage level Van = -
Vdc
2
, turn on all lower switches 𝑆1and 𝑆2and finally, for voltage level Van = 0,
3. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 26 | P a g e
turn on two middle switches 𝑆2 and 𝑆1. Fig. 2(B) represents full-wave circuit topology for three-level diode
clamped inverter. The output phase voltage has three-levels with negative reference:
Vdc
2
, 𝑉𝑑𝑐 , 0. To explain how
the staircase voltage is synthesized in fig. 2(B) above, the neutral point 0 is considered as the output phase
voltage reference point. There are two switch combinations to synthesize two level voltages across Va and 0.
Firstly, for voltage level Va0 =
Vdc
2
, turn on two middle switches 𝑆2 and 𝑆1, secondly, for voltage level Van = Vdc ,
turn on all upper switches 𝑆1 and 𝑆2, and finally, for voltage level Van = 0, turn on all lower switches 𝑆1and 𝑆2.
Fig. 2(B) represents full-wave circuit topology for three-level diode clamped inverter. There are two clamping
diodes (Da1 and Da1) and four anti-parallel diodes (D1 , D2, D1 and D2). These clamping diodes clamp the
switching voltage to half level of the dc-bus voltage. The neutral point 0 is considered as the reference point [6].
To produce a three-level voltage, two switch combinations must be used. Although each active switching device
is only required to block a voltage level of
Vdc
(𝑛−1)
, the clamping diodes must have different voltage rating for
reverse voltage blocking [7]. So if diodes with same voltage rating as the active devices are used, the number of
required diodes for each phase will be 2(2n-3) and the number of power switches are given by 2(n-1). This
number represents a linear increment and when n is sufficiently high, the number of diodes required will make
the system impractical to implement and if the inverter runs under PWM, the diodes reverse recovery of these
clamping diodes becomes the major design challenge in high-voltage high-power applications [7]. Fig. 2(B)
above can be extended to three-phase circuit configuration by interconnection of another two-phase circuit to get
Vb andVc, and the control logic circuit is achieved by phase-shifting phase -A by 120° and 240° respectively.
B. Improved multilevel inverter: This inverter topology consists of a diode embedded bidirectional
switches, half H-bridge convectional inverter circuit and two bank capacitors.
Fig. 3. One Phase of three-Level Improved inverter topology.
As it is shown in the circuit above, in this type of multilevel we have only one DC-source and the DC-
bus is split into n-level by n-1 capacitors. Here n= 3 and we have two capacitors. Fig. 3(A) represents half-wave
circuit topology for three-level improved inverter. Consequently, the output phase voltage has the following:
𝐕 𝐝𝐜
𝟐
, 0, -
𝐕 𝐝𝐜
𝟐
,. To explain how the staircase voltage is synthesized in fig. 3(A) above, the neutral point 0 is
considered as the output phase voltage reference point. The output voltage can be synthesized as follows:
Firstly, for voltage level 𝐕𝐚𝟎 =
𝐕 𝐝𝐜
𝟐
, turn on the upper switch 𝐒 𝟏, secondly, for voltage level 𝐕𝐚𝐧 = -
𝐕 𝐝𝐜
𝟐
, turn on
lower switch 𝐒 𝟐 and finally, for voltage level 𝐕𝐚𝐧 = 0, turn on the middle switch 𝑺 𝒂. Fig. 2(B) represents full-
4. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 27 | P a g e
wave circuit topology for three-level improved inverter. The output phase voltage has three-levels with negative
reference:
𝐕 𝐝𝐜
𝟐
, 𝐕𝐝𝐜, 0. Furthermore, fig. 3(B) depicts full-wave three-level improved inverter topology with
output voltage of 0,
𝐕 𝐝𝐜
𝟐
, and 𝐕𝐝𝐜. Thus, the proposed inverter synthesizes one and half levels of the dc bus
voltage. To obtain the maximum positive output voltage 𝐕𝐚𝟎 = 𝑽 𝒅𝒄, 𝑺 𝟏 is turned ON, to obtain the half-positive
output voltage 𝐕𝐚𝟎 =
𝐕 𝐝𝐜
𝟐
, 𝑺 𝒂 is turned ON and, 𝐕𝐚𝟎 = 0, when 𝑺 𝟐 is turned ON. If diodes with same voltage
rating as the active devices are used, the number of required diodes for each phase will be 2(2n-3) and the
number of power switches are given by n, where n is the number of the inverter output voltage level.
III. THREE-PHASE ASYNCHRONOUS MOTOR
Asynchronous machines are widely used in industries. Induction motors have their characteristic during
starting and fault conditions [8]. At this study a kind of squirrel cage asynchronous machine from the library of
MATLAB/Sims Power is used as a load for our multilevel inverters. Synchronous speed of Asynchronous
Motor varies directly proportional to the supply frequency. Hence, by changing the frequency, the synchronous
speed and the motor speed can be controlled below and above the normal full load speed. The voltage induced
in the stator, E is directly proportional to the product of slip frequency and air gap flux. The Asynchronous
Motor terminal voltage can be considered proportional to the product of the frequency and flux, if the stator
voltage is neglected. Any reduction in the supply frequency without a change in the terminal voltage causes an
increase in the air gap flux. Asynchronous motors are designed to operate at the knee point of the magnetization
characteristic to make full use of the magnetic material. Therefore the increase in flux will saturate the motor.
This will increase the magnetizing current, distort the line current and voltage, increase the core loss and the
stator copper loss, and produce a high pitch acoustic noise. While any increase in flux beyond rated value is
undesirable from the consideration of saturation effects, a decrease in flux is also avoided to retain the torque
capability of the motor. Therefore, the pulse width modulation (PWM) control below the rated frequency is
generally carried out by reducing the machine phase voltage, V, along with the frequency in such a manner that
the flux is maintained constant. Above the rated frequency, the motor is operated at a constant voltage because
of the limitation imposed by stator insulation or by supply voltage limitations [9]. In this paper split-phase
single-phase Asynchronous Motor is used as inverter load throughout the simulation process.
Fig. 4. Split-phase Single-phase Asynchronous Motor.
A three-phase symmetrical induction motor upon losing one of its stator phase supplies while running
may continue to operate as essentially a single-phase motor with the remaining line-to-line voltage across the
other two connected phases. When the main winding coil is connected in parallel with ac voltage, as in the split-
phase single-phase asynchronous motor of fig. 4, the current of the auxiliary winding, 𝒊 𝒅𝒔, leads 𝒊 𝒒𝒔 of the main
winding. For even a larger single-phase induction motor, that lead can be further increased by connecting a
capacitor in series with the auxiliary winding, this arrangement brings about a Capacitor-start single-phase
asynchronous motor. Fig. 4 shows that the motor has two windings: the main (running) winding and the
auxiliary (starting) winding. This motor is modeled in two parts: Electrical part which is represented by a
fourth-order state-space model and, mechanical part which is represented by second-order system. All electrical
variables and parameters are referred to the stator. This is indicated by the prime signs in the machine equations
given below. All stator and rotor quantities are in the stator reference frame (d-q frame).
Electrical System Part Analysis:
5. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 28 | P a g e
Fig. 5 Main winding (q-axis) circuit diagram
𝐕𝐪𝐬 = 𝐑 𝐬 𝐢 𝐪𝐬 +
𝐝
𝐝𝐭
𝛗 𝐪𝐬 (3)
Where, 𝛗 𝐪𝐬 = 𝐋𝐥𝐬 + 𝐋 𝐦𝐬 𝐢 𝐪𝐬 + 𝐋 𝐦𝐬 𝐢′
𝐪𝐫
𝐕′
𝐪𝐫 = 𝐑′
𝐫 𝐢′
𝐪𝐫 +
𝐝
𝐝𝐭
𝛗′
𝐪𝐫
−
𝐍 𝐬
𝐍𝐬
𝛚 𝐫 𝛗′
𝐝𝐫
(4)
Where, 𝝋′
𝒒𝒓
= 𝐋′
𝐥𝐫 + 𝐋 𝐦𝐬 𝐢′
𝐪𝐫 + 𝐋 𝐦𝐬 𝐢 𝐪𝐬
Fig. 6 Auxiliary winding (d-axis) circuit diagram
𝐕𝐝𝐬 = 𝐑 𝐒 𝐢 𝐝𝐬 +
𝐝
𝐝𝐭
𝛗 𝐝𝐬 (5)
Where, 𝝋 𝒅𝒔 = 𝐋𝐥𝐒 + 𝐋 𝐦𝐒 𝐢 𝐝𝐬 + 𝐋 𝐦𝐒 𝐢′
𝐝𝐫
𝐕′
𝐝𝐫 = 𝐑′
𝐑 𝐢′
𝐝𝐫 +
𝐝
𝐝𝐭
𝛗′
𝐝𝐫
+
𝐍𝐬
𝐍 𝐬
𝛚 𝐫 𝛗′
𝐪𝐫
(6)
Where, 𝝋′
𝒅𝒓
= 𝐋′
𝐥𝐑 + 𝐋 𝐦𝐒 𝐢′
𝐝𝐫 + 𝐋 𝐦𝐒 𝐢 𝐝𝐬
𝐓𝐞 = 𝐩(
𝐍𝐬
𝐍 𝐬
𝛗′
𝐪𝐫
𝐢′
𝐝𝐫 −
𝐍 𝐬
𝐍𝐬
𝛗′
𝐝𝐫
𝐢′
𝐪𝐫) (7)
Mechanical System part Analysis
𝒅
𝒅𝒕
𝝎 𝐦 =
𝟏
𝟐𝑯
(𝑻 𝒆 − 𝑭𝝎 𝐦 − 𝑻 𝑳) (8)
𝒅
𝒅𝒕
𝛉 𝐦 = 𝝎 𝐦 (9)
It is vital to note that the reference frame fixed in the stator is used to convert voltages and currents to the dq
frame, this enables for easier model analysis of the system. The following relationships describe the ab-to-dq
frame transformations applied to the single phase asynchronous machine.
𝐟 𝐪𝐬
𝐟 𝐝𝐬
=
𝟏 𝟎
𝟎 −𝟏
𝐟 𝐚𝐬
𝐟 𝐛𝐬
(10)
𝐟 𝐪𝐫
𝐟 𝐝𝐫
=
𝐜𝐨𝐬𝛉 𝐫 −𝐬𝐢𝐧𝛉 𝐫
−𝐬𝐢𝐧𝛉 𝐫 −𝐜𝐨𝐬𝛉 𝐫
𝐟 𝐚𝐫
𝐟 𝐛𝐫
(11)
The variable f can represent either voltage, current or flux linkage. The single phase asynchronous machine
block parameters as shown in fig. 7 are defined as follows (all quantities are referred to the stator):
Table 1 Definition Of Symbols In Asynchronous Motor Model
Para-
meters
Definitions units
𝐑 𝐬, 𝐋𝐥𝐬 Main winding stator resistance and leakage
inductance
𝛀 𝒂𝒏𝒅 H𝐑 𝐒, 𝐋𝐥𝐒 Auxiliary winding stator resistance and leakage
6. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 29 | P a g e
inductance
𝐑′
𝐫, 𝐋′
𝐥𝐫 Main winding rotor resistance and leakage
inductance
𝐑′
𝐑, 𝐋′
𝐥𝐑 Auxiliary winding rotor resistance and leakage
inductance
𝐋 𝐦𝐬 Main winding magnetizing inductance H
𝐋 𝐦𝐒 Auxiliary winding magnetizing inductance
𝐕𝐚𝐬, 𝐢 𝐚𝐬
𝐕𝐛𝐬, 𝐢 𝐛𝐬
𝐕𝐪𝐬, 𝐢 𝐪𝐬
𝐕𝐝𝐬, 𝐢 𝐝𝐬
𝐕′
𝐪𝐫, 𝐢′
𝐪𝐫
𝐕′
𝐝𝐫, 𝐢′
𝐝𝐫
Main winding stator voltage and current
Auxiliary winding stator voltage and current
q-axis stator voltage and current
d-axis stator voltage and current
q-axis rotor voltage and current
d-axis rotor voltage and current
V and A
𝛗 𝐪𝐬, 𝛗 𝐝𝐬 Stator q and d-axis fluxes V.s
𝛗′
𝐪𝐫
, 𝛗′
𝐝𝐫
Rotor q and d-axis fluxes V.s
𝛚 𝐦 Rotor angular velocity Rad/sec
𝜽 𝒎 Rotor angular position rad
p Number of pair poles
𝝎 𝒓 Electrical angular velocity (𝝎 𝒓 ∗ 𝒑) Rad/sec
𝜽 𝒓 Electrical rotor angular position ( 𝜽 𝒓 ∗ 𝒑) rad
𝑻 𝒆 Electromagnetic torque Nm
𝑻 𝒎 Shaft mechanical torque Nm
J Combined rotor and load inertia coefficient.
Set to infinite to simulate locked rotor
Kg.m^2
F Combined rotor and load viscous friction
coefficient
Nms
H Combined rotor and load inertia constant.
Set to infinite to simulate locked rotor
sec
Ns Number of auxiliary winding‟s effective turns turns
𝑵 𝒔 Number of main winding‟s effective turns Turns
Fig. 7 A three-phase Squirrel-cage asynchronous motor parameter.
7. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 30 | P a g e
IV. MATLAB SIMULINK SIMULATION RESULTS
Multilevel inverter fed asynchronous motor drive is implemented in MATLAB/ SIMULINK which is
shown in fig. 8. The MATLAB/ SIMULINK model of diode clamped and improved three-phase multilevel
inverter using three-level configuration topology is shown in fig. 8. The logic algorithm for firing each of the
circuit topology is embedded in the logic circuit and also different inverter configurations are also embedded in
the diagram with a name as multilevel invereter topology. Voltmeter is attached between the inverter output
terminal and motor input terminal, this helps to measure the inverter ouput readings and machine input voltages.
Fig. 8 Matlab/Simulink model of Multilevel Asynchronous Motor drive.
Diode clamped three phase three-level inverter output voltage after feeding to synchronous motor is
shown in fig. 9. The stator main and rotor winding output currents with respect to three-phase are shown in fig.
10. The variation of speed and torque are also shown. The inverter output voltage which serves as the machine
input voltage is also plotted in fig.10. The machine starts at no load and then at t=0.20secs, once the machine
has reached its steady state, the load torque is increased to its nominal value (10 N.m) in 1.0 sec. The speed
increases and settles at 1500 rpm without torque load and drops to 1450 rpm when loaded with torque load.
Fig. 9 Matlab/Simulink model of Diode clamped Three-phase Three-level Inverter.
powergui
Discrete,
Ts= 5e-005 s.
Wm
Vtri 2
Vtri1
Vref 2
Vref1
Vref
Three -Phase
V-I Measurement
Vabc
A
B
C
a
b
c
Te
TL =10 Nm
Stator
Current
Rotor
Current
Ouput Inverter
Voltages
Multilevel
Inverter topology
Leg A firing signals
Leg B firing signals
Leg C firing signal
Positive terminal
Negative Terminal
Va
Vb
Vc
Logic circuit
for firing signal
sin(theta)
sin(theta-120)
Asin(theta-240)
Triangular2
Triangular1
ga
gb
gc Gain
-K-
DC Voltage
Source
Asynchronous Machine
SI Units squirrel cage
Rating 5.4HP, 400 V,
50Hz,1500 rpm .
Tm
m
A
B
C
<Stator current is _a (A)>
<Stator current is _b (A)>
<Electromagnetic torque Te (N*m)>
<Rotor current ir _a (A)>
<Rotor current ir _b (A)>
<Rotor current ir _c (A)>
<Stator current is _c (A)>
<Rotor speed (wm)>
Sc2
g
C
E
Sc1
g
C
E
Sb 2
g
C
E
Sb 1
g
C
E
Sa2
g
C
E
Sa1
g
C
E
NotSc 2
g
C
E
NotSc 1
g
C
E
NotSb 2
g
C
E
NotSb 1
g
C
E
NotSa 2
g
C
E
NotSa 1
g
C
E
NotDa 1
From 9
[ga 2]
From 8
[ga 1]
From 7
NOTgb 2]
From 6
NOTgb 1]
From 5
[gb 2]
From 4
[gb 1]
From 3
NOTgc 2]
From 2
NOTgc 1]
From 11
NOTga 2]
From 10
NOTga 1]
From 1
[gc2]
From
[gc 1]
Diode 5Db1Da1
DC Voltage
Source
D1D
C2
C1
Asynchronous Machine
SI Units
Tm
m
A
B
C
8. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 31 | P a g e
Fig. 10a Diode Clamped Multilevel Inverter Topology Simulation Results.
Fig. 10b A Waveform for Torque versus Rotor Speed
An Improved three phase three-level inverter output voltage after feeding to asynchronous motor is
shown in fig. 11. The stator main and rotor winding output currents with respect to three-phase are shown in fig.
12. The variation of speed and torque are also shown. The inverter output voltage which serves as the machine
input voltage is also plotted in fig.12. The machine starts at no load and then at t=2.0secs, once the machine has
reached its steady state, the load torque is increased to its nominal value (10 N.m) in 1.0 sec. The speed
increases and settles at 1500 rpm without torque load and drops to 1450 rpm when loaded with torque load.
0 0.5 1 1.5 2
-60
-40
-20
0
20
40
Time (secs)
RotorCurrentIra
(A)
Graph of Phase A Rotor Current
0 0.5 1 1.5 2
-40
-20
0
20
40
60
Time(secs)
StatorcurrentIsa
(A)
Graph of Phase A Stator current
0 0.5 1 1.5 2
0
500
1000
1500
2000
Time (secs)
RotorSpeed(rpm)
Graph of Rotor Speed
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
RotorCurrentIrb
(A)
Graph of Phase B Rotor Current
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
StatorCurrentIsb
(A)
Graph of Phase B Stator Current
0 0.5 1 1.5 2
-20
0
20
40
Time(secs)
Torque(N-m)
Graph of Electromagnetic Torque(N.m)
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
RotorcurrentIrc
(A)
Graph of Phase C Rotor current
0 0.5 1 1.5 2
-40
-20
0
20
40
Time(secs)
StatorCurrentIsc
(A)
Graph of Phase C Stator Current(A)
0 0.01 0.02 0.03 0.04 0.05 0.06
-500
0
500
Time(secs)
MotorInputVoltages(V)
Graph of Inverter Output Voltages
Va
Vb
Vc
0 200 400 600 800 1000 1200 1400 1600
-10
-5
0
5
10
15
20
25
30
35
40
Rotor Speed (RPM)
Torque(Nm)
Graph of Torque versus Rotor-Speed
9. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 32 | P a g e
Fig. 11 Matlab/Simulink model of An Improved Three-phase Three-level Inverter.
Fig. 12a An Improved Multilevel inverter topology simulation results.
powergui
Discrete,
Ts= 5e-005 s.
Scc
g
C
E
Sc2
g
C
E
Sc1
g
C
E
Sb2
g
C
E
Sb 1
g
C
E
Sb
g
C
E
Sa 2 g
C
E
Sa1
g
C
E
Sa
g
C
E
From 8
[g5 ]
From 7
[g6]
From 6
[g4 ]
From 5
[g3 ]
From 4
[g2 ]
From 3
[g1 ]
From 2
[gc]
From1
[gb ]
From
[ga ]
DC Voltage
Source
D8
D7D6
D5
D4
D3
D2
D14
D13
D12
D11
D1
C2
C1
Asynchronous Machine
SI Units
Tm
m
A
B
C
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
RotorCurrentIra
(A)
Graph of Phase A Rotor Current
0 0.5 1 1.5 2
-40
-20
0
20
40
60
Time(secs)
StatorcurrentIsa
(A)
Graph of Phase A Stator current
0 0.5 1 1.5 2
0
500
1000
1500
2000
Time (secs)
RotorSpeed(rpm)
Graph of Rotor Speed
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
RotorCurrentIrb
(A)
Graph of Phase B Rotor Current
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
StatorCurrentIsb
(A)
Graph of Phase B Stator Current
0 0.5 1 1.5 2
-10
0
10
20
30
40
Time(secs)
Torque(N-m)
Graph of Electromagnetic Torque(N.m)
0 0.5 1 1.5 2
-40
-20
0
20
40
Time (secs)
RotorcurrentIrc
(A)
Graph of Phase C Rotor current
0 0.5 1 1.5 2
-40
-20
0
20
40
Time(secs)
StatorCurrentIsc
(A)
Graph of Phase C Stator Current(A)
0 0.01 0.02 0.03 0.04 0.05 0.06
-600
-400
-200
0
200
400
Time(secs)
MotorInputVoltages(V)
Graph of Inverter Output Voltages
Va
Vb
Vc
10. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 33 | P a g e
Fig. 12b Waveform for Torque versus Rotor Speed
4.1 NUMBER OF COMPONENT COUNT.
The number of required three-phase multilevel inverter components according to output voltage levels
(N) is illustrated in table 2. Analysis from Table 2 clearly shows that the numbers of components in this
proposed configuration are lower than any other configuration.
Table 2: NUMBER OF COMPONENTS FOR THREE-PHASE MULTILEVEL INVERTER
Inverter
Type/comp
onents
Diode
Clamped
Flying
Capacit
or
Cascaded
H-bridge
Improv
ed
Main
Switches
𝟑(𝟑𝐍 − 𝟓) 𝟑(𝟑𝐍
− 𝟓)
𝟑(𝟑𝐍
− 𝟓)
𝟑𝐍
Main
Diodes
𝟑(𝟑𝐍 − 𝟓) 𝟑(𝟑𝐍
− 𝟓)
𝟑(𝟑𝐍
− 𝟓)
6
Clamping
Diodes
𝟔(𝐍 − 𝟐) 0 0 𝟏𝟐(𝐍
− 𝟐)
DC bus
Capacitor/i
solate
supplies
𝐍 − 𝟏 1 𝐍 − 𝟏 𝐍 − 𝟏
Flying
capacitors
0 𝟐(𝐍
− 𝟐)
0 0
Total
Numbers
𝟐(𝟏𝟕𝐍
− 𝟐𝟔)
𝟐𝟎𝐍
− 𝟑𝟑
𝟏𝟗𝐍
− 𝟑𝟏
𝟏𝟔𝐍
− 𝟕
0 200 400 600 800 1000 1200 1400 1600
-5
0
5
10
15
20
25
30
35
40
Rotor Speed (RPM)
Torque(Nm)
Graph of Torque versus Rotor-Speed
11. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 34 | P a g e
Fig. 13 required components for multi-level inverter in different topology.
V. CONCLUSION
The Diode clamped and Improved multilevel inverter topologies were simulated in MATLAB
simulation platform and their output performances were obtained. The circuit performance was tested by three-
phase asynchronous motor load. It was observed that their outputs displayed similar performance. In the
required circuit components count, it is also observed that the Improved inverter topology shows significantly
reduced number of component count, when compared with other inverter topologies. As a result of this the cost,
weight and size of the improved inverter power circuit has to be reduced.
REFERENCE
[1] J. S. Lai and F. Z. Peng, “Multilevel converters–A new breed of power converters,” IEEE Trans. Ind.
Applicat., vol. 32, pp. 509–517, May/June 1996.
[2] L. Tolbert, F.-Z. Peng, and T. Habetler, “Multilevel converters for large electric drives,” IEEE Trans. Ind.
Applicat., vol. 35, pp. 36–44, Jan./Feb. 1999.
[3] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point clamped PWM inverter,” IEEE Trans. Ind.
Applicat., vol. IA-17, pp. 518–523, Sept./Oct. 1981.
[4] T. A. Meynard and H. Foch, “Multi-level choppers for high voltage applications,” Eur. Power Electron.
Drives J., vol. 2, no. 1, p. 41, Mar.1992.
[5] P. Hammond, “A new approach to enhance power quality for medium voltage ac drives,” IEEE Trans.
Ind. Applicat., vol. 33, pp. 202–208, Jan./Feb. 1997.
[6] Qiang, S. and L. Wenhua,‟ Control of a cascade statcom with star configuration under unbalanced
conditions‟. IEEE T. Power Electr., 24(1): 45-58, 2009.
[7] José, R., L. Jih-Sheng and Z.P. Fang, „Multilevel inverters: A survey of topologies, controls and
applications‟. IEEE T. Power Electr., 49(4): 724-738. 2002.
[8] Hagiwara, M., K. Nishimura and H. Akagi, A medium-voltage motor drive with a modular multilevel
PWM inverter. IEEE T. Power Electr., 25(7): 1786-1799, 2010.
[9] S. Manasa, S. Balajiramakrishna, S. Madhura and H. M Mohan, “Design and Simulation of three Phase
five level and seven level inverter fed induction motor drive with two cascaded H-bridge configuration”
International Journal of electrical and electronics Engineering (IJEEE), ISSN(Print): 2231-5284 Vol-1
Iss-4, 2012.
APPENDIX
FIG.8 LOGIC FIRING SIGNALS
function [ga1,ga2,gb1,gb2,gc1,gc2]=
fcn(SIN,SIN1,SIN2,T1,T2)
if (SIN >T1)
ga1=1;
else
ga1=0;
end
if (SIN >T2)
ga2=1;
else
ga2=0;
end
%Phase b programme
%SIN1=(SIN-2*pi/3);
if (SIN1 >T1)
gb1=1;
0 5 10 15 20 25 30 35 40 45 50
0
200
400
600
800
1000
1200
1400
1600
1800
Numberofcomponentcount
Numberofthree-phasecomponentcount
Diode
Flying
Cascaded
Improved
12. Design And Simulation Of Three-Phase Diode Clamped And Improved Inverter Fed Asynchronous Motor Drive
International organization of Scientific Research 35 | P a g e
else
gb1=0;
end
if (SIN1 >T2)
gb2=1;
else
gb2=0;
end
% phase c programme
%SIN2=(SIN-4*pi/3);
if (SIN2 >T1)
gc1=1;
else
gc1=0;
end
if (SIN2 >T2)
gc2=1;
else
gc2=0;
end
FIG.10a SIMULATION RESULT
x=Xout;
T=x(:,1);
figure(1)
subplot(3,3,1)
plot(T,x(:,2),'r')
xlabel('Time (secs)')
ylabel('Rotor Current Ir_a(A)')
title('Graph of Phase A Rotor Current')
grid on
subplot(3,3,2)
plot(T,x(:,5),'r')
xlabel('Time(secs)')
ylabel('Stator current Is_a(A)')
title('Graph of Phase A Stator current')
grid on
subplot(3,3,3)
plot(T,x(:,8),'k','linewidth',2.0)
xlabel('Time (secs)')
ylabel('Rotor Speed(rpm)')
title('Graph of Rotor Speed')
grid on
subplot(3,3,4)
plot(T,x(:,3),'b')
xlabel('Time (secs)')
ylabel('Rotor Current Ir_b(A)')
title('Graph of Phase B Rotor Current')
grid on
subplot(3,3,5)
plot(T,x(:,6),'b')
xlabel('Time (secs)')
ylabel('Stator Current Is_b(A)')
title('Graph of Phase B Stator Current')
grid on
subplot(3,3,6)
plot(T,x(:,9),'k','LineWidth',2.0')
xlabel('Time(secs)')
ylabel('Torque (N-m)')
title('Graph of Electromagnetic Torque(N.m)')
grid on
subplot(3,3,7)
plot(T,x(:,4),'m')
xlabel('Time (secs)')
ylabel('Rotor current Ir_c(A)')
title('Graph of Phase C Rotor current')
grid on
subplot(3,3,8)
plot(T,x(:,7),'m')
xlabel('Time(secs)')
ylabel('Stator Current Is_c(A)')
title('Graph of Phase C Stator Current(A)')
grid on
subplot(3,3,9)
plot(T,x(:,10),':r','linewidth',2)
xlabel('Time(secs)')
ylabel('Motor Input Voltages(V)')
title('Graph of Inverter Output Voltages')
grid on
hold on
plot(T,x(:,11),'-.b','linewidth',2)
hold on
plot(T,x(:,12),'m','linewidth',2)
Legend('Va','Vb','Vc')
figure(2)
plot(x(:,8),x(:,9),'r','linewidth',1)
xlabel('Rotor Speed (RPM)')
ylabel('Torque (Nm)')
title('Graph of Torque versus Rotor-Speed')
grid on