This document describes a low power delay buffer circuit that uses several techniques to reduce power consumption. It uses a ring counter addressing scheme with double-edge triggered flip-flops to reduce the clock frequency in half. It also proposes a novel gated clock driver tree to reduce activity on the clock distribution network. The gated driver tree idea is also applied to the input and output ports of the memory block to decrease loading and further reduce power. Simulation results show the effectiveness of these techniques in reducing power consumption for the delay buffer circuit.