The document describes a proposed design for a low power implicit pulse triggered flip-flop (P-FF). P-FFs have advantages over conventional master-slave FFs in high-speed applications and can reduce clock power consumption. The proposed design uses only transistor switching logic with 8 transistors, reducing power and area compared to other P-FF designs. Simulations show the proposed design has lower power consumption of 2.339μW compared to other designs. The design achieves lower power and area through a reduced transistor count.