This document summarizes a universal digital converter family for software radio applications. It offers two front-end configurations: wide-band direct sampling and narrow-band channelized. In wide-band mode, samples are available through a FIFO for FPGA/DSP processing. In narrow-band mode, DDC/DUC chips are used to select channels and reduce bandwidth. The family includes products with up to 4 or 16 channels that sample at 80Msps with 14-bit resolution and 500MHz bandwidth, and interface with FPGAs and PCI buses. Open APIs and sample code are provided for developers.

1. Digital Converters
Universal digital converter family for wide-band and phased array software radio applications
Front-end
BUS
CH4
Sampling
CLK
for converters
FPGA
LOGIC and DSP
resource
SCLK OSC
10MHz
CLK DRV
X2/X4/X8 Sampling
CLK
External
TRG in/out
PCI
HOST
Interface
LCLK OSC
33MHz
External
CLK
in/out
Dedicated
data
connection
FPGA
Analog
driver
DAC
Analog
preamp
ADC
Local
CLK
PCI BUS connector
The members of the converter product family are based on the same
digital back-end base structure. We offer two basic conversion frontend structure for wide-band and channelised applications.
FIFO
FPGA
In wide-band the samples are available trough a FIFO for the
FPGA/DSP processing elements
RX
CH3
FIFO
Full bandwidth
FPGA CFG
Control
BUS
ADC
Config
EEPROM
DDC
FPGA
Reduced bandwidth
TX
CH2
MCU
TX
Different
conversion
front-end
configurations
Analog
preamp
Analog
driver
DAC
DUC
FPGA
NARROW-BAND
(Channelized)
RS-232
serial control
interface
I2C
WIDE-BAND
(Direct sampled)
PROM FPGA
JTAG JTAG
RX
Control
EEPROM
CH1
In narrow-band (channelised) version DDC/DUC chips are used for
selecting the required channel and reduce the bandwidth
Members of the converter family
DCU-214:
DCUMax. 4 analog I/O channels
Max. 2 independent channels
1 clock I/O channel
80Msps/14bit sampling
500MHz bandwidth
Xilinx Spartan II FPGA
32bit/33MHz PCI interface
133Mbyte/sec signaling rate
DCU-214:
DCUMax. 4 analog I/O channels
Max. 4 independent digital tuner
1 clock I/O channel
80Msps/14bit sampling
500MHz bandwidth
Xilinx Spartan II FPGA
32bit/33MHz PCI interface
133Mbyte/sec signaling rate
DCU-304:
DCUMax. 4 analog I/O channels
1 clock I/O channel
80Msps/14bit sampling
500MHz bandwidth
80 bit front-end bus
frontXilinx Virtex II FPGA
64bit/66MHz PCI interface
528Mbyte/sec signaling rate
DRU-304:
DRUMax. 16 independent analog
I/O channels
1 clock I/O channel
80Msps/14bit sampling
500MHz bandwidth
Xilinx Virtex II FPGA
Max. 16 independent
digital tuner
Software support
Open application Programming Interface (API) and sample code are
available for developers
www.sagax.hu
Matlab based time and frequency domain analiser tool
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Ltd.
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111096 Budapest, HUNGARY