CS304PC:Computer Organization
and Architecture (R18 II(I sem))
Department of computer science and engineering (AI/ML)
Session 31
by
Asst.Prof.M.Gokilavani
VITS
3/21/2023 Department of CSE (AI/ML) 1
TEXTBOOK:
• 1. Computer System Architecture – M. Moris Mano,
Third Edition, Pearson/PHI.
REFERENCES:
• Computer Organization – Car Hamacher, Zvonks
Vranesic, Safea Zaky, Vth Edition, McGraw Hill.
• Computer Organization and Architecture – William
Stallings Sixth Edition, Pearson/PHI.
• Structured Computer Organization – Andrew S.
Tanenbaum, 4th Edition, PHI/Pearson.
3/21/2023 Department of CSE (AI/ML) 2
Unit V
Reduced Instruction set computer: CISC
characteristics, RISC characteristics.
Pipeline and vector processing: parallel processing,
pipelining, Arithmetic pipeline, instruction pipeline,
RISC pipeline, vector processing, array processing.
Multi Processors: Characteristics of multiprocessors,
interconnection structures, Interprocessors arbitration,
Interprocessors communication and synchronization,
cache coherence.
3/21/2023 Department of CSE (AI/ML) 3
Topics covered in session 30
3/21/2023 Department of CSE (AI/ML) 4
•Reduced Instruction set computer
•Pipeline and vector processing
•Multi Processors
Introduction
• Multiprocessor system is an interconnection of
two or more CPUs with memory and input-output
equipment
• The components that forms multiprocessor are
CPUs IOPs connected to input –output devices ,
and memory unit that may be partitioned into a
number of separate modules.
• Multiprocessor are classified as
• multiple instruction stream
• multiple data stream (MIMD) system.
3/21/2023 5
Department of CSE (AI/ML)
Why Choose a Multiprocessor?
• A single CPU can only go so fast, use more
than one CPU to improve performance
• Multiple users
• Multiple applications
• Multi-tasking within an application
• Responsiveness and/or throughput
• Share hardware between CPUs
3/21/2023 6
Department of CSE (AI/ML)
What you the difference between
Multiprocessor and Multicomputer?
3/21/2023 7
Department of CSE (AI/ML)
How multiprocessor are classified?
• Multiprocessor are classified by the way their
memory is organized, mainly it is classified into two
types
• Tightly coupled multiprocessor
• Loosely coupled multiprocessor
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Department of CSE (AI/ML)
Tightly coupled Multiprocessor
• A multiprocessor is a tightly coupled computer system
having two or more processing units (Multiple
Processors) each sharing main memory and
peripherals, in order to simultaneously process
programs.
• Tightly coupled Multiprocessor is also know as shared
memory system.
Loosely-coupled multiprocessor
• Loosely-coupled multiprocessor systems (often referred
to as clusters ) are based on multiple standalone single
or dual processor commodity computers interconnected
via a high speed communication system.
• Loosely-coupled multiprocessor is also known as
distributed memory.
• Example: A Linux beowulf cluster
3/21/2023 9
Department of CSE (AI/ML)
Difference b/w Tightly coupled and
Loosely coupled multiprocessor
Tightly coupled
3/21/2023 10
Department of CSE (AI/ML)
Interconnection Structures
• The physical forms for establishing an
interconnection network .
• Time shared common bus.
• Multiport memory.
• Crossbar switch
• Multistage switching network.
• Hypercube system.
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Department of CSE (AI/ML)
Time –shared common bus
• A system common bus multiprocessor system
consists of a number of processors connected through
path to a memory unit.
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Department of CSE (AI/ML)
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Multiport Memory
• A multiport memory system employs separate buses
between each memory module and each CPU.
3/21/2023 14
Department of CSE (AI/ML)
Cross bar switch
• The crossbar switch organization consists of a
number of cross points that are placed at
intersections between processor buses and
memory modules parts.
• The small Square in each cross point is a
switch that determines the path from a
processor to a memory module.
3/21/2023 Department of CSE (AI/ML) 15
Cross bar switch
3/21/2023 Department of CSE (AI/ML) 16
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Multistage switching Network
• The basic component of a multistage network is a
two- input , two- output interchange switch.
• There are control sign associated with switch that
establish the interconnection between the input and
output terminals.
• The switch has the capability connecting input A to
either of the outputs.
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Department of CSE (AI/ML)
Multistage switching Network
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Department of CSE (AI/ML)
3/21/2023 Department of CSE (AI/ML) 20
Hypercube Interconnection
• The hypercube or binary n-cube multiprocessor
structure is loosely coupled system composed of
N=2n processor interconnected in an n-
dimensional binary cube.
• Hyper cube structures for n = 1,2,3.
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Department of CSE (AI/ML)
Hypercube Interconnection
3/21/2023 Department of CSE (AI/ML) 22
Interprocessors arbitration
• Arbitration logic resolves bus conflict
• It would be the part of system bus controller
• Arbitration procedures services all processor
requests on the basis of established priorities.
• Two types
– Serial Arbitration procedure
– Parallel Arbitration procedure
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Serial Arbitration procedure
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Department of CSE (AI/ML)
Parallel Arbitration procedure
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Department of CSE (AI/ML)
Dynamic Arbitration Algorithm
3/21/2023 26
Department of CSE (AI/ML)
Topics to be covered in next session 32
• Interprocessors communication and
synchronization
3/21/2023 Department of CSE (AI/ML) 27
Thank you!!!

CS304PC:Computer Organization and Architecture Session 31 Multiprogramming.pptx

  • 1.
    CS304PC:Computer Organization and Architecture(R18 II(I sem)) Department of computer science and engineering (AI/ML) Session 31 by Asst.Prof.M.Gokilavani VITS 3/21/2023 Department of CSE (AI/ML) 1
  • 2.
    TEXTBOOK: • 1. ComputerSystem Architecture – M. Moris Mano, Third Edition, Pearson/PHI. REFERENCES: • Computer Organization – Car Hamacher, Zvonks Vranesic, Safea Zaky, Vth Edition, McGraw Hill. • Computer Organization and Architecture – William Stallings Sixth Edition, Pearson/PHI. • Structured Computer Organization – Andrew S. Tanenbaum, 4th Edition, PHI/Pearson. 3/21/2023 Department of CSE (AI/ML) 2
  • 3.
    Unit V Reduced Instructionset computer: CISC characteristics, RISC characteristics. Pipeline and vector processing: parallel processing, pipelining, Arithmetic pipeline, instruction pipeline, RISC pipeline, vector processing, array processing. Multi Processors: Characteristics of multiprocessors, interconnection structures, Interprocessors arbitration, Interprocessors communication and synchronization, cache coherence. 3/21/2023 Department of CSE (AI/ML) 3
  • 4.
    Topics covered insession 30 3/21/2023 Department of CSE (AI/ML) 4 •Reduced Instruction set computer •Pipeline and vector processing •Multi Processors
  • 5.
    Introduction • Multiprocessor systemis an interconnection of two or more CPUs with memory and input-output equipment • The components that forms multiprocessor are CPUs IOPs connected to input –output devices , and memory unit that may be partitioned into a number of separate modules. • Multiprocessor are classified as • multiple instruction stream • multiple data stream (MIMD) system. 3/21/2023 5 Department of CSE (AI/ML)
  • 6.
    Why Choose aMultiprocessor? • A single CPU can only go so fast, use more than one CPU to improve performance • Multiple users • Multiple applications • Multi-tasking within an application • Responsiveness and/or throughput • Share hardware between CPUs 3/21/2023 6 Department of CSE (AI/ML)
  • 7.
    What you thedifference between Multiprocessor and Multicomputer? 3/21/2023 7 Department of CSE (AI/ML)
  • 8.
    How multiprocessor areclassified? • Multiprocessor are classified by the way their memory is organized, mainly it is classified into two types • Tightly coupled multiprocessor • Loosely coupled multiprocessor 3/21/2023 8 Department of CSE (AI/ML)
  • 9.
    Tightly coupled Multiprocessor •A multiprocessor is a tightly coupled computer system having two or more processing units (Multiple Processors) each sharing main memory and peripherals, in order to simultaneously process programs. • Tightly coupled Multiprocessor is also know as shared memory system. Loosely-coupled multiprocessor • Loosely-coupled multiprocessor systems (often referred to as clusters ) are based on multiple standalone single or dual processor commodity computers interconnected via a high speed communication system. • Loosely-coupled multiprocessor is also known as distributed memory. • Example: A Linux beowulf cluster 3/21/2023 9 Department of CSE (AI/ML)
  • 10.
    Difference b/w Tightlycoupled and Loosely coupled multiprocessor Tightly coupled 3/21/2023 10 Department of CSE (AI/ML)
  • 11.
    Interconnection Structures • Thephysical forms for establishing an interconnection network . • Time shared common bus. • Multiport memory. • Crossbar switch • Multistage switching network. • Hypercube system. 3/21/2023 11 Department of CSE (AI/ML)
  • 12.
    Time –shared commonbus • A system common bus multiprocessor system consists of a number of processors connected through path to a memory unit. 3/21/2023 12 Department of CSE (AI/ML)
  • 13.
  • 14.
    Multiport Memory • Amultiport memory system employs separate buses between each memory module and each CPU. 3/21/2023 14 Department of CSE (AI/ML)
  • 15.
    Cross bar switch •The crossbar switch organization consists of a number of cross points that are placed at intersections between processor buses and memory modules parts. • The small Square in each cross point is a switch that determines the path from a processor to a memory module. 3/21/2023 Department of CSE (AI/ML) 15
  • 16.
    Cross bar switch 3/21/2023Department of CSE (AI/ML) 16
  • 17.
  • 18.
    Multistage switching Network •The basic component of a multistage network is a two- input , two- output interchange switch. • There are control sign associated with switch that establish the interconnection between the input and output terminals. • The switch has the capability connecting input A to either of the outputs. 3/21/2023 18 Department of CSE (AI/ML)
  • 19.
    Multistage switching Network 3/21/202319 Department of CSE (AI/ML)
  • 20.
  • 21.
    Hypercube Interconnection • Thehypercube or binary n-cube multiprocessor structure is loosely coupled system composed of N=2n processor interconnected in an n- dimensional binary cube. • Hyper cube structures for n = 1,2,3. 3/21/2023 21 Department of CSE (AI/ML)
  • 22.
  • 23.
    Interprocessors arbitration • Arbitrationlogic resolves bus conflict • It would be the part of system bus controller • Arbitration procedures services all processor requests on the basis of established priorities. • Two types – Serial Arbitration procedure – Parallel Arbitration procedure 3/21/2023 23 Department of CSE (AI/ML)
  • 24.
    Serial Arbitration procedure 3/21/202324 Department of CSE (AI/ML)
  • 25.
    Parallel Arbitration procedure 3/21/202325 Department of CSE (AI/ML)
  • 26.
    Dynamic Arbitration Algorithm 3/21/202326 Department of CSE (AI/ML)
  • 27.
    Topics to becovered in next session 32 • Interprocessors communication and synchronization 3/21/2023 Department of CSE (AI/ML) 27 Thank you!!!