The document provides design details for a critical conduction mode power factor correction (PFC) circuit using the TB6819AFG controller IC. It includes the application circuit, design specifications, equations for determining component values like the output inductor L1, input capacitor C1, and output capacitor C2. It also describes the use of time scaling to speed up transient simulations and modeling of the common mode choke coil. The steps outlined include selecting the output voltage and feedback circuit, output capacitor, inductance L1, input capacitor C4, auxiliary winding L2, and circuits for current detection and zero current detection.
RF Module Design - [Chapter 4] Transceiver ArchitectureSimen Li
This document discusses RF transceiver architectures. It begins by outlining general considerations for transmitters such as adjacent channel leakage and receiver considerations like rejection of interference. It then covers frequency conversion techniques used in receivers like heterodyne receivers and issues they face like images and mixing spurs. Receiver architectures covered include the basic heterodyne, modern approaches like zero-IF, and dual-IF receivers which attempt to balance image rejection and channel selection. Transmitter architectures discussed include direct conversion and heterodyne approaches.
This document describes the operation and modeling of one-switch and two-switch flyback converters. It discusses the ideal and non-ideal cases, comparing the circuits with and without parasitic components. The one-switch converter has issues with resonance from leakage inductance, while the two-switch topology clamps voltages and recycles leakage energy. Simulation models of the circuits are presented, showing the effects of parasitic capacitances and inductances. Component mismatches and their impacts are also analyzed. Finally, losses including conduction, forward voltage, and switching are calculated and compared between the converter designs.
This document describes a simplified SPICE behavioral model for a 3-phase DC/AC inverter. The model allows for transient simulation of the inverter's input-output characteristics without detailed circuitry. It is parameterized based on the inverter's specifications, such as voltage and efficiency ratings. Simulation examples are provided to demonstrate the inverter's output voltage, current, efficiency, and behavior at minimum input voltage.
This PPT will help to understand about the following:
1. what is DSC ?
2. what is mp ?
3. Difference between mp and DSC ?
4. Various generation of TMS320 ?
5. Application of TMS320F2000 FAMILY
This document summarizes different types of noise in electronic components, including thermal noise, shot noise, flicker noise, antenna noise, and noise figure. It discusses various noise sources such as Johnson noise, atmospheric noise, solar noise, galactic noise, ground noise, and man-made noise. It also covers concepts like equivalent noise temperature, available noise power, noise power spectrum density, and methods for measuring noise temperature including the gain method and Y-factor method.
GaAs Wafer and Epiwafer Market: RF, Photonics, LED, Display and PV Applicatio...Yole Developpement
The report provides a market analysis of the GaAs wafer and epiwafer markets from 2019 to 2025. It forecasts that the GaAs wafer market will increase from $200 million in 2019 to $348 million in 2025, with the largest application segments being RF, photonics, and LED. The open epiwafer market is also analyzed, with IQE and VPEC together comprising almost 80% of the $262 million total market in 2019. Key drivers of growth are discussed for various applications such as 5G adoption for RF and increasing use of VCSELs for 3D sensing and LiDAR.
OSRAM Opto Semiconductors presents How to Read a Datasheet Part 1 of 2 - Typical/Maximum Characteristics and Binning as part of the LED Fundamentals section on the LED Light Site. In this presentation we examine the key parameters specified on the first half of an LED datasheet from OSRAM Opto Semiconductors. The datasheet captures some of the most important technical characteristics of an LED. These include electrical, optical and thermal quantities, knowledge of which is paramount for an LED system design. Also, it has information on ordering codes, labeling and packaging of the LEDs. Fan us on Facebook https://www.facebook.com/OSRAMLEDLight and visit our website for more information http://ledlight.osram-os.com/
This document provides an overview of voltage references and describes a lecture on bandgap voltage references. It discusses the performance requirements of voltage references including accuracy, stability, load regulation, and thermal stability. It then summarizes zener diode references and describes how a bandgap voltage reference works by combining the positive temperature coefficient of thermal voltage VT with the negative coefficient of the base-emitter voltage VBE to produce an output voltage independent of temperature. The document explains the fundamentals and shows a bandgap voltage reference circuit using two bipolar transistors with different emitter areas to generate proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages.
RF Module Design - [Chapter 4] Transceiver ArchitectureSimen Li
This document discusses RF transceiver architectures. It begins by outlining general considerations for transmitters such as adjacent channel leakage and receiver considerations like rejection of interference. It then covers frequency conversion techniques used in receivers like heterodyne receivers and issues they face like images and mixing spurs. Receiver architectures covered include the basic heterodyne, modern approaches like zero-IF, and dual-IF receivers which attempt to balance image rejection and channel selection. Transmitter architectures discussed include direct conversion and heterodyne approaches.
This document describes the operation and modeling of one-switch and two-switch flyback converters. It discusses the ideal and non-ideal cases, comparing the circuits with and without parasitic components. The one-switch converter has issues with resonance from leakage inductance, while the two-switch topology clamps voltages and recycles leakage energy. Simulation models of the circuits are presented, showing the effects of parasitic capacitances and inductances. Component mismatches and their impacts are also analyzed. Finally, losses including conduction, forward voltage, and switching are calculated and compared between the converter designs.
This document describes a simplified SPICE behavioral model for a 3-phase DC/AC inverter. The model allows for transient simulation of the inverter's input-output characteristics without detailed circuitry. It is parameterized based on the inverter's specifications, such as voltage and efficiency ratings. Simulation examples are provided to demonstrate the inverter's output voltage, current, efficiency, and behavior at minimum input voltage.
This PPT will help to understand about the following:
1. what is DSC ?
2. what is mp ?
3. Difference between mp and DSC ?
4. Various generation of TMS320 ?
5. Application of TMS320F2000 FAMILY
This document summarizes different types of noise in electronic components, including thermal noise, shot noise, flicker noise, antenna noise, and noise figure. It discusses various noise sources such as Johnson noise, atmospheric noise, solar noise, galactic noise, ground noise, and man-made noise. It also covers concepts like equivalent noise temperature, available noise power, noise power spectrum density, and methods for measuring noise temperature including the gain method and Y-factor method.
GaAs Wafer and Epiwafer Market: RF, Photonics, LED, Display and PV Applicatio...Yole Developpement
The report provides a market analysis of the GaAs wafer and epiwafer markets from 2019 to 2025. It forecasts that the GaAs wafer market will increase from $200 million in 2019 to $348 million in 2025, with the largest application segments being RF, photonics, and LED. The open epiwafer market is also analyzed, with IQE and VPEC together comprising almost 80% of the $262 million total market in 2019. Key drivers of growth are discussed for various applications such as 5G adoption for RF and increasing use of VCSELs for 3D sensing and LiDAR.
OSRAM Opto Semiconductors presents How to Read a Datasheet Part 1 of 2 - Typical/Maximum Characteristics and Binning as part of the LED Fundamentals section on the LED Light Site. In this presentation we examine the key parameters specified on the first half of an LED datasheet from OSRAM Opto Semiconductors. The datasheet captures some of the most important technical characteristics of an LED. These include electrical, optical and thermal quantities, knowledge of which is paramount for an LED system design. Also, it has information on ordering codes, labeling and packaging of the LEDs. Fan us on Facebook https://www.facebook.com/OSRAMLEDLight and visit our website for more information http://ledlight.osram-os.com/
This document provides an overview of voltage references and describes a lecture on bandgap voltage references. It discusses the performance requirements of voltage references including accuracy, stability, load regulation, and thermal stability. It then summarizes zener diode references and describes how a bandgap voltage reference works by combining the positive temperature coefficient of thermal voltage VT with the negative coefficient of the base-emitter voltage VBE to produce an output voltage independent of temperature. The document explains the fundamentals and shows a bandgap voltage reference circuit using two bipolar transistors with different emitter areas to generate proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages.
This document contains an exam for an RF IC Design course, listing 8 questions covering various topics in radio frequency integrated circuit design. Students were instructed to answer any 5 of the 8 questions, which covered topics such as inter-symbol interference, analog modulation, coherent vs non-coherent detection, phase locked loops, low noise amplifier design, mobile RF communications concepts, transmitter architectures, oscillator design techniques, and power amplifier classes and matching. The exam was 3 hours long and worth a maximum of 60 marks.
The increasing demand for light emitting diodes (LEDs) has been driven by a number of application categories, including display backlighting, communications, medical services, signage, and general illumination. The construction of LEDs is somewhat similar to microelectronics, but there are functional requirements, materials, and interfaces in LEDs that make their failure modes and mechanisms unique. This web seminar will present a review for industry and academic research on LED failure mechanisms and reliability to help LED developers and end-product manufacturers focus resources in an effective manner. The focus is on the reliability of LEDs at the die and package levels. The driving factors for precipitating these mechanisms will be discussed to help the developers and users of LEDs control the mechanisms and assess reliability. We will concentrate on the phosphor thermal quenching mechanism to illustrate the uniqueness of LEDs compared with other semiconductor devices.
PN junction diode –structure, operation and V-I characteristics, diffusion and transient capacitance - Rectifiers – Half Wave and Full Wave Rectifier,– Display devices- LED, Laser diodes- Zener diodecharacteristics-Zener Reverse characteristics – Zener as regulator,TRANSISTORS, BJT, JFET, MOSFET- structure, operation, characteristics and Biasing UJT, Thyristor and IGBT Structure and characteristics,BJT small signal model – Analysis of CE, CB, CC amplifiers- Gain and frequency response –
MOSFET small signal model– Analysis of CS and Source follower – Gain and frequency response- High frequency analysis,BIMOS cascade amplifier, Differential amplifier – Common mode and Difference mode analysis – FET input stages – Single tuned amplifiers – Gain and frequency response – Neutralization methods, power amplifiers –Types (Qualitative analysis),Advantages of negative feedback – voltage / current, series , Shunt feedback –positive feedback – Condition for oscillations, phase shift – Wien bridge, Hartley, Colpitts and Crystal oscillators.
This document discusses analog versus digital systems and the digital revolution. It notes that analog values are continuous while digital values are discrete. It gives examples of analog clocks and temperature measurements versus digital clocks. The document then discusses how many devices have been converted from analog to digital, including record albums to CDs, VHS tapes to DVDs, and analog TV to digital TV. Finally, it briefly explains how CD players work by taking the digital data from the CD and converting it to an analog audio signal for playback through speakers.
This document discusses interfacing an OV7670 camera module with an Arduino board. It provides an overview of the hardware used, including details of the Arduino board specifications and the camera module. It then describes how the camera module connects to the Arduino via its pins and communicates over the Serial Camera Control Bus protocol. The document explains that the Arduino software IDE makes it easy to write code to capture and process images from the camera module.
This document presents a SPICE model for an ideal diode. It contains a copyright notice and defines a SPICE model called DIDEAL with parameters for saturation current, emission coefficient, knee current, knee voltage and bandgap. The model is then used in a netlist to simulate the ideal diode behavior.
This document discusses trends in the IC packaging industry and technology. It provides an overview of the market growth in IC packaging units and revenues. Key challenges for the industry are declining ASPs and increasing materials costs. Emerging technologies discussed include wafer-level packaging, 2.5D/3D IC with TSV, and integrated passives. The document outlines SPIL's packaging portfolio and roadmaps for 3D IC and TSV development over the next few years. It also summarizes SPIL's testing and certification capabilities.
types of voltage regulator and DC power supply notes.pdfSorrystudy
In This presentation file their is a topic named Types of voltage regulator and DC power supply explained easily. You will interesting material in this PPT file.
SPICE MODEL of TLP521-1 SAMPLE A in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document outlines the agenda for a two-day workshop on the TMS320C6745 digital signal processor. Day 1 covers introductions to DSP architecture and the CCS development environment, as well as tutorials on waveform generation, UART interfaces, and image processing techniques. Day 2 focuses on additional image processing topics like discrete wavelet transforms and filters, as well as a valedictory session. The document provides context about the instructor and includes specifications about the TMS320C6745 processor.
1) The document examines the impact of hot carrier injection (HCI) on voltage controlled oscillator (VCO) lifetime prediction through reliability tests using constant voltage stress (CVS) and ramped voltage stress (RVS).
2) Results show HCI dominates over negative bias temperature instability (NBTI) as the stress voltage increases, shifting the dominant degradation mechanism. Break points in RVS tests can guide proper stress voltage ranges to suppress HCI effects.
3) Simulation software RelXpert was used to model the VCO degradation, matching measurement results and showing pFET degradation mainly contributes to VCO changes, with NBTI dominating at low voltages and HCI at high voltages. Failing to account
Electronics engineering is an important and growing field that impacts everyday life. Electronics engineers design devices like phones, computers, and communication systems using science, math, and engineering techniques. Studying electronics engineering provides opportunities to create electrical systems that help millions of people. Careers in electronics include positions as electronics engineers, communication engineers, design engineers, and more in both government sectors like ISRO and private companies like Samsung. The field of electronics engineering continues to expand with new technologies and remains in high demand.
System-on-Chip Design, Embedded System Design Challengespboulet
The document discusses challenges in system-on-chip design. The main challenges are:
1. Increasing design productivity by over 100% per technology node to keep up with Moore's Law scaling.
2. Managing power, especially for low-power, wireless, and multimedia applications.
3. Integrating heterogeneous technologies like MEMS and optoelectronics at the system level.
4. Developing test methodologies for system-on-chips, including reusable tests and built-in self-test for analog and digital components.
STT MRAM for Artificial Intelligence ApplicationsDanny Sabour
Yiming Huai of Avalanche Technology presented on STT-MRAM and its applications for artificial intelligence at Semicon Taiwan 2020. STT-MRAM offers benefits over other memory types like flash and SRAM as it has unlimited endurance, high speed performance comparable to DRAM, non-volatility, and can scale to smaller nodes. Avalanche has developed pMTJ technology that achieves fast write speeds of 20ns or less. Measurement results showed STT-MRAM macros achieved endurance of over 1014 cycles, 10-year data retention at 125C, and are manufactured on 22nm process through partnerships with foundries. STT-MRAM is well-suited for edge AI applications requiring high
This document outlines the syllabus for a VLSI design course. The syllabus covers five units: (1) CMOS technology, including history, characteristics, and enhancements; (2) circuit characterization and simulation; (3) combinational and sequential circuit design; (4) CMOS testing; and (5) specification using Verilog HDL. The first unit provides an introduction to CMOS technology, discussing MOS transistors, CMOS processes like p-well and n-well, and layout design rules. Subsequent units cover circuit analysis, common circuit elements, testing approaches, and hardware description languages. References include textbooks on VLSI design, digital circuits, and Verilog HDL.
Project list pic microcontroller 877- projectsAshraf11111
This document provides a list of over 50 microcontroller projects using PIC microcontrollers. It introduces PIC microcontrollers and notes they are used widely in electronics from multimedia devices to medical equipment. It then lists various categories of PIC projects including LED projects, motor projects, sensor projects, and more. Each project listing includes the microcontroller used and a brief description. It also includes advertisements for related tools and components.
This document provides an introduction to system on chip (SoC) based smartphone processors, their working, and architecture. It defines an SoC as an integrated circuit that combines all components of an electronic system into a single chip, including digital, analog and radio frequency functions. SoCs are used in smartphones to minimize size and power consumption by integrating components like the CPU, memory, timing sources and peripherals onto one chip. Popular smartphone SoCs include Qualcomm's Snapdragon and Samsung's Exynos, which are based on ARM architecture and include CPU cores, GPU, and cellular radios. Key aspects of SoC processors discussed include cores, clock speed, multi-threading, and why Qualcomm Snapdragon processors are
Analog to Digital Converter (ADC) is a device that converts an analog quantity (continuous voltage) to discrete digital values.
The PIC microcontroller can be used in various electronic devices like alarm systems, electronic gadgets and computer control systems.
PWM is used to control motor speed and light dimming by varying the duty cycle of an output waveform. It can be generated using a timer, comparator, and waveform generator. The timer increments at a set rate while the comparator monitors the timer value and outputs a pulse while the timer is less than the compare value set by the output compare register. Different PWM modes and registers control aspects like waveform, frequency, and output compare functionality.
IC Design of Power Management Circuits (II)Claudia Sin
The document discusses various aspects of integrated circuit design for power management circuits. It covers control loop design including biasing circuits, oscillators, comparators and operational amplifiers. It also discusses power stage design such as power transistors, synchronous rectification and active diodes. Finally it discusses peripheral circuits including undervoltage lockout, overcurrent protection and soft start circuits. The document provides guidelines and examples for analog integrated circuit design of switching converters and related circuits.
The document provides design details for a critical conduction mode power factor correction (PFC) circuit. It includes:
1) An introduction describing the need for power factor correction to draw sinusoidal current in phase with input voltage for improved power factor.
2) An application circuit diagram for a 400V/200W PFC circuit using a TB6819AFG controller IC along with component values and simulation parameters.
3) Explanations of techniques used including time scaling to speed up simulations and modeling of a common mode choke coil.
4) An 8-step design process covering the output voltage feedback, output capacitor sizing, inductor, input capacitor, auxiliary winding, current/zero current detection
The document provides design specifications and steps for a critical conduction mode power factor correction (PFC) circuit. It includes an application circuit diagram using a TB6819AFG controller IC along with component values and equations. Time scaling is used to speed up transient simulations in SPICE. Key steps explained are selecting the output voltage and feedback resistors, output capacitor, inductor, input capacitor, auxiliary winding, and circuits for current and zero current detection.
This document contains an exam for an RF IC Design course, listing 8 questions covering various topics in radio frequency integrated circuit design. Students were instructed to answer any 5 of the 8 questions, which covered topics such as inter-symbol interference, analog modulation, coherent vs non-coherent detection, phase locked loops, low noise amplifier design, mobile RF communications concepts, transmitter architectures, oscillator design techniques, and power amplifier classes and matching. The exam was 3 hours long and worth a maximum of 60 marks.
The increasing demand for light emitting diodes (LEDs) has been driven by a number of application categories, including display backlighting, communications, medical services, signage, and general illumination. The construction of LEDs is somewhat similar to microelectronics, but there are functional requirements, materials, and interfaces in LEDs that make their failure modes and mechanisms unique. This web seminar will present a review for industry and academic research on LED failure mechanisms and reliability to help LED developers and end-product manufacturers focus resources in an effective manner. The focus is on the reliability of LEDs at the die and package levels. The driving factors for precipitating these mechanisms will be discussed to help the developers and users of LEDs control the mechanisms and assess reliability. We will concentrate on the phosphor thermal quenching mechanism to illustrate the uniqueness of LEDs compared with other semiconductor devices.
PN junction diode –structure, operation and V-I characteristics, diffusion and transient capacitance - Rectifiers – Half Wave and Full Wave Rectifier,– Display devices- LED, Laser diodes- Zener diodecharacteristics-Zener Reverse characteristics – Zener as regulator,TRANSISTORS, BJT, JFET, MOSFET- structure, operation, characteristics and Biasing UJT, Thyristor and IGBT Structure and characteristics,BJT small signal model – Analysis of CE, CB, CC amplifiers- Gain and frequency response –
MOSFET small signal model– Analysis of CS and Source follower – Gain and frequency response- High frequency analysis,BIMOS cascade amplifier, Differential amplifier – Common mode and Difference mode analysis – FET input stages – Single tuned amplifiers – Gain and frequency response – Neutralization methods, power amplifiers –Types (Qualitative analysis),Advantages of negative feedback – voltage / current, series , Shunt feedback –positive feedback – Condition for oscillations, phase shift – Wien bridge, Hartley, Colpitts and Crystal oscillators.
This document discusses analog versus digital systems and the digital revolution. It notes that analog values are continuous while digital values are discrete. It gives examples of analog clocks and temperature measurements versus digital clocks. The document then discusses how many devices have been converted from analog to digital, including record albums to CDs, VHS tapes to DVDs, and analog TV to digital TV. Finally, it briefly explains how CD players work by taking the digital data from the CD and converting it to an analog audio signal for playback through speakers.
This document discusses interfacing an OV7670 camera module with an Arduino board. It provides an overview of the hardware used, including details of the Arduino board specifications and the camera module. It then describes how the camera module connects to the Arduino via its pins and communicates over the Serial Camera Control Bus protocol. The document explains that the Arduino software IDE makes it easy to write code to capture and process images from the camera module.
This document presents a SPICE model for an ideal diode. It contains a copyright notice and defines a SPICE model called DIDEAL with parameters for saturation current, emission coefficient, knee current, knee voltage and bandgap. The model is then used in a netlist to simulate the ideal diode behavior.
This document discusses trends in the IC packaging industry and technology. It provides an overview of the market growth in IC packaging units and revenues. Key challenges for the industry are declining ASPs and increasing materials costs. Emerging technologies discussed include wafer-level packaging, 2.5D/3D IC with TSV, and integrated passives. The document outlines SPIL's packaging portfolio and roadmaps for 3D IC and TSV development over the next few years. It also summarizes SPIL's testing and certification capabilities.
types of voltage regulator and DC power supply notes.pdfSorrystudy
In This presentation file their is a topic named Types of voltage regulator and DC power supply explained easily. You will interesting material in this PPT file.
SPICE MODEL of TLP521-1 SAMPLE A in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document outlines the agenda for a two-day workshop on the TMS320C6745 digital signal processor. Day 1 covers introductions to DSP architecture and the CCS development environment, as well as tutorials on waveform generation, UART interfaces, and image processing techniques. Day 2 focuses on additional image processing topics like discrete wavelet transforms and filters, as well as a valedictory session. The document provides context about the instructor and includes specifications about the TMS320C6745 processor.
1) The document examines the impact of hot carrier injection (HCI) on voltage controlled oscillator (VCO) lifetime prediction through reliability tests using constant voltage stress (CVS) and ramped voltage stress (RVS).
2) Results show HCI dominates over negative bias temperature instability (NBTI) as the stress voltage increases, shifting the dominant degradation mechanism. Break points in RVS tests can guide proper stress voltage ranges to suppress HCI effects.
3) Simulation software RelXpert was used to model the VCO degradation, matching measurement results and showing pFET degradation mainly contributes to VCO changes, with NBTI dominating at low voltages and HCI at high voltages. Failing to account
Electronics engineering is an important and growing field that impacts everyday life. Electronics engineers design devices like phones, computers, and communication systems using science, math, and engineering techniques. Studying electronics engineering provides opportunities to create electrical systems that help millions of people. Careers in electronics include positions as electronics engineers, communication engineers, design engineers, and more in both government sectors like ISRO and private companies like Samsung. The field of electronics engineering continues to expand with new technologies and remains in high demand.
System-on-Chip Design, Embedded System Design Challengespboulet
The document discusses challenges in system-on-chip design. The main challenges are:
1. Increasing design productivity by over 100% per technology node to keep up with Moore's Law scaling.
2. Managing power, especially for low-power, wireless, and multimedia applications.
3. Integrating heterogeneous technologies like MEMS and optoelectronics at the system level.
4. Developing test methodologies for system-on-chips, including reusable tests and built-in self-test for analog and digital components.
STT MRAM for Artificial Intelligence ApplicationsDanny Sabour
Yiming Huai of Avalanche Technology presented on STT-MRAM and its applications for artificial intelligence at Semicon Taiwan 2020. STT-MRAM offers benefits over other memory types like flash and SRAM as it has unlimited endurance, high speed performance comparable to DRAM, non-volatility, and can scale to smaller nodes. Avalanche has developed pMTJ technology that achieves fast write speeds of 20ns or less. Measurement results showed STT-MRAM macros achieved endurance of over 1014 cycles, 10-year data retention at 125C, and are manufactured on 22nm process through partnerships with foundries. STT-MRAM is well-suited for edge AI applications requiring high
This document outlines the syllabus for a VLSI design course. The syllabus covers five units: (1) CMOS technology, including history, characteristics, and enhancements; (2) circuit characterization and simulation; (3) combinational and sequential circuit design; (4) CMOS testing; and (5) specification using Verilog HDL. The first unit provides an introduction to CMOS technology, discussing MOS transistors, CMOS processes like p-well and n-well, and layout design rules. Subsequent units cover circuit analysis, common circuit elements, testing approaches, and hardware description languages. References include textbooks on VLSI design, digital circuits, and Verilog HDL.
Project list pic microcontroller 877- projectsAshraf11111
This document provides a list of over 50 microcontroller projects using PIC microcontrollers. It introduces PIC microcontrollers and notes they are used widely in electronics from multimedia devices to medical equipment. It then lists various categories of PIC projects including LED projects, motor projects, sensor projects, and more. Each project listing includes the microcontroller used and a brief description. It also includes advertisements for related tools and components.
This document provides an introduction to system on chip (SoC) based smartphone processors, their working, and architecture. It defines an SoC as an integrated circuit that combines all components of an electronic system into a single chip, including digital, analog and radio frequency functions. SoCs are used in smartphones to minimize size and power consumption by integrating components like the CPU, memory, timing sources and peripherals onto one chip. Popular smartphone SoCs include Qualcomm's Snapdragon and Samsung's Exynos, which are based on ARM architecture and include CPU cores, GPU, and cellular radios. Key aspects of SoC processors discussed include cores, clock speed, multi-threading, and why Qualcomm Snapdragon processors are
Analog to Digital Converter (ADC) is a device that converts an analog quantity (continuous voltage) to discrete digital values.
The PIC microcontroller can be used in various electronic devices like alarm systems, electronic gadgets and computer control systems.
PWM is used to control motor speed and light dimming by varying the duty cycle of an output waveform. It can be generated using a timer, comparator, and waveform generator. The timer increments at a set rate while the comparator monitors the timer value and outputs a pulse while the timer is less than the compare value set by the output compare register. Different PWM modes and registers control aspects like waveform, frequency, and output compare functionality.
IC Design of Power Management Circuits (II)Claudia Sin
The document discusses various aspects of integrated circuit design for power management circuits. It covers control loop design including biasing circuits, oscillators, comparators and operational amplifiers. It also discusses power stage design such as power transistors, synchronous rectification and active diodes. Finally it discusses peripheral circuits including undervoltage lockout, overcurrent protection and soft start circuits. The document provides guidelines and examples for analog integrated circuit design of switching converters and related circuits.
The document provides design details for a critical conduction mode power factor correction (PFC) circuit. It includes:
1) An introduction describing the need for power factor correction to draw sinusoidal current in phase with input voltage for improved power factor.
2) An application circuit diagram for a 400V/200W PFC circuit using a TB6819AFG controller IC along with component values and simulation parameters.
3) Explanations of techniques used including time scaling to speed up simulations and modeling of a common mode choke coil.
4) An 8-step design process covering the output voltage feedback, output capacitor sizing, inductor, input capacitor, auxiliary winding, current/zero current detection
The document provides design specifications and steps for a critical conduction mode power factor correction (PFC) circuit. It includes an application circuit diagram using a TB6819AFG controller IC along with component values and equations. Time scaling is used to speed up transient simulations in SPICE. Key steps explained are selecting the output voltage and feedback resistors, output capacitor, inductor, input capacitor, auxiliary winding, and circuits for current and zero current detection.
The document summarizes the design, verification, and optimization of a boost converter circuit with the following specifications: input voltage (VIN) of 5V, output voltage (VOUT) of 9V, output current (IOUT) of 50mA, and peak-to-peak ripple voltage of 30mV. It describes 1) circuit design verification to meet specifications, 2) output stage optimization by comparing output capacitors and selecting a diode, 3) analyzing the selected diode and power switch characteristics and stresses. The optimizations reduced output ripple voltage and switching stresses.
This document describes LTspice simulations of a 50W flyback converter circuit using different input voltages. It includes the circuit schematic, input and output waveforms, power output, and gate drive timing for input voltages of 85Vac, 110Vac and 265Vac. It also provides more detailed waveforms and analysis for an example simulation with 110Vac input, examining the transformer operation, MOSFET switching, and feedback circuit. Specifications and simulation settings are provided in appendices.
This document provides a design workflow for a step-down DC-DC converter using the NJM2309 PWM controller IC. The workflow includes: [1] setting the controller parameters; [2] selecting resistor values for the output voltage; [3] choosing the inductor and capacitor values; [4] adding compensation to stabilize the converter; and [5] simulating the load transient response. Appendices provide additional details on compensation calculation and feedback loop types.
This data sheet provides specifications for the Broadcom ACPL-K49T 20-kBd digital optocoupler. It is designed for automotive applications with a wide operating temperature range of -40°C to +125°C. The optocoupler provides electrical insulation between input and output connections using an LED and integrated photodetector. It has high common-mode rejection up to 30 kV/μs and low propagation delays under 20 μs. The device is available in either a 4-pin or 5-pin configuration and packaged in a compact SO8 package.
This document discusses the design of a power factor correction (PFC) circuit using critical conduction mode (CRM) control. It begins with an introduction to poor power factor in rectifying circuits and how PFC improves power factor. It then presents the application circuit using a TB6819AFG PFC controller IC. Key parameters are specified and the circuit operation is explained. Design steps are outlined to calculate component values to achieve the desired power factor ratio near unity.
Original Opto LTV-354T LTV354T 354T 354 SOP-4 NewAUTHELECTRONIC
This document provides product data and specifications for Lite-On Technology Corp.'s LTV-354T series photocouplers. It includes details on packaging, electrical and optical characteristics, temperature profiles for soldering, and recommended footprints. The photocouplers feature AC input response, high isolation voltage up to 3,750Vrms, and mini-flat packages as small as 2.0mm in profile. They are suitable for applications requiring high density mounting such as hybrid substrates, programmable controllers, and measuring instruments.
The document provides specifications for the S30A40AC analog servo drive. It is designed to drive 3-phase brushless motors with sine wave current at high frequencies. It requires two 120-degree phase shifted sine wave command signals for commutation and torque control. The drive has overcurrent, overvoltage, and thermal protections. It is compliant with various safety and EMC standards.
This document discusses flyback converter design considerations for multi-kilowatt power conversion applications. It outlines flyback converter advantages and disadvantages, and solutions to overcome the disadvantages. Specifically, it focuses on single-stage power factor correction (PFC) applications using a flyback topology. The document discusses adapting the flyback converter for PFC, selecting an appropriate PFC control IC, modifying the control IC for high power applications, and transformer design considerations. It provides block diagrams and partial schematics as examples.
The document describes an analog servo drive that:
- Can provide up to 40A of peak current and 20A of continuous current from a 45-265VAC power supply.
- Includes protection against overvoltage, undervoltage, overcurrent, overheating and short circuits.
- Can be controlled via analog input, encoder, or hall sensors and has adjustable current limits, gains and offsets.
- Has DIP switches to select modes of operation and feedback and includes monitoring outputs.
The document provides specifications for the S60A40AC analog servo drive. It is designed to drive 3-phase brushless motors with sinusoidal current at high switching frequencies. The drive requires two 120-degree phase shifted sine wave command signals for motor control. It has over-current, over-voltage and short circuit protections. Key features include 4-quadrant regenerative operation, adjustable current limits and a built-in brake/shunt regulator.
The document describes an analog servo drive that:
- Can provide up to 60A of peak current and 30A of continuous current from a 60-400VDC power supply.
- Includes protection against overvoltage, overcurrent, overheating and other faults.
- Can be controlled via a ±10V analog command and supports Hall, encoder and tachometer feedback.
- Has adjustable current limits, acceleration/deceleration rates, and other parameters via onboard potentiometers.
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- Can provide up to 30A of peak current and 15A of continuous current from a 45-265VAC power supply.
- Includes protections against overvoltage, overcurrent, overheating and other faults.
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- Has adjustable current limits, commutation phasing and other parameters via onboard potentiometers.
Similar to Critical Conduction Mode (CRM) PFC Circuit (20)
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2. Contents
• Introduction
• Application Circuit
• Design Specification
• Time Scaling
• Application Circuit with Time Scaling (tscale =10)
• Common Mode Choke Coil for PFC
• Design Steps (1-8)
• Switching Devices VPEAK and IPEAK at Steady State
• Switching Devices VPEAK and IPEAK at Start Up
Appendix
A.Excel Calculation Sheet
B.Simulation Index
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 2
3. Introduction
Most electronic ballasts and switching power supplies use a bridge rectifier
and a bulk storage capacitor to derive raw dc voltage from the utility ac line,
figure above: Vin=100Vac, 50Hz and PO=200W.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 3
Vin
AC_IN1
PARAMETERS:
f req = 50Hz
Vin = 100Vac
AC_IN2
Cbulk
2000uF
0
bulk
DB1
DB2
DB3
Diode
DB4
Load
1.414Adc
Iline
Vbulk
4. Time
160ms 164ms 168ms 172ms 176ms 180ms 184ms 188ms 192ms 196ms 200ms
AVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
0
0.2
0.4
0.6
0.8
1.0
ABS( I(Vin) )
0A
10A
20A
ABS( V(AC_IN1,AC_IN2) ) V(bulk)
0V
100V
200V
SEL>>
Introduction
The Uncorrected Power Factor rectifying circuit draws current from the ac line
when the ac voltage exceeds the capacitor voltage (Vbulk). The current (Iline) is non-
sinusoidal. This results in a poor power factor condition where the apparent input
power is much higher than the real power, figure above, power factor ratios of 0.5 to
0.7 are common.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 4
|VAC, in, 100V| (VPEAK, in=100*2=141.42V) and Vbulk
|Iline|
Power Factor Ratio = Pin, avg./(Vin, rms* Iin, rms)
5. Vac, in
C1
1uF
C2
200u
ILoad
0.5A
L1
1
2
Diode
D2
Q1
MOSFET
R7
L2
1 2
0
0
Rectifiers PFC
TB6819AFG
Controller
Circuit
PARAMETERS:
f req = 50Hz
Vin = 100Vac
Introduction
The Power Factor Correction (PFC) circuit, as an off-line active preconverter, is
designed to draw a sinusoidal current from the AC line that is in phase with input
voltage. As a result, the power factor ratio is improved to be near to ideal (1).
The TB6819AFG is a critical conduction mode (CRM) PFC controller IC. The
description including equation and constants as a guide to understand its designing
process is included in this document.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 5
Iline
VDC, OUT
6. Time*10
100ms 104ms 108ms 112ms 116ms 120ms 124ms 128ms 132ms 136ms 140ms
AVG(ABS(W(Vin))) / (RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
0
0.2
0.4
0.6
0.8
1.0
-I(Vin)
-8.0A
0A
8.0A
SEL>>
1 V(AC_IN1,AC_IN2) 2 V(VOUT)
-160V
0V
160V
1
200V
400V
600V
2
>>
Introduction
The poor power factor load is corrected by keeping the ac line current sinusoidal and in
phase with the line voltage. This results with power factor ratio is 0.85.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 6
VAC, in, 100V and VDC, OUT, 400V
Iline
Power Factor Ratio = 0.85
*simulation result at tscale = 10
8. Time
10ms 11ms 12ms 13ms 14ms 15ms 16ms 17ms 18ms 19ms 20ms
AVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
0
0.5
1.0
Time
0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms
-I(Vin)
-10A
0A
10A
SEL>>
1 V(AC_IN1,AC_IN2) 2 V(VOUT)
-200V
0V
200V
1
380V
400V
420V
2
>>
Application Circuit
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 8
VAC, in, 100V and VDC, OUT, 400V
Iline
Power Factor Ratio = 0.85
Total simulation time = 1429.49 seconds
9. Design Specification
This application circuit is for 400VDC/200W output
Critical Conduction Mode (CRM) PFC Circuit :
• VAC, in,min = 85 (VAC)
• VAC, in,max = 265 (VAC)
• VO = 400 (VDC)
• Po = 200 (W)
• fs = 20kHz ~ 150kHz, 50kHz
• (assumed) = 90%
Control IC :
• Part # TTB6819AFG (PFC Controller IC)
• Switching Technique: Critical Conduction Mode (CRM)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 9
10. Time Scaling
The transient (cycle-by-cycle) simulation of PFC circuits is really time (and memory)
consuming exercise, even with a fast computer.
There is a way to speed up simulations by artificially altering some of the key element values
by using of time scaling ratio (tscale), passed as a parameter to the simulation engine:
• F line = F line tscale
• C 2 = C 2 tscale
• C 3 = C 3 tscale
• C 4 = C 4 tscale
• C 5 = C 5 tscale
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 10
12. Time*10
10ms 11ms 12ms 13ms 14ms 15ms 16ms 17ms 18ms 19ms 20ms
AVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
0
0.5
1.0
Time*10
0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms
-I(Vin)
-10A
0A
10A
SEL>>
1 V(AC_IN1,AC_IN2) 2 V(VOUT)
-200V
0V
200V
1
380V
400V
420V
2
>>
Application Circuit with Time Scaling (tscale =10)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 12
VAC, in, 100V and VDC, OUT, 400V
Iline
Power Factor Ratio = 0.85
Total simulation time = 132.41 seconds
13. Common Mode Choke Coil for PFC
To model a simple common mode choke coil, the
SPICE primitive k, which describes the coupling ratio
between L1 and L2, can be used.
COUPLING=1 of K_Linear means there is no leakage
inductance in the common mode choke coil model.
N is a ratio of L2 turns and L1 turns, or N2/N1
Input the parameters: L as an L1 inductance value
and N, then L2 is calculated using equation: L2 =
N2L1
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 13
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
14. Design Steps (1-8)
(1) Output Voltage and Feedback Circuit
(2) Output Capacitor
(3) L1 Inductance
(4) Input Capacitor
(5) Auxiliary Winding L2
(6) Multiplier Input Circuit (MULT)
(7) Current Detection Circuit (IS)
(8) Zero Current Detection Circuit (ZCD)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 14
15. (1) Output Voltage and Feedback Circuit
The output voltage is resistively divided and applied to the error amplifier, to set the VO
the R1 and R2 resistor value should satisfy the following equation :
*With VO=400V and R2=1.5M, R1 is calculated to be 9.47k, however a resistor of 9.53k , which
is available in the E96 series, is used as R1 (actual).
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 15
2.51
R
R
R
V
2
1
1
O
Output DC Voltage, VO 400 V
Error Amplifier Reference Voltage Verr 2.51 V
R2 1.5 M
R1 9.47 k
R1 (actual) 9.53* k
16. (2) Output Capacitor
The output capacitance C2 is determined so that the PFC output ripple voltage dose not
exceed the VOPV-2, for the capacitor selection, the following equation should be satisfied:
The value of VOVP-2, min and Verr, min are inform in the TB6819AFG datasheet.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 16
PO 200 W
fin 50 Hz
VO 400 V
VOVP-2, min 2.63 V
Verr, min 2.46 V
C2 41 F
C2used 200 F
1
-
/V
V
V
2
2
P
C2
err
2
-
OVP
2
O
O
in
f
17. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 100
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 3.85
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (1) and (2)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 17
Vin = 100Vac with
frequency 50Hz,
tscale = 10
R1=9.53k and
R2=1.5M
Iload = 0.5A as
PO=200W at
VO=400V
C2 =
200F
*Analysis directives:
.TRAN 0 4ms 0 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
18. Time*10
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms
V(FB_IN) 2.63 2.46
2.4
2.6
2.8
V(VOUT)
380V
400V
420V
SEL>>
V(AC_IN1,AC_IN2)
-200V
0V
200V
Simulation of Step (1) and (2)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 18
VAC, in,=100V (VPEAK, in,=100*1.4142=141.4V)
V(FB IN), VOVP-2, min.(2.63V), and Verr,min(2.46V)
VO=400Vdc with 2fline ripple
Total simulation time = 270.61 seconds
19. (3) L1 Inductance
The switching frequencyfs (Hz) depends on the L1 inductance and
input/output condition which the equation and the calculation data are as shown
below.
*The fs value should be within 20kHz and 150kHz, to avoid an occurrence of EMI
problem, fs=50kHz is used.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 19
O
O
2
min
in,
AC,
min
in,
AC,
O
P
V
fs
100
2
V
)
V
2
(V
L1
η
Output DC Voltage, VO 400 V
Minimum AC Input Voltage, VAC, in, min 85 V
Power Efficiency, (assumed) 90 %
Switching Frequency, fs* 50 kHz
Output Power, PO 200 W
Calculated Inductance, L1(calculated) 227 H
Selected (Actual) Inductance, L1(actual) 230 H
20. (4) Input Capacitor
C1 should be capable of supplying energy stored in the L1 while the FET is on. Assumed
that the on/off duty is 50%, the C1 should be temporarily able to supply twice the current.
A current reaches its maximum at the VAC, in, min. Thus, the following relationship should
be satisfied:
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 20
L1 230 H
PO 200 W
VAC, in, min 85 V
C1 0.35 F
C1used 1 F
4
min
in,
AC,
2
O
V
P
L1
2
C1
21. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 85
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 4.22
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (3) and (4)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 21
Vin, min = 85Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
The Calculated L1 value
227H (adjusted 230H
is used)
I(L1)
C1 = 1F
*Analysis directives:
.TRAN 0 20ms 16m 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
22. Time
16.45ms 16.46ms 16.47ms 16.48ms 16.49ms 16.50ms 16.51ms 16.52ms 16.53ms 16.54ms 16.55ms
V(POUT)
0V
10V
20V
-I(L1)
0A
5A
10A
V(VOUT)
395V
400V
405V
SEL>>
Simulation of Step (3) and (4)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 22
VO=400Vdc with high switching ripple
I(L1)
Switching Control Signal, fs = 48.4 kHz
Total simulation time = 1056.11 seconds
23. (5) Auxiliary Winding L2
The auxiliary winding L2 is used to detect the zero inductor current condition of the inductor L1.
Since the maximum reference voltage for the ZCD comparator is 1.9V (the IC specification) ,
N1/N2 should meet the following condition:
Where N1 is the number of winding of turns of L1, N2 is that of L2
*To ensure that the design requirements are met, N1/N2 should preferably about 10 (9.6 is
used) to allow for design margins.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 23
9
.
1
max
in,
AC,
O V
2
V
N1/N2
Output DC Voltage, VO 400 V
Maximum AC Input Voltage, VAC, in, max 265 V
Calculated Turn Number Ratio, N1/N2 < 14
Selected Transformer Turn Ratio, N1/N2 (actual) 9.6*
24. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 265
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 2.533
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (5)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 24
N1/N2=9.6, input
parameter N =
N2/N1 = 1/9.6
I(L1)
Vin, min = 265Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
*Analysis directives:
.TRAN 0 4ms 2ms 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
25. Time*10
20ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40ms
V(ZCD) 1.9
0
2.5
5.0
7.5
-I(L1)
0A
2.5A
5.0A
V(VOUT)
375V
400V
425V
SEL>>
V(AC_IN1,AC_IN2)
-400V
0V
400V
Simulation of Step (5)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 25
VO=400V and PO=200W
VAC, in, min=265V (VPEAK, in, min=265*1.4142=374.8V)
I(L1)
V(ZCD) and the maximum reference voltage of the TB6819AFG’s ZCD comparator, 1.9V
Total simulation time = 1012.86 seconds
26. (6) Multiplier Input Circuit (MULT)
The AC input supply voltage (sinewave) is applied to the multiplier by dividing a full-wave
rectified voltage waveform.
The IC startup threshold voltages of the Brown Out Protection (BOP) function = 0.75V and
the MULT linear input voltage range of the multiplier = 0 to 3V, the R9 and R10 resistor should
satisfy the following condition:
with excel calculation sheet PFC_Cal-Sht.xlsx you can input R9 and R10 values, then check the
calculated BOP and Linear MULT values to be within the maximum values.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 26
10
9
10
min
in,
AC,
R
R
R
2
V
0
75
.
Maximum AC Input Voltage, VAC, in, min 400 V
Maximum AC Input Voltage, VAC, in, max 265 V
R9 3 M
R10 22 k
Minimum Condition for BOP 0.875 > 0.75
Maximum Condition for Linear MULT 2.728 < 3
3
10
9
10
max
in,
AC,
R
R
R
2
V
and
27. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 85
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 4.22
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (6) at Vin, min
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 27
R10=3M and
R11=22k
Vin, min = 85Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
*Analysis directives:
.TRAN 0 20ms 16m 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
28. Time*10
180ms 182ms 184ms 186ms 188ms 190ms 192ms 194ms 196ms 198ms 200ms
V(MULT) 0.75
0
0.5
1.0
V(Rtf)
0V
40V
80V
120V
SEL>>
V(AC_IN1,AC_IN2)
-200V
0V
200V
Simulation of Step (6) at Vin, min
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 28
Full-wave rectified voltage
VAC, in, min=85V (VPEAK, in, min=85*1.4142=120.2V)
V(MULT) > BOP threshold voltage (0.75V)
Total simulation time = 1056.11 seconds
29. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 265
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 2.533
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (6) at Vin, max
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 29
Vin, max = 265Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
R10=3M and
R11=22k
*Analysis directives:
.TRAN 0 4ms 2ms 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
30. Time*10
20ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40ms
V(MULT) 3
0
1.0
2.0
3.0
4.0
V(Rtf)
0V
100V
200V
300V
400V
V(AC_IN1,AC_IN2)
-400V
-200V
0V
200V
400V
SEL>>
Simulation of Step (6) at Vin, max
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 30
Full-wave rectified voltage
VAC, in, max=265V (VPEAK, in, min=265*1.4142=374.8V)
V(MULT) < MULT linear input maximum voltage (3V)
Total simulation time = 1012.86 seconds
31. (7) Current Detection Circuit (IS)
Iq1 (power switch current) is converted into voltage by R7, then applied to the IS pin. The R7
resistor value calculation follows these steps:
1) The maximum current of the Q1 current, Iq1 (max) should allow the output power PO to meet
the specification. Therefore, the following equation should be satisfied:
2) the IS pin peak voltage (Visp) is calculated using the following equation:
3) R7 = Visp / Iq1(max.).
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 31
R10
R9
R10
2
V
0.65
Visp min
in,
AC,
Minimum ac input voltage, VAC, in, min 85 V
Output power, PO 200 W
Power efficiency, (assumed) 90 %
R9 3 M
R10 22 k
Power switch current, Iq1(max.) 5.23 A
TB6819AFG IS pin peak voltage Visp 0.57 V
R7 0.11
)
2
V
( η
2
2
100
P
Iq1(max.)
min
in,
AC,
O
32. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 85
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 4.22
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (7)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 32
Iq1
R7 =
0.11
Vin, min = 85Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
R10=3M and
R11=22k
*Analysis directives:
.TRAN 0 20ms 16m 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
34. (8) Zero Current Detection Circuit (ZCD)
The auxiliary winding L2 is connected to the ZCD pin. The current through L2 is limited to ZCD
pin rated current (3mA) by using the current limiting resistor R6. The following relationship
should be satisfied depending on whether the external FET is on or off:
FET = On:
FET = Off:
A resistor of 68k is used for limiting the current to 1/5 of the rated current
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 34
VAC, in, max 265 V
N2/N1 1/9.6 W
VO 400 V
FET = ON, R6 > 13.0 k
FET = OFF, R6 > 13.9 k
R6 (actual) 68 k
3mA
(N2/N1)
2
V
R6 max.
in,
AC,
3mA
(N2/N1)
V
R6 O
35. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 85
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 4.22
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Simulation of Step (8)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 35
ON/OFF
R6 =
68k
Vin, max = 265Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
R10=3M and
R11=22k
*Analysis directives:
.TRAN 0 4ms 2ms 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
36. Time*10
20ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40ms
I(R6) 3m/5
-1.0m
0
1.0m
V(VOUT)
375V
400V
425V
V(AC_IN1,AC_IN2)
-400V
0V
400V
SEL>>
Simulation of Step (8)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 36
VAC, in, max=265V
V(VOUT)
I(R6) and 1/5 of the ZCD rated current (3mA/5)
Total simulation time = 1012.86 seconds
37. Load
0.5A
R12
39k
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 85
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 4.22
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
C2 {200u/tscale}
IC = {2.51*1509.53/9.53}
PARAMETERS:
tscale = 10
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
DB1
Diode
D2
Diode
D3
Diode
D4
DB2
DB3
Diode
DB4
Q1
MOSFET
R5
10
Switching Devices VPEAK and IPEAK at Steady State
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 37
Vin, min = 85Vac with
frequency 50Hz,
tscale = 10
Iload = 0.5A as
PO=200W at
VO=400V
I(D2)
Switching
Diode, D2
*Analysis directives:
.TRAN 0 20ms 16m 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 40
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
ID(Q1)
Switching
MOSFET, Q1
38. Time
18.00ms 18.25ms 18.50ms 18.75ms 19.00ms 19.25ms 19.50ms 19.75ms 20.00ms
ID(Q1)
-6A
0A
6A
12A
V(Q1:d,Q1:s)
0V
200V
400V
600V
I(D2)
8A
16A
-2A
SEL>>
V(D2:2,D2:1)
0V
200V
400V
600V
Switching Devices VPEAK and IPEAK at Steady State
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 38
D2 VKA, Peak ≈ 400V at steady state
Total simulation time = 1056.11 seconds
D2 IF, Peak ≈ 12A at steady state
Q1 VDS, Peak ≈ 400V at steady state
Q1 ID, Peak ≈ 7.2A at steady state
40. Time*40
0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms 360ms 400ms
1 V(Q1:d,Q1:s) 2 ID(Q1)
-500V
0V
500V
1
-10A
0A
10A
2
>>
1 V(D2:2,D2:1) 2 I(D2)
0V
200V
400V
600V
1
SEL>>
0A
6A
12A
18A
2
SEL>>
1 V(DB1:2,DB1:1) 2 I(DB1)
100V
200V
-10V
1
>>
0A
8A
16A
2
V(VOUT)
0V
200V
400V
600V
Switching Devices VPEAK and IPEAK at Start Up
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 40
V(VOUT) at start up
Total simulation time = 1056.11 seconds
D2 VKA, Peak ≈ 400V and IF, Peak ≈ 16A at start up
Q1 VDS, Peak ≈ 400V and ID, Peak ≈ 10A at start up
DB1-4 IF, Peak ≈ 10A at start up
41. Simulation with Models from the SpicePark (1/4)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 41
Load
0.5A
R12
39k
Q2
2SK2611
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 100
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47.1uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 3.74
L1
{L}
1
2
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
IS
ZCD
GND
POUT
VCC
FB_IN
IS
ZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
C2
RJJ-35V221MG5-T20
D2
SCS110AG
DB1
Diode
D3
Diode
D4
PARAMETERS:
tscale = 10
DB2
DB3
Diode
DB4
R5
10
Capacitor
model
MOSFET
professional
model
Schottky diode
model
Replace some default model with models from SpicePark
42. Time
484us 488us 492us 496us 500us 504us 508us 512us 516us 520us 524us
V(V2)
0V
40V
-I(L1)
0A
5A
10A
V(V1)
0V
250V
500V
V(Q2:g)
10V
20V
SEL>>
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(VOUT)
392V
400V
Simulation with Models from the SpicePark (2/4)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 42
V(VOUT) with high frequency ripple which is caused by ESR and ESL of the capacitor model.
Gate charge characteristics is include in the MOSFET Professional model.
V(V1)
I (L1)
V(V2)
43. Time
480us 485us 490us 495us 500us 505us 510us 515us
476us
V(V2)
40V
-20V
SEL>>
-I(L1)
0A
5A
10A
V(V1)
0V
250V
500V
V(Q1:g)
0V
10V
20V
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(VOUT)
392V
400V
Simulation with Models from the SpicePark (3/4)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 43
The Simulation Waveform with the defaults models
V(V1)
I (L1)
V(V2)
V(VOUT) without high frequency ripple which is caused by ESR and ESL of the capacitor model.
Gate charge characteristics is not include in the default model.
44. Simulation with Models from the SpicePark (1/4)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 44
SpicePark of MOSFET model
Select the device which is
capable of handling the
simulated peak values.
45. Excel Calculation Sheet (1/2)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 45
Design Specification
VAC, in,min 85 V
VAC, in,max 265 V
fin 50 Hz
VO 400 V
PO 200 W
fs 50 kHz
(assumed) 90 %
(1) Output Voltage & Feedback Circuit
R2 1.5 MW ; Input R2 value, the R1 for the VO specification is
auto-calculated
R1 9.47 kW
R1 (actual) 9.53 kW
(2) Output Capacitor
VOVP-2, MIN. 2.63 V ; VOVP-2, MIN. and Verr, MIN. are TB6819AFG electrical
characteristics
Verr, MIN. 2.46 V
C2 ³ 41 mF
(3) L1 Inductance
L1 227 mH
L1(actual) 230 mH
46. Excel Calculation Sheet (2/2)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 46
(4) Input Capacitor
C1 ³ 0.35 F
C1(actual) 1 F
(5) Auxiliary Winding L2
N1/N2 < 14
N1/N2(actual) 9.6
(6) Multiplier Input Circuit (MULT)
R9 3 MW ; Input R9 and R10 values, then check the BOP and
the Linear MULT values
R10 22 kW
Codition:
BOP 0.875 > 0.75
Linear MULT 2.728 < 3
(7) Current Detection Circuit (IS)
Iq1(max.) 5.23 A
Visp 0.57 V
R7 0.11
(8) Zero Current Detection Circuit (ZCD)
FET=ON, R8 > 13.0 k
FET=OFF, R8 > 13.9 k
R8 (actual) 68 k ; limiting the current to 1/5 of the rated current.
Remark
Input your design specification and your selected parameters. The numbers in the green font are auto-
calculated numbers. The numbers in the blue font are the design actual selected (used) number.
47. Simulation Index
All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 47
Simulations Folder name
1. Application Circuit.......................................................................
2. Application Circuit with Time Scaling (tscale
=10).........................
3. Simulation of Step (1) and (2).....................................................
4. Simulation of Step (3) and (4).....................................................
5. Simulation of Step (5).................................................................
6. Simulation of Step (6) at Vin, min...................................................
7. Simulation of Step (6) at Vin, max..................................................
8. Simulation of Step (7).................................................................
9. Simulation of Step (8).................................................................
10. Switching Devices VPEAK and IPEAK at Steady State...................
11. Switching Devices VPEAK and IPEAK at Start Up...........................
APPCKT
APPCKT_tscale
STEP1-2
STEP3-4
STEP5
STEP6_INMIN
STEP6_INMAX
STEP7
STEP8
IVPEAK-SS
IVPEAK-SU
Libraries :
1. ..parttb6819afgtb6819afg.lib
2. ..partparts.lib