This document discusses flyback converter design considerations for multi-kilowatt power conversion applications. It outlines flyback converter advantages and disadvantages, and solutions to overcome the disadvantages. Specifically, it focuses on single-stage power factor correction (PFC) applications using a flyback topology. The document discusses adapting the flyback converter for PFC, selecting an appropriate PFC control IC, modifying the control IC for high power applications, and transformer design considerations. It provides block diagrams and partial schematics as examples.

1. 1
BRUCE CARSTEN ASSOCIATES
Power Conversion Consulting & Research
6410 NW Sisters Place
Corvallis, Oregon 97330
Ph: 541-745-3935
Fx: 541-745-3923
carsten@peak.org
www.bcarsten.com
Multi-Kilowatt Flyback Converters;
Advantages and practical design considerations
With a focus on single stage PFC ac-dc applications

2. 2
Outline:
2) Flyback Converter Advantages
3) Flyback Converter Disadvantages
4) Solutions to Flyback Disadvantages
7) Selecting the PFC Control IC
8) Adapting the PFC Control IC to High Power
9) Removing the "Twice Line Frequency" Output Ripple
5) Adapting the Flyback to a Single Stage PFC
10) Proposed Improvements to the Control IC
1) Why Consider the Flyback? Cost? Efficiency?
12) References
6) Calculating Currents, etc.
11) Notes on Transformer Design, Full Schematics

3. 3
80%
85%
90%
95%
100%
2 3 4 5 7 2 3 5 kW
30 W 4 5 7 100 W 1 kW
Prototype 50 kHz, 4.5 kW PFC Flyback Converter Efficiency
90%
99
100%
98
97
96
95%
94
93
91
92
180
220
200
240
260
275V, 4.56 kW
175V, 2.02 kW
75V, 201 W
vs. Output Power, @ 230 Vac Input
vs. Vac Input
Vo, 75 Vdc
Vo, 175 Vdc
Vo, 275 Vdc
Efficiency
Efficiency
However, SiC FETs and Schottkies were enabling technologies.

4. 4
Flyback Converter Advantages
1) A Transformer and Inductor are integrated into a
single power magnetic device, with savings in size,
mass, and power loss [1].
4) The simplest isolated power converter, with a single
power transistor, rectifier, and magnetic device.
3) A buck-boost topology works efficiently over a wide
range of input/output voltage ratios.
5) For PFC applications, inrush currents are minimized,
with the energy storage capacitors on the output.
2) FET & rectifier "Component Load Factors" (in VA/W)
are essentially the same as in a forward converter [2].

5. 5
Flyback Converter Disadvantages
1) Pulsating input and output currents.
4) Twice line frequency output ripple in PFC applications.
5) For PFC, the input HF bypass capacitors need to be
placed before the input rectifier, to prevent excessive
ac line current distortion at zero voltage crossing.
2) The transformer leakage inductance energy must be
dealt with, which is more difficult in PFC applications.
3) A RHP zero in the control function (common to all
buck-boost, and not important in PFC applications).

6. 6
Dealing with the Disadvantages: Pulsating Currents
2) Pulsating input and output currents are reduced by
interleaving, by 1/N (N = the number of "phases").
A) Operate in light and heavy current modes at
constant frequency, and thus;
3) But, this requires a control circuit that can:
B) Be locked to a master multi-phase clock, and;
C) Be forced to share current or power.
1) High power converters typically operate at higher
voltages, where pulsating currents are easier to filter.
(Will be covered later)

7. 7
Transformer Leakage Inductance
2) A "resonant reset".
3) A two transistor flyback converter.
4) With a tertiary clamp winding.
5) With an active clamp.
6) Passive clamp with active discharge.
7) Passive clamp and energy recovery circuit.
The leakage inductance "spike" can be clamped by:
1) Dissipative (passive) clamps.

8. 8
Dissipative Clamping
Zener/TVS Clamp
Tightest clamp voltage
Limited power capability
R-C-D Clamp
Variable clamp voltage
High power capability
Low cost
Resonant
Reset
Capacitor Only
Advisable for
"boundary mode"
operation only
Low loss, low cost
Hi FET peak voltage

9. 9
Two Transistor Flyback Converter
High Efficiency, with clamp energy recovery
Flyback voltage limited to Vin, unsuitable for PFC
applications where high boost required as Vin
goes to zero.
Duty cycle limited to 50%, and:

10. 10
Tertiary Clamp Winding
High Efficiency, with clamp energy recovery
Still unsuitable for PFC applications where
high boost required as Vin goes to zero.
Duty cycle can be greater than 50%, but:
A coupling capacitor can be used to
overcome pri-ter leakage inductance
voltage voltage spike when Np:Nt = 1:1

11. 11
Active Clamp Flyback Converter
Output current waveform reaches a peak at
the end of the "off" period.
Q1
Q2
High Efficiency, with clamp energy recovery.
Potentially suitable for PFC applications, but:
Minimum peak voltage on main FET.
Some ZVS achievable, improving efficiency.
Driving of a "high side" FET required;
Vi Vo
0
Vi
Vi + Vo
IS
VQ1
LIGHT LOAD
IQ2
IP,
IP+S
0
Vi
Vi + Vo
VQ1
HEAVY LOAD
IP+S
IS
Clamp FET current similar to main FET, much
higher than in the active clamp forward;
(A little harder to analyze)
IQ1
IP,
IQ1
IP,
IQ2
IP,
(Goggle "active clamp flyback" for more information)
IP
IS
(For my early "active clamp" forward converters, see [3], [4])

12. 12
Passive Clamp with Active Discharge
High power capability.
This was the clamp method of choice for the prototype.
Constant clamp voltage.
Minimum loss for a dissipative clamp.
Conceptual
Circuit
One clamp can serve multiple interleaved phases.

13. 13
Passive Clamp with Energy Recovery Circuit
A buck regulator has been used to
return clamp energy to the input.
Clamp voltage can be constant, or controlled.
Efficient clamp energy recovery.
Will work with PFC, but:
A high side FET drive is required;
A high inductance, low current choke is required. In my
case, about 50 mA drawn from a 1 kV clamp voltage.

14. 14
Adapting the Flyback to a Single Stage PFC
1) A bridge rectifier input was chosen for simplicity and
cost, despite the nearly 1% power loss.
2) As noted, the only "adaptation" required is that the HF
switching current bypass capacitors must be before the
bridge rectifier to prevent high line current distortion:
Small HF
bypass cap
10x
AC
Input
2.2 uF

15. 15
3) These capacitors now need to be "X2" rated for "safety",
and carry the full pulsating FET switching currents.
4) I found that 2.2 uF, 275 Vac polypropylene capacitors
had an ESR of 10 - 15 mohm at 50 kHz, rising to 20 - 25
mohm at 500 kHz, and could thus easily carry several
amps of ripple current each. Ten such caps were used,
5) The input rectifier must also carry the switching current,
and I was concerned that forward recovery losses may
occur for each pulse.
6) Fortunately, in conventional P-N rectifiers the charge
carrier lifetime was sufficiently long that this was not a
problem.

16. 16
4.5 kW PFC Flyback Block Diagram
Fuses
& MOV
AC
Input
Relay
EMI Filter
& Bypass
Capacitors
Bridge
Rectifier
PS2, 230 Vac
to +18Vdc
+12V to
Output Logic
+18V to
Input
Logic
A1
Input Regulation
and Control
A2
Output Control
Output
Capacitor
Bank
DC
Output
Isolation
Boundary
PS1, 230 Vac
to +12Vdc
Flyback Power
Converter "A"
Flyback Power
Converter "B"

17. 17
File: Buck-Boost (Magnetics) Voltage and Current Calculations
Calculated 05/01/15 *05/31/15: IL'pk
= Ii/2D + 30.67(1-D) [1 of 2 phases, L = 90 uH]
0 - 10
10 - 20
20 - 30
30 - 40
40 - 50
50 - 60
60 - 70
70 - 80
80 - 90
5
15
25
35
45
55
65
75
85
Vac:
220
Vrms,
311.1
Vpk
Iac:
21.1
Arms,
29.8
Apk
27.1
80.5
131.5
178.4
220.0
254.8
282.0
300.5
309.9
24.69
62.33
89.05
108.37
122.41
132.50
139.47
143.86
145.99
0.9105
0.7742
0.6773
0.6073
0.5565
0.5199
0.4947
0.4788
0.4711
7.9
106.0
287.8
498.6
701.3
875.4
1010.6
1102.2
1148.4
8.14
99.25
345.7
792.2
1433.7
2204.6
2980.6
3614.2
3971.0
2.60
7.71
12.59
17.09
21.07
24.41
27.01
28.78
29.69
7.41
76.84
234.2
481.1
797.9
1146.2
1474.5
1730.5
1870.7
0.255
2.250
6.00
11.05
16.79
22.54
27.59
31.33
33.33
0.73
22.41
111.6
311.1
635.9
1058.4
1506.1
1883.7
2100.2
41.43 29.48 16.79
29.12
rms or
Effective
Vrms(CALC)
= 219.98 5.738x106


B(EFF) = 118.3

(EFF/NORM) = 0.857
Irms(CALC)
= 21.10
B(EFF) = 114.6

(EFF/NORM) = 0.830
610
3,886
7,931
11,745
17,556
14,985
19,452
20,697
21,313

17 (4.2)
142 (11.9)
368 (19.2)
682 (26.1)
1058 (32.5)
1459 (38.2)
1832 (42.8)
2120 (46.0)
2278 (47.7)
33.3
Calculating the Flyback Converter Currents, etc.
Mean
Vi


 D
Vo: 276 Vdc Assumed: No Current Ripple
Pi: 4.64 kW
B
=Vo(1-D)
B(NORM) = 0.5 V0 = 138
B2.8

Ii = Ipk (Sin )
D =Vo/(Vi+Vo)
x 103
B(EFF) = 8
.
2
9
/

Vi = Vpk (Sin )

Ii
(Ii/D)2
(IWDG)2
Ii2
/ D
(IFET)2
Ii2
(1-D)/D2
(IDIODE(rms))2
Ii(1-D)/D
(IDIODE(ave))
Bridge Rectifier Vf = 0
 B2
x 103
Leakage Ind.*
IL'pk
2
(IL'pk)

18. 18
0 1 2
IP-P / IAVE
1.00
1.20
1.10
1.15
1.05
IAVE
Irms
1.155
The rms current of a ramp current pulse can
be approximated by the average current:
Current Pulse with
IP-P / IAVE = 1.0
0
IP-P
I1
I2
IAVE
Irms =
+ I1
I2
+ I2
2
) 3
(I1
2
(Located on the inside back cover of your notes)

19. 19
200 220 240 260 280
180
50
45
40
35
30
25
20
15
10
5
0
Currents,
A
Input Voltage, Vac
Iac(rms)
IWDG(rms)
VWDG(ave), B2.8
IFET(rms)
IRECT(rms)
IRECT(ave)
300
270
240
210
180
150
120
90
60
30
0
Winding
Voltage
B2.0

20. 20
Control Circuit Options
1) For PFC ac-dc applications, there are a number of PFC
flyback control circuits available.
3) Most operate either in boundary mode (variable
frequency), or in light mode at constant frequency.
5) I found only one control IC that could meet the minimum
requirements, the ON Semiconductor NCP1652 series.
4) But, it is highly desirable to operate in heavy mode at
maximum peak power to avoid excessive rms currents.
2) However, they all seem to have been developed for low
power LED luminaire applications at 20W to 200 W.

21. 21
1) Operates in light and heavy mode at constant frequency;
2) Can be injection locked to a master clock;
3) The control input is an output power control, regardless
of ac input or dc output voltage.
The NCP 1652:
However, the control IC does have numerous disadvantages
for high power applications that need to be overcome:
1) It is noise sensitive (not uncommon for control ICs).
2) Will not start up with an external Vcc power applied.

22. 22
3) The IC goes into "soft skip" at light loads, ostensibly to
conserve power, but didn't work well in my application.
5) No instantaneous peak current limiting
6) Significant output voltage overshoot upon startup (which
is common to PFC circuits, due to low control bandwidth)
4) Problems in synchronizing start up in interleaved
operation, due to a Startup "abort" after time-out without
achieving output voltage regulation.
NCP 1652 Disadvantages (cont.)
"Fixes" will be shown in a few partial schematics,
most in full schematics provided at the end.

23. 23
R4A
330R
C6A
100n
R3A
7k5
C3A
4u7
R2A
7k5
C2A
1n0
R1A
30k
C1A
1n0
C4A
100n
C5A
2n2
R5A
10k
C9A
33n
100n
C8A
R6A
47k
C7A
1n0
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Control IC Board Circuitry
10V
U1A NCP1652A
1
2
3
4
5
6
7
8
CT
Ramp
Comp
AC in
FB
VFF
CM
AC Comp
Latch
Off
Rdelay
Startup
GND
Out B
Out A
Vcc
Ispos
Iavg
11
12
13
14
15
16
9
10
The PFC flyback control IC is very sensitive to noise on its inputs.
This was overcome by using an SO to DIP adapter with
pads for SMD components and an embedded ground plane

24. 24
NCP1652AG
http://www.electroboards.com/
ElectroBoards: S016-50-EB
103
303
752
752
473
100n
33n
1n0
100n
2n2
While SMD in series are "tented"
SMD in parallel are stacked:
SO to DIP adapter with the control
IC and SMD components in place

25. 25
Part of Input Control Board
10k
ZVP2106A
33k
33k
1k0
1N4148
10n
2N7000
Q1A
D S
G
D
S
G
25V
6u8
C11A
BAT48
R10A
R4A
330R
C6A
100n
R3A
7k5
C3A
4u7
R2A
7k5
C2A
1n0
R1A
30k
C1A
1n0
C4A
100n
C5A
2n2
R5A
10k
C9A
33n
100n
C8A
R6A
47k
C7A
1n0
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Control IC Board A2A
10V
C10A
R7A R8A
R9A
Q2A
U1A NCP1652A
1
2
3
4
5
6
7
8
CT
Ramp
Comp
AC in
FB
VFF
CM
AC Comp
Latch
Off
Rdelay
Startup
GND
Out B
Out A
Vcc
Ispos
Iavg
11
12
13
14
15
16
9
10
D1A
D2A
AC
in
Vff
Stup
Dr.
B
11
IsnsB
12
2
1 3
IN
Com
4
Dr.
A
5
IsnsA
6 7 8 9 10
NC
IN
Com
NC
NC
1N4148
D11A
BAT85
D12A
Ext.
Vcc
Input
Startup with an
ext.Vcc input
D3A
BAT48
R11A
2R7
R12A
2R7
10R
R13A
Z1A 1N5261B
47V

26. 26
(12"
Black
wires)
Top Schematic
4.5 kW PFC Flyback Converter
DC
Output
R13 200k
R11 180k
C24
2u2
275 Vac
1N4007
D7
R14 200k
R12 180k
Vac(L)
Vac(N)
+Vo
-Vo
PS2 +18V
VOFM-5-18
25V
82u
C31
R10
10k
2W
55W
10R
R17
10k
Q4
STP45N40
DM2AG
R7
On
Chassis
+Vo
-Vo
Vclamp
IsnsA
Dr. A
+18V
+Vrect
In Com
10k
R18
Power Converter
Circuit "A"
+18V
78L15
3
2
1
com
In Out
U3
+15V
+Vo
-Vo
Vclamp
IsnsB
Dr. B
+18V
+Vrect
In Com
Power Converter
Circuit "B"
+18V
+18V
Isolation
Boundary
0.25"
Min
Separation
DB1
GBPC
3510W
Input Com
Output Com
AC Ground
(to chassis)
HS3
HS4
R15 10k
R16
100k
Z7
IN4749A
24V
Q3
TN0104N3-G
+12V
230 Vac
Input
F1
ABC 30A K1
T92S7D12-12
F2
ABC 30A
VR1
275V
F3
1A
250V
Vac1
Vac2
AC
GND
Isolation Boundary
0.25" Min Separation
RAC04-12SC/277
Vac(N)
+Vo
6
-Vo
2
3
PS1
+12V
+12V
25V
82u
C32
Vac(L)
5
A2
Output
Control
Board
1
2
3
4
IN Com
NC
Enable
NC
9
10
11
12 IN Com
FB
16
15
14
13
18
17
ENA
PWR
MV
HV
+12
Out com
24
22
21
Disch
NC
+Vo
(1.8" x 1.8"
pin grid,
2.0" x 2.0"
overall.)
+12V
External
Control
Input
TS1
TS2
TS3
TS5
TS4
1
2
3
4
5
6
IN Com
P2
P4
130k
R21
+15V
4584B
Q5
NDFP03
N150CG
5x
10k
R19
14
7
62k
R20
Design;
Trip: 1113V
Reset: 1087V
HS5
U2
1k0
55W
P3
5
6 NC
NC 20
19
Pwr-ON
7
8 Mode 3
IN Com
Out com
NC
R9
100k
2W
230
Vac
to
Fan(s)
P1
L1 33uH
10x 2u2
275 Vac
WIMA
MKP2
C10 - C19
13T of 2ll #15
on "T250-40"
2u2
275
Vac
C21
L2 2.5mH
2u2
275
Vac
C20
2u2
275
Vac
C22
L3 2.5mH
C25
4n7
2u2
275
Vac
C23
C27
4n7
C29
4n7
C26
4n7
C28
4n7
C30
4n7
On
Chassis
Brn.
Red
Or.
Yel.
Grn.
Blu.
8 x 1,000u, 400V
C33 - C40
+Vo -Vo
5x 1N5281B
Z6 Z5 Z4 Z3
Z8
R8B
R8A
1k0
55W
+18V
(1.9" x 2.2" pin grid,
2.1" x 2.4" overall.)
R17 R16
FB
Mode 3
+15V
IN Com
+18V
IN Com
Stup
AC
in
VFF
Dr.
A
IsnsA
IN
Com
Dr.
B
IsnsB
IN
Com
NC
NC
NC
8
7 9 11
10 12
2
1 3 5
4 6
NC
NC
NC
NC
Enable
IN Com
14
13
15
17
16
18
20
19
21
23
22
24
A1
Input Regulation Control Board
+15V
Modifications to A1 & A2 pinouts
Active Discharge
of Passive Clamp

27. 27
Input
Control
Board
A1
FB
D3A
BAT48
10k
ZVP2106A
33k
33k
1k0
1N4148
10n
2N7000
Q1A
D
S
G
D
S
G
25V
6u8
C11A
BAT48
R10A
R11A 2R7
R12A 2R7
10R
R13A
10k
ZVP2106A
33k
33k
1N4148
D
S
G
D
S
G
BAT48
R10B
R4A 330R
C6A 100n
R3A 7k5
C3A 4u7
R2A 7k5
C2A 1n0
R1A 30k
C1A 1n0
C4A 100n
C5A 2n2
R5A 10k
C9A 33n
100n
C8A R6A 47k
C7A 1n0
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Control
IC
Board
A2A
Mode
3
20
+18V
19
+15V
2N7000
Q1B
Input
Com
21
10V
C10A
R7A
R8A
R9A
Q2A
U1A
NCP1652A
1
2
3
4
5
6
7
8
CT
Ramp
Comp
AC
in
FB
V
FF
CM
AC
Comp
Latch
Off
R
delay
Startup
GND
Out
B
Out
A
V
cc
I
spos
I
avg
11
12
13
14
15
16
9
10
D1A
D2A
D2B
Q2B
R7B
R8B
R9B
D1B
AC in
Vff
Stup
Dr. B
11
IsnsB
12
2
1
3
IN Com
4
Dr. A
5
IsnsA
6
7
8
9
10
NC
IN Com
NC
NC
22
23
24
Input
Com
14
13
15
16
17
18
NC
NC
NC
NC
ENA
NC
Z1A
1N5261B
D9A
D9B
BAT85
D10
BAT85
BAT85
Q4
2N4126
R19
4k3
R18
4k3
Q3
2N4126
R20
470k
Z2
1N5240B
R21
75K
Clock
Phase
B
R14
47k
1
3
2
cw
4584B
R17
10k
1
3
2
cw
R16
200k
R15
200k
C13
100p
C12
220p
C14
100p
C15
100p
1N4148
1N4148
1N4148
1N4148
1N4148
Frequency
Duty
Cycle
Master
Clock
7
14
Clock
Phase
A
U2
D4
D5
D6
D7
D8
C16
100n
11
3
13
2
12
1
8
6
5
9
4
10
1N4148
D11A
1N4148
D11B
1k0
25V
6u8
C11B
R4B 330R
C6B 100n
R3B 7k5
C3B 4u7
R2B 7k5
C2B 1n0
R1B 30k
C1B 1n0
C4B 100n
C5B 2n2
U1B
NCP1652A
1
2
3
4
5
6
7
8
CT
Ramp
Comp
AC
in
FB
V
FF
CM
AC
Comp
Latch
Off
R
delay
Startup
GND
Out
B
Out
A
V
cc
I
spos
I
avg
11
12
13
14
15
16
9
10
R5B 10k
C9B 33n
100n
C8B R6B 47k
C7B 1n0
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Control
IC
Board
A2B
D3B BAT48
R11B 2R7
R12B 2R7 10R
R13B
Z1B 1N5261B
47V
47V
1N5244B
Z3
14V
Q6
Q5
TN0104N3-G
2N4124
R22
200K
R23
180K
1N5244B
Z4
R25
10K
R24
10K
14V
BAT85
D12A
10n
C10B
BAT85
D12B
Q7
2N7000
"Soft
skip"
holdoff
(pulls
down
input
voltage
sensing)
"Mode
3"
(low
power)
shuts
down
one
power
circuit,
and:

28. 28
Output Control Board
R18
51k
R16
118k
2
1
3
4
C2
1u0
R24
4k7
U4
TL431IB
U6
SFH615A-4
2
3
1
P1
1n0
300
Vac
1n0
22n
2
3
1
2
3
6
U3
TL431IB
1
3
2
cw
R15
100k
Mode
#1 Adj.
R22
1k5
R21
1k5
1
2
3
4
5
ENA
PWR
MV
HV
+12
+12
4584B
Pwr-ON
R10 10k
R5
R7 3k9
1 3
2
cw
R11 20k
1 3
2
cw
R12 50k
R13 50k
U2
TL431IB
2
3
1
7.75V
+12V
R9
8k2*
R8
3k9*
* Selected for
2.10:1 Ratio
3k9
Mode #2 Adj.
Mode
#3 Adj.
R6
3k9
R1 10k
R2 10k
R3
R4
10k
10k
FB
Input
COM
Disch.
7
2
1
3
4
U7
SFH615A-4
P1
Mode 3
Input
COM
R17
118k
+Vo
U1
D1
1N4148
1N4148
D2
+12V
14
D4
1N4148
D5
D6
D7
D8
1N4148
1N4148
1N4148
1N4148
C3
C4
C5
3
4
2 1
10 11
12 13
6 5
8 9
100n
C6
R26
1K3
R25
1k0
+12V
R20
3k3
R19
100R
1
3
2
cw
R14
200R
OVP
Adj
R28
20k
+12V
C1 1n0
R23
7
3k3
LMC6081
U5 4
100n C7
6
Gnd
J1
R29 10k
2
1
3
4
U8
SFH615A-4
P1
Enable
Input
COM
R28
10k
"Mode 3" (low power) Shuts
down one power circuit, holds
off "soft skip" by pulling down
on input voltage sensing.
R27 10k
"Enable" allows power
conversion to start.
U3 halts power conversion with
a few % output overvoltage

29. 29
200:1
Power Converter
Circuit A
ENA
1
2
3
4 INB
GND
INA
ENB 8
7
6
5
OUTA
Vdd
OUTB
UCC27528
10n
Isolation
Boundary
0.25"
Min
Separation
U1A
4u7
C3A
+Vrect
1
2
3 4
6
5
T4A
CCMCK-3
In Com
Dr A
+18V
BAT85
680p
C6A
1R0
R24A
D4A
T2A
C8A
D6A
C1A
150n
1.6 kV
C4D02120A
C2A
D2A
86
uH
C9A 4n7
1u0 630V
Vclamp
Q1A
C2M0040120D
1
2 3
4
86
uH
T1A
HS1A
The T1 core will be sitting on
the topside INPUT copper
YW40705-TC
1R0
R1A
25V
BAT85
BAT48
1N5261B
Z2A 47V
T5A
R3A2
10R
Q2A
BAT85
D5A
2N4401
D3A
100R
R2A 10R
300R
R23A
2N3906
Q6A
1.0 V
R3A1
R4A 1k5
3k6
R22A
D1A C4D20120A
390R 5W
C4A1 R5A
220p
+Vo
-Vo
HS2A
C4A2
220p
390R 5W
C5A1 R6A
220p
C5A2
220p
200:1
T3A
IsnsA
Peak Current Limiting Circuit

30. 30
(Note that, in three phase applications, this twice line frequency ripple
issue goes away.)
Logic &
Drive
The "Twice Line Frequency" Output Ripple can be Removed with:
Boost Regulator
The semiconductor "Component Load Factor" (V-A/W) in a buck or boost
regulator can be as low as 1/4 of that in a dc-dc converter or a buck-boost
regulator.
In each case the dc output current is always flowing through either an
additional FET or diode.
There is some preference for the boost regulator, in part because the
FET rms current will be lower, although the diode current higher
Logic &
Drive
or a Buck Regulator

31. 31
Logic &
Drive
Logic &
Drive
"Twice Line Frequency" Output Ripple Removal Through "Trim" Regulators
Boost Trim Regulator Buck Trim Regulator
The total V-A in the regulator is now an order of magnitude less,
including the filter inductor and FET, but:
High current now in two additional (but lower voltage) diodes
High ripple current now in additional (but lower voltage) capacitors

32. 32
"Twice Line Frequency" Output Ripple Removal Through dc-ac "Trim" Inverter
Output "Trim" Inverter
Another possibility is a non-isolated low voltage
dc-ac "inverter" to cancel the LF output ripple.
The inverter FETs carry the output current, but
at only a low voltage. Silicon FETs would be
adequate.
One advantage is that there is no net power
output from the inverter, so the tertiary output
is low power, supplying only the losses in the
inverter.
A detailed analysis would determine which ripple
removal approach would have the greatest cost
and/or performance advantages.

33. 33
Proposed Improvements to the Control IC
1) "Soft skip" at light loads.
Features to get rid of:
2) Bootstrap self-start circuitry, and its associated need to
believe it started up itself. Replace with external Vcc
power source, or at least start up if external Vcc applied.
3) Remove the internal frequency dithering.
4) The "Out B" doesn't seem to be of any use. (Out of
phase with main drive output, with non-overlap dead
times.

34. 34
1) A more readily synchronizable clock, or perhaps an
external clock input.
Features to add:
2) Built in, fast peak current limiting.
3) A fast ac line OVP shutdown at, say, 450 V peak, with
recovery at 400 V, or set with scaling resistors. This
can be an "instantaneous" shutdown and recovery, still
trying to operate when the line voltage before the
rectifier is low enough.
4) Possibly, a convenient "inhibit" input, to allow stopping
of one or more interleaved converter phases at light
loads.

35. 35
Custom Transformers by:
50 mm
Primary
Secondary
30 mm
2.25 kW Flyback
Transformer Design
Windings: Pri. & Sec. both 18 turns of 50 micron
copper foil, 50 mm wide.
Insulation: 50 micron Nomex between winding layers,
3 layers of 127 micron Nomex between.
Pri. & Sec. Term.: 250 micron copper, 10 mm wide.
The winding sequence of the second Pri.-Sec. pair
is the same as the first, except that the termination
tabs are brought out of the opposite end, so that
the windings can be connected directly in parallel.
I wanted to use their magnetically biased InDUR MaxFlux
inductor technology, which would have reduced the size
and leakage inductance, but the biasing magnets are not
yet thin enough to work with foil winding with high ripple.
Spezial-Transformatoren
Stockach GmbH & Co.

36. 36
Early 4.5 kW Flyback with One Power Circuit

37. 37
References:
[1] B. Carsten, "Converter Component Load Factors; A performance Limitation of Various
Topologies", proceedings of PCI '88 Conference, Munich, Germany
[2] B. Carsten, "On the Fundamental Performance Similarities of Flyback and Forward
Converters at High Frequencies", proceedings of PCI '87 Conference, Long Beach, CA
[3] B. Carsten, "High Power SMPS Require Intrinsic Reliability", proceedings of PCI '81
Conference, Munich, Germany
[4] B. Carsten, "Design Techniques for Transformer Active Reset Circuits at High
Frequencies and Power Levels", proceedings of HFPC '90 Conference, Santa Clara, CA