Concepts of Behavioral modelling in Verilog HDL

Timing Controls
Various behavioral timing control constructs are available in Verilog. In Verilog, if there
are no timing control statements, the simulation time does not advance. Timing controls
provide a way to specify the simulation time at which procedural statements will
execute.
There are three methods of timing control: delay-based timing control, event-based
timing control, and level-sensitive timing control.
Delay-Based Timing Control
Delay-based timing control in an expression specifies the time duration between when
the statement is encountered and when it is executed.
Delays are specified by the symbol #.
Syntax for the delay-based timing control statement is shown below:
delay3 ::= # delay_value | # ( delay_value [ , delay_value [ ,delay_value ] ] )
delay2 ::= # delay_value | # ( delay_value [ , delay_value ] )
delay_value ::= unsigned_number | parameter_identifier | specparam_identifier |
mintypmax_expression
There are three types of delay control for procedural assignments: regular delay control,
intra-assignment delay control, and zero delay control.
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Verilog HDL_18EC44 by Anand H D, Dr. AIT,
Bengaluru-56

Regular delay control
Regular delay control is used when a non-zero delay is specified to the left of a procedural
assignment.
// no delay control
// delay control with a number. Delay execution of y = 1 by 10 units
// Delay control with identifier. Delay of 20 units
// Delay control with expression
// Delay control with identifier. Take value of y.
/* Minimum, typical and maximum delay values. Discussed in gate-level
modeling chapter.*/
//define parameters
parameter latency = 20;
parameter delta = 2;
//define register variables
reg x, y, z, p, q;
initial
begin
x = 0;
#10 y = 1;
#latency z = 0;
#(latency + delta) p = 1;
#y x = x + 1;
#(4:5:6) q = 0;
end
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Intra-assignment delay control
Instead of specifying delay control to the left of the assignment, it is possible to assign a
delay to the right of the assignment operator.
Such delay specification alters the flow of activity in a different manner.
reg x, y, z; //define register variables
//intra assignment delays
initial
begin
x = 0; z = 0;
y = #5 x + z;
end
/*Equivalent method with temporary variables and
regular delay control*/
initial
begin
x = 0; z = 0;
temp_xz = x + z;
#5 y = temp_xz;
end
/*Take value of x and z at the time=0,
evaluate x + z and then wait 5 time
units to assign value to y.*/
/*Take value of x + z at the current time and
store it in a temporary variable.
Even though x and z might change between 0 and 5*/
 Note the difference between intra-
assignment delays and regular delays.
 Regular delays defer the execution of
the entire assignment.
 Intra-assignment delays compute the
righthand-side expression at the
current time and defer the assignment
of the computed value to the left-
hand-side variable.
 Intra-assignment delays are like using
regular delays with a temporary
variable to store the current value of a
right-hand-side expression.
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module blocking_nonblocking();
reg a,b,c,d;
initial begin
#10 a = 0;
#11 a = 1;
#12 a = 0;
#13 a = 1;
end
initial begin
#10 b <= 0;
#11 b <= 1;
#12 b <= 0;
#13 b <= 1;
end
initial begin
c = #10 0;
c = #11 1;
c = #12 0;
c = #13 1;
end
initial begin
d <= #10 0;
d <= #11 1;
d <= #12 0;
d <= #13 1;
end
initial begin
$monitor("TIME = %g A = %b B = %b C = %b D = %b",$time, a, b, c, d);
#50 $finish;
end
Simulator Output:
TIME = 0 A = x B = x C = x D = x
TIME = 10 A = 0 B = 0 C = 0 D = 0
TIME = 11 A = 0 B = 0 C = 0 D = 1
TIME = 12 A = 0 B = 0 C = 0 D = 0
TIME = 13 A = 0 B = 0 C = 0 D = 1
TIME = 21 A = 1 B = 1 C = 1 D = 1
TIME = 33 A = 0 B = 0 C = 0 D = 1
TIME = 46 A = 1 B = 1 C = 1 D = 1
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reg a,b,c,d;
initial begin
#10 a = 0;
#11 a = 1;
#12 a = 0;
#13 a = 1;
end
initial begin
#10 b <= 0;
#11 b <= 1;
#12 b <= 0;
#13 b <= 1;
end
initial begin
c = #10 0;
c = #11 1;
c = #12 0;
c = #13 1;
end
initial begin
d <= #10 0;
d <= #11 1;
d <= #12 0;
d <= #13 1;
end
10 a <= 0;
21 a <= 1;
33 a<= 0;
46 a <= 1;
10 b <= 0;
21 b <= 1;
33 b<= 0;
46 b <= 1;
10 c <= 0;
21 c <= 1;
33 c<= 0;
46 c <= 1;
10 d <= 0;
11 d <= 1;
12 d <= 0;
13 d <= 1;
Simulator Output:
TIME = 0
TIME = 10
TIME = 11
TIME = 12
TIME = 13
TIME = 21
TIME = 33
TIME = 46
A = x
A = 0
A = 0
A = 0
A = 0
A = 1
A = 0
A = 1
B = x
B = 0
B = 0
B = 0
B = 0
B = 1
B = 0
B = 1
C = x
C = 0
C = 0
C = 0
C = 0
C = 1
C = 0
C = 1
D = x
D = 0
D = 1
D = 0
D = 1
D = 1
D = 1
D = 1
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reg a,b,c,d;
initial begin
#10 a = 0;
#11 a = 1;
#12 a = 0;
#13 a = 1;
end
initial begin
#10 b <= 0;
#11 b <= 1;
#12 b <= 0;
#13 b <= 1;
end
initial begin
c = #10 0;
c = #11 1;
c = #12 0;
c = #13 1;
end
initial begin
d <= #10 0;
d <= #11 1;
d <= #12 0;
d <= #13 1;
end
initial begin
$monitor("TIME = %g A = %b B = %b C = %b D = %b",$time, a, b, c, d);
#50 $finish;
end
Simulator Output:
TIME = 0 A = x B = x C = x D = x
TIME = 10 A = 0 B = 0 C = 0 D = 0
TIME = 11 A = 0 B = 0 C = 0 D = 1
TIME = 12 A = 0 B = 0 C = 0 D = 0
TIME = 13 A = 0 B = 0 C = 0 D = 1
TIME = 21 A = 1 B = 1 C = 1 D = 1
TIME = 33 A = 0 B = 0 C = 0 D = 1
TIME = 46 A = 1 B = 1 C = 1 D = 1
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Zero delay control
initial
begin
x = 0;
y = 0;
end
initial
begin
#0 x = 1; //zero delay control
#0 y = 1;
end
In this Example, four statements
x = 0, y = 0, x = 1, y = 1 are to be executed at
simulation time 0.
However, since x = 1 and y = 1 have #0, they
will be executed last. Thus, at the end of time
0, x will have value 1 and y will have value 1.
The order in which x = 1 and y = 1 are executed
is not deterministic.
Using #0 is not a recommended practice.
Procedural statements in different always-initial blocks may be evaluated at the same
simulation time.
The order of execution of these statements in different always-initial blocks is
nondeterministic.
Zero delay control is a method to ensure that a statement is executed last, after all other
statements in that simulation time are executed.
This is used to eliminate race conditions. However, if there are multiple zero delay
statements, the order between them is nondeterministic.
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Event-Based Timing Control
An event is the change in the value on a register or a net. Events can be utilized to trigger
execution of a statement or a block of statements.
There are four types of event-based timing control: regular event control,
named event control,
event OR control, and
level sensitive timing control.
Regular event control:
The @ symbol is used to specify an event control.
Statements can be executed on changes in signal value or at a positive or negative
transition of the signal value.
The keyword posedge is used for a positive transition.
@(clock) q = d;
@(posedge clock) q = d;
@(negedge clock) q = d;
q = @(posedge clock) d;
//q = d is executed whenever signal clock changes value
/*q = d is executed whenever signal clock does a positive
transition ( 0 to 1,x or z, x to 1, z to 1 )*/
/*q = d is executed whenever signal clock does a negative
transition ( 1 to 0,x or z,x to 0, z to 0) */
/*d is evaluated immediately and assigned to q at the positive
edge of clock*/ 8
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Named event control
Verilog provides the capability to declare an event and then trigger and recognize the
occurrence of that event.
The event does not hold any data. A named event is declared by the keyword event.
An event is triggered by the symbol ->. The triggering of the event is recognized by the
symbol @.
//This is an example of a data buffer storing data after the last packet of data has
arrived.
event received_data;
always @(posedge clock)
begin
if(last_data_packet)
->received_data;
end
//Define an event called received data
//check at each positive clock edge
//If this is the last data packet
//trigger the event received_data
always @(received_data)
data_buf = {data_pkt[0], data_pkt[1], data_pkt[2], data_pkt[3]};
//Await triggering of event received_data
//When event is triggered, store all four packets of received data in data buffer using
concatenation operator { }
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Event OR Control
Sometimes a transition on any one of multiple signals or events can trigger the execution
of a statement or a block of statements. This is expressed as an OR of events or signals.
The list of events or signals expressed as an OR is also known as a sensitivity list.
The keyword or is used to specify multiple triggers.
//A level-sensitive latch with asynchronous reset
always @( reset or clock or d)
begin
if (reset)
q = 1'b0;
else if(clock)
q = d;
end
Sensitivity lists can also be specified using the "," (comma) operator instead of the or
operator. Comma operators can also be applied to sensitivity lists that have edge-
sensitive triggers.
//Wait for reset or clock or d to change
//if reset signal is high, set q to 0.
//if clock is high, latch input
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//A level-sensitive latch with asynchronous reset
always @( reset, clock, d)
begin
if (reset)
q = 1'b0;
else if(clock)
q = d;
end
A positive edge triggered D flipflop with asynchronous falling reset can be modeled as
shown below
//Wait for reset or clock or d to change
//if reset signal is high, set q to 0.
//if clock is high, latch input
//Note use of comma operatoralways @(posedge clk, negedge reset)
if(!reset)
q <=0;
else
q <=d;
end
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When the number of input variables to a combination logic block are very large,
sensitivity lists can become very cumbersome to write.
Moreover, if an input variable is missed from the sensitivity list, the block will not behave
like a combinational logic block.
To solve this problem, Verilog HDL contains two special symbols: @* and @(*).
Both symbols exhibit identical behavior.
These special symbols are sensitive to a change on any signal that may be read by the
statement group that follows this symbol.
Use of @* Operator
always @(a or b or c or d or e or f or g or h or p or m)
begin
out1 = a ? b+c : d+e;
out2 = f ? g+h : p+m;
end
//Combination logic block using the or operator
//Cumbersome to write and it is easy to miss one input to the block
always @(*)
begin
out1 = a ? b+c : d+e;
out2 = f ? g+h : p+m;
end
//Instead of the above method, use @(*) symbol
//Alternately, the @* symbol can be used
//All input variables are automatically included in the sensitivity list.
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Level-Sensitive Timing Control:
Event control discussed earlier waited for the change of a signal value or the triggering of
an event.
The symbol @ provided edge-sensitive control.
Verilog also allows level sensitive timing control, that is, the ability to wait for a certain
condition to be true before a statement or a block of statements is executed.
The keyword wait is used for level sensitive constructs.
always
wait (count_enable) #20 count = count + 1;.
In the above example, the value of count_enable is monitored continuously.
If count_enable is 0, the statement is not entered.
If it is logical 1, the statement count = count + 1 is executed after 20 time units.
If count_enable stays at 1, count will be incremented every 20 time units
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Conditional Statements:
Conditional statements are used for making decisions based upon certain conditions.
These conditions are used to decide whether or not a statement should be executed.
Keywords if and else are used for conditional statements.
There are three types of conditional statements:
//Type 1 conditional statement. No else statement.
//Statement executes or does not execute.
//Type 2 conditional statement. One else statement
//Either true_statement or false_statement is evaluated
//Type 3 conditional statement. Nested if-else-if.
//Choice of multiple statements. Only one is executed.
if (<expression>) true_statement ;
if (<expression>) true_statement ; else false_statement ;
if (<expression1>) true_statement1 ;
else if (<expression2>) true_statement2 ;
else if (<expression3>) true_statement3 ;
else default_statement ; 14
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The <expression> is evaluated. If it is true (1 or a non-zero value), the true_statement is
executed. However, if it is false (zero) or ambiguous (x), the false_statement is executed.
The <expression> can contain any operators. Each true_statement or false_statement
can be a single statement or a block of multiple statements.
A block must be grouped, typically by using keywords begin and end. A single statement
need not be grouped.
//Type 1 statements
if(!lock) buffer = data;
if(enable) out = in;
//Type 2 statements
if (number_queued < MAX_Q_DEPTH)
begin
data_queue = data;
number_queued = number_queued + 1;
end
else
$display("Queue Full. Try again"); 15
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//Type 3 statements
//Execute statements based on ALU control signal.
if (alu_control == 0)
y = x + z;
else if(alu_control == 1)
y = x - z;
y = x * z;
else
$display("Invalid ALU control signal");
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Examples on Conditional Statements
module simple_if();
reg latch;
wire enable,din;
always @ (enable or din)
if (enable)
Begin
latch <= din;
end
endmodule
module if_else();
reg dff;
wire clk,din,reset;
always @ (posedge clk)
if (reset) begin
dff <= 0;
end
else
begin
dff <= din;
end
endmodule
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module nested_if(counter, clk, reset, enable, up_en, down_en);
output reg [3:0] counter;
input clk, reset, enable, up_en, down_en;
// If reset is asserted
/* If counter is enable and
up count is asserted */
down count is asserted */
// If counting is disabled
// Redundant code
if (reset == 1'b0) begin
counter <= 4'b0000;
end
else if (enable == 1'b1 && up_en == 1'b1)
begin
counter <= counter + 1'b1;
end
else if (enable == 1'b1 && down_en == 1'b1)
begin
counter <= counter - 1'b1;
end
else
begin
counter <= counter;
end
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module stimulus();
reg [3:0] counter;
reg clk,reset,enable, up_en, down_en;
initial
begin
$monitor ("@%0dns reset=%b enable=%b up=%b down=%b count=%b“, $time,
reset, enable, up_en, down_en,counter);
$display("@%0dns Driving all inputs to know state",$time);c
clk = 0;
reset = 0;
enable = 0;
up_en = 0;
down_en = 0;
#3 reset = 1;
$display("@%0dns De-Asserting reset",$time);
#4 enable = 1;
$display("@%0dns De-Asserting enable",$time);
#4 up_en = 1;
$display("@%0dns Putting counter in up count mode",$time);
#10 up_en = 0;
down_en = 1;
$display("@%0dns Putting counter in down count mode",$time);
#8 $finish;
end
always #1 clk = ~clk;
endmodule 19
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@0ns Driving all inputs to know state
@0ns reset=0 enable=0 up=0 down=0 count=xxxx
@1ns reset=0 enable=0 up=0 down=0 count=0000
@3ns De-Asserting reset
@7ns De-Asserting enable
@11ns Putting counter in up count mode
@21ns Putting counter in down count mode
Simulator Output:
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module parallel_if();
reg [3:0] counter;
wire clk,reset,enable, up_en, down_en;
if (reset == 1'b0)
begin
counter <= 4'b0000;
end
else
begin
if (enable == 1'b1 && up_en == 1'b1) begin
counter <= counter + 1'b1;
end
if (enable == 1'b1 && down_en == 1'b1)
begin
counter <= counter - 1'b1;
end
end
endmodule
//If reset is asserted
up count is mode*/
down count is mode*/
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module Full_Adder_Behavioral_Verilog( input X1, X2, Cin, output S, Cout ); reg[1:0]
temp;
always @(*)
begin
temp = {1'b0,X1} + {1'b0,X2}+{1'b0,Cin};
end
assign S = temp[0];
assign Cout = temp[1];
$monitor(“%g: a=%b; B=%b; Cin=%b; S=%b; Cout=%b”, $time, X1, X2, Cin, S, Cout);
endmodule
module Testbench_Behavioral_adder();
reg A,B,Cin; wire S,Cout; //Verilog code for the structural full adder
Full_Adder_Behavioral_Verilog Behavioral_adder(.X1(A), .X2(B), .Cin(Cin), .S(S), .Cout(Cout) );
Initial
begin
A = 0; B = 0; Cin = 0;
#5; A = 0; B = 0; Cin = 1;
#5; A = 0; B = 1; Cin = 0;
#5; A = 0; B = 1; Cin = 1;
#5; A = 1; B = 0; Cin = 0;
#5; A = 1; B = 0; Cin = 1;
#5; A = 1; B = 1; Cin = 0;
#5; A = 1; B = 1; Cin = 1;
#5; end
endmodule
Stimulator output:
#0: A = 0; B = 0; Cin = 0; S=0; Cout=0
#5: A = 0; B = 0; Cin = 1; S=1; Cout=0
#10: A = 0; B = 1; Cin = 0; S=1; Cout=0
#15: A = 0; B = 1; Cin = 1; S=0; Cout=1
#20: A = 1; B = 0; Cin = 0; S=1; Cout=0
#25: A = 1; B = 0; Cin = 1; S=0; Cout=1
#30: A = 1; B = 1; Cin = 0; S=0; Cout=1
#35: A = 1; B = 1; Cin = 1; S=1; Cout=122
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Multiway Branching:
case Statement
The keywords case, endcase, and default are used in the case statement.
case (expression)
alternative1: statement1;
...
...
default: default_statement;
endcase
Each of statement1, statement2 ,
default_statement can be a single statement or a
block of multiple statements.
If none of the alternatives matches, the default_statement is executed. The
default_statement is optional.
For the first alternative that matches, the corresponding statement or block is executed.
A block of multiple statements must be grouped
by keywords begin and end.
The expression is compared to the alternatives in
the order they are written.
Placing of multiple default statements in one case statement is not allowed.
The case statements can be nested. 23
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//Execute statements based on the ALU control signal
reg [1:0] alu_control;
...
...
case (alu_control)
2'd0 : y = x + z;
2'd1 : y = x - z;
2'd2 : y = x * z;
default : $display("Invalid ALU control signal");
endcase
//Type 3 statements
//Execute statements based on ALU control signal.
if (alu_control == 0)
y = x + z;
y = x - z;
y = x * z;
else
$display("Invalid ALU control signal");
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module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0}) //Switch based on concatenation
of control signals
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule
The case statement can also act like a many-to-one multiplexer.
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output out;
input s1, s0;
reg out;
case ({s1, s0}) //Switch based on concatenation
of control signals
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule
The case statement can also act like a many-to-one multiplexer.
The case statement compares 0, 1, x,
and z values in the expression and the
alternative bit for bit.
If the expression and the alternative are
of unequal bit width, they are zero filled
to match the bit width of the widest of
the expression and the alternative.
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module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;
always @(s1 or s0 or in)
case ({s1, s0}) //Switch based on control signals
2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end
2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end
2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx : begin
out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx; end
2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z : begin
out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
default: $display("Unspecified control signals");
endcase
endmodule
In the demultiplexer, multiple
input signal combinations such as
2'bz0, 2'bz1, 2,bzz, 2'b0z, and 2'b1z
that cause the same block to be
executed are put together with a
comma (,) symbol.
Case Statement with x and z
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casex, casez Keywords
There are two variations of the case statement. They are denoted by keywords, casex and
casez.
• casez treats all z values in the case alternatives or the case expression as don‘t cares.
All bit positions with z can also represented by ? in that position.
• casex treats all x and z values in the case item or the case expression as don‘t cares.
The use of casex and casez allows comparison of only non-x or -z positions in the case
expression and the case alternatives.
encoding Next_state
1xxx 3
x1xx 2
xx1x 1
xxx1 0
Default 0
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reg [3:0] encoding;
integer state;
casex (encoding)
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
default : next_state = 0;
endcase
casez.
encoding Next_state
1xxx 3
x1xx 2
xx1x 1
xxx1 0
Default 0
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Thus, an input
encoding = 4'b10xz would cause next_state = 3 to be executed
encoding = 4'b11zz would cause
encoding = 4‘b0000 would cause
encoding = 4'bxz11 would cause
encoding = 4'b00xz would cause
encoding = 4'b1111 would cause
encoding = 4'bzxxz would cause
reg [3:0] encoding;
integer state;
casex (encoding)
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
endcase
casez.
next_state = 2 to be executed
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reg [3:0] encoding;
integer state;
casez (encoding)
4'b1zzz : next_state = 3;
4'bz1zz : next_state = 2;
4'bzz1z : next_state = 1;
4'bzzzz : next_state = 0;
endcase
casez.
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module case_compare;
reg sel;
initial begin
#1 $display ("n Driving 0");
sel = 0;
sel = 1;
#1 $display ("n Driving x");
sel = 1'bx;
#1 $display ("n Driving z");
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
1'b0 : $display("Normal : Logic 0 on sel");
1'bx : $display("Normal : Logic x on sel");
1'bz : $display("Normal : Logic z on sel");
endcase
Comparing case, casex & casez satements
always @ (sel)
casex (sel)
1'b0 : $display("CASEX : Logic 0 on sel");
1'bx : $display("CASEX : Logic x on sel");
1'bz : $display("CASEX : Logic z on sel");
endcase
always @ (sel)
casez (sel)
1'b0 : $display("CASEZ : Logic 0 on sel");
1'bx : $display("CASEZ : Logic x on sel");
1'bz : $display("CASEZ : Logic z on sel");
endcase
endmodule
SIMULATOR OUTPUT
?
32
Bengaluru-56

reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
33
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Simulator Output
Driving 0
34
Bengaluru-56

reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
35
Bengaluru-56

reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
36
Bengaluru-56

reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
37
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Simulator Output
Driving 0
Normal : Logic 0 on sel
CASEX : Logic 0 on sel
CASEZ : Logic 0 on sel
38
Bengaluru-56

reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
39
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Simulator Output
Driving 0
Driving 1
40
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
41
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
42
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
43
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Simulator Output
Driving 0
Driving 1
44
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
45
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Simulator Output
Driving 0
Driving 1
Driving x
46
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
47
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
48
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
49
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Simulator Output
Driving 0
Driving 1
Driving x
Normal : Logic x on sel
CASEZ : Logic x on sel
50
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
51
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Simulator Output
Driving 0
Driving 1
Driving x
Driving z
52
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
53
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
54
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
55
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Simulator Output
Driving 0
Driving 1
Driving x
Driving z
Normal : Logic z on sel
56
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reg sel;
initial begin
sel = 0;
sel = 1;
sel = 1'bx;
sel = 1'bz;
#1 $finish;
end
always @ (sel)
case (sel)
endcase
always @ (sel)
casex (sel)
endcase
always @ (sel)
casez (sel)
endcase
endmodule
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Simulator Output with timing analysis
Driving 0
Driving 1
Driving x
Driving z
Normal : Logic z on sel
#1
#2
#3
#4
$finish #5 58
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Loops
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59
•There are four types of looping statements in Verilog: while, for, repeat, and forever.
•The syntax of these loops is very similar to the syntax of loops in the C programming
language.
•All looping statements can appear only inside an initial or always block. Loops
may contain delay expressions.
While Loop:
•The keyword while is used to specify this loop.
•The while loop executes until the while expression is not true. If the loop is entered
when the while-expression is not true, the loop is not executed at all.
•Each expression can contain the operators. Any logical expression can be specified with
these operators.
•If multiple statements are to be executed in the loop, they must be grouped typically
using keywords begin and end.

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Example1:
integer count;
initial
begin
count = 0;
while (count < 128)
begin
$display("Count = %d", count);
count = count + 1;
end
end
Example2:
'define TRUE 1'b1';
'define FALSE 1'b0;
reg [15:0] flag;
integer i; //integer to keep count
reg continue;
initial
begin
flag = 16'b 0010_0000_0000_0000;
i = 0;
continue = 'TRUE;
while((i < 16) && continue)
begin
if (flag[i])
begin
$display("Encountered a TRUE bit at element number %d", i);
continue = 'FALSE;
end
i = i + 1;
end
end
//Execute loop till count is 127.
//exit at count 128
//Multiple conditions using
operators.

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For Loop
The keyword for is used to specify this loop. The for loop contains three parts:
• An initial condition
• A check to see if the terminating condition is true
• A procedural assignment to change value of the control variable
integer count;
initial
for ( count=0; count < 128; count = count + 1)
The initialization condition and the incrementing procedural assignment are included
in the for loop and do not need to be specified separately. Thus, the for loop provides
a more compact loop structure than the while loop.
Note, however, that the while loop is more general-purpose than the for loop. The for
loop cannot be used in place of the while loop in all situations.

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Example:
'define MAX_STATES 32
integer state [0: 'MAX_STATES-1];
integer i;
initial
begin
for(i = 0; i < 32; i = i + 2)
state[i] = 0;
for(i = 1; i < 32; i = i + 2)
state[i] = 1;
end
//Integer array state with elements 0:31
//initialize all even locations with 0
//initialize all odd locations with 1
for loops are generally used when there is a fixed beginning and end to the loop.
If the loop is simply looping on a certain condition, it is better to use the while loop.

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Repeat Loop
The keyword repeat is used for this loop.
The repeat construct executes the loop a fixed number of times. A repeat construct
cannot be used to loop on a general logical expression. A while loop is used for that
purpose.
A repeat construct must contain a number, which can be a constant, a variable or a signal
value. However, if the number is a variable or signal value, it is evaluated only when the
loop starts and not during the loop execution.
integer count;
initial
begin
count = 0;
repeat(128)
begin
count = count + 1;
end
end
The counter expressed with the repeat loop

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Example:
module data_buffer(data_start, data, clock);
parameter cycles = 8;
input data_start;
input [15:0] data;
input clock;
reg [15:0] buffer [0:7];
integer i;
begin
if(data_start)
begin
i = 0;
repeat(cycles)
begin
@(posedge clock) buffer[i] = data;
i = i + 1;
end
end
end
endmodule
//data start signal is true
//Store data at the posedge of next 8 clock cycles
//waits till next posedge to latch data
Data buffer module example
•After it receives a data_start
signal.
•Reads data for next 8 cycles.

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65
Forever loop
•The keyword forever is used to express this loop.
•The loop does not contain any expression and executes forever until the $finish task is
encountered. The loop is equivalent to a while loop with an expression that always
evaluates to true, e.g., while (1).
•A forever loop can be exited by use of the disable statement.
•A forever loop is typically used in conjunction with timing control constructs.
•If timing control constructs are not used, the Verilog simulator would execute this
statement infinitely without advancing simulation time and the rest of the design would
never be executed.

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Example 1: Clock generation
//Use forever loop instead of always block
reg clock;
initial
begin
clock = 1'b0;
forever #10 clock = ~clock; //Clock with period of 20 units
end
Example 2: Synchronize two register values at every positive edge of clock
reg clock;
reg x, y;
initial
forever @(posedge clock) x = y

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Sequential and Parallel Blocks:
Block statements are used to group multiple statements to act together as one.
In previous examples, we used keywords begin and end to group multiple statements.
Thus, we used sequential blocks where the statements in the block execute one after
another.
In this section we discuss the block types: sequential blocks and parallel blocks.
Block Types:
There are two types of blocks: sequential blocks and parallel blocks.
Sequential blocks:
The keywords begin and end are used to group statements into sequential blocks.

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Sequential blocks have the following characteristics:
• The statements in a sequential block are processed in the order they are specified.
A statement is executed only after its preceding statement completes execution
• If delay or event control is specified, it is relative to the simulation time when the
previous statement in the block completed execution,
(except for nonblocking assignments with intra-assignment timing control).
reg x, y;
reg [1:0] z, w;
initial
begin
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
end
//Illustration 1: Sequential block
without delay
//Illustration 2: Sequential blocks with delay.
reg x, y;
reg [1:0] z, w;
initial
begin
x = 1'b0; //completes at simulation time 0
#5 y = 1'b1; //completes at simulation time 5
#10 z = {x, y}; //completes at simulation time 15
#20 w = {y, x}; //completes at simulation time 35
end

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Parallel blocks:
Parallel blocks, specified by keywords fork and join, provide interesting simulation
features.
Parallel blocks have the following characteristics:
• Statements in a parallel block are executed concurrently.
• Ordering of statements is controlled by the delay or event control assigned to each
statement.
• If delay or event control is specified, it is relative to the time the block was entered.
Notice the fundamental difference between sequential and parallel blocks. All
statements in a parallel block start at the time when the block was entered. Thus, the
order in which the statements are written in the block is not important.
reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0;
#5 y = 1'b1;
#10 z = {x, y};
#20 w = {y, x};
join
//Example 1: Parallel blocks with delay.
//completes at simulation time 0

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Generate Blocks:
Generate statements allow Verilog code to be generated dynamically at elaboration time
before the simulation begins.
This facilitates the creation of parameterized models. Generate statements are particularly
convenient when the same operation or module instance is repeated for multiple bits of a
vector, or when certain Verilog code is conditionally included based on parameter
definitions.
Generate statements allow control over the declaration of variables, functions, and tasks,
as well as control over instantiations.
All generate instantiations are coded with a module scope and require the keywords
generate - endgenerate
Generated instantiations can be one or more of the following types:
• Modules
• User defined primitives
• Verilog gate primitives
• Continuous assignments
• initial and always blocks

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Generated declarations and instantiations can be conditionally instantiated into a design.
Generated variable declarations and instantiations can be multiply instantiated into a
design.
Generated instances have unique identifier names and can be referenced
hierarchically.
To support interconnection between structural elements and/or procedural blocks,
generate statements permit the following Verilog data types to be declared within
the generate scope:
• net, reg
• integer, real, time, realtime
• event
Parameter redefinition using ordered or named assignment or a defparam statement can
be declared with the generate scope.
However, a defparam statement within a generate scope is allowed to modify the value
of a parameter only in the same generate scope or within the hierarchy instantiated
within the generate scope.

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72
Task and function declarations are permitted within the generate scope but not within a
generate loop. Generated tasks and functions have unique identifier names and can be
referenced hierarchically.
Connections to generated module instances are handled in the same way as with normal
module instances.
There are three methods to create generate statements:
• Generate loop
• Generate conditional
• Generate case
Generate Loop
A generate loop permits one or more of the following to be
instantiated multiple times using a for loop:
• Variable declarations
• Modules
• User defined primitives, Gate primitives

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Example: Bit-wise Xor of Two N-bit Buses
bitwise_xor (out, i0, i1);
parameter N = 32;
output [N-1:0] out;
input [N-1:0] i0, i1;
genvar j;
//Generate the bit-wise Xor with a single loop
generate for (j=0; j<N; j=j+1) begin: xor_loop
xor g1 (out[j], i0[j], i1[j]);
end //end of the for loop inside the generate block
endgenerate //end of the generate block
// As an alternate style, the xor gates could be replaced by always blocks.
//reg [N-1:0] out;
//generate for (j=0; j<N; j=j+1) begin: bit
//always @(i0[j] or i1[j]) out[j] = i0[j] ^ i1[j];
//end
//endgenerate
endmodule
// Port declarations
// 32-bit bus by default
// Declare a temporary loop variable. This variable is used only in the
evaluation of generate blocks. This variable does not exist during the
simulation of a Verilog design

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Prior to the beginning of the simulation, the simulator elaborates (unrolls) the
code in the generate blocks to create a flat representation without the generate
blocks.
The unrolled code is then simulated. Thus, generate blocks are simply a convenient way of
replacing multiple repetitive Verilog statements with a single statement inside a loop.
• genvar is a keyword used to declare variables that are used only in the evaluation
of generate block. genvars do not exist during simulation of the design.
• The value of a genvar can be defined only by a generate loop.
• Generate loops can be nested. However, two generate loops using the same
genvar as an index variable cannot be nested.
• The name xor_loop assigned to the generate loop is used for hierarchical name
referencing of the variables inside the generate loop. Therefore, the relative
hierarchical names of the xor gates will be xor_loop[0].g1, xor_loop[1].g1, .......,
xor_loop[31].g1

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Generated Ripple Adder
module ripple_adder(co, sum, a0, a1, ci);
parameter N = 4; // 4-bit bus by default
output [N-1:0] sum;
output co;
input [N-1:0] a0, a1;
input ci;
wire [N-1:0] carry;
assign carry[0] = ci;
genvar i;
//Generate the bit-wise Xor with a single loop
generate for (i=0; i<N; i=i+1) begin: r_loop
wire t1, t2, t3;
xor g1 (t1, a0[i], a1[i]);
xor g2 (sum[i], t1, carry[i]);
and g3 (t2, a0[i], a1[i]);
and g4 (t3, t1, carry[i]);
or g5 (carry[i+1], t2, t3);
end //end of the for loop inside the generate block
//Local wire declaration
//Assign 0th bit of carry equal to carry input

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// For the above generate loop, the following relative hierarchical instance names are
generated
// xor : r_loop[0].g1, r_loop[1].g1, r_loop[2].g1, r_loop[3].g1
r_loop[0].g2, r_loop[1].g2, r_loop[2].g2, r_loop[3].g2
// and : r_loop[0].g3, r_loop[1].g3, r_loop[2].g3, r_loop[3].g3
r_loop[0].g4, r_loop[1].g4, r_loop[2].g4, r_loop[3].g4
// or : r_loop[0].g5, r_loop[1].g5, r_loop[2].g5, r_loop[3].g5
// Generated instances are connected with the following generated nets
// Nets: r_loop[0].t1, r_loop[0].t2, r_loop[0].t3
// r_loop[1].t1, r_loop[1].t2, r_loop[1].t3
assign co = carry[N];
endmodule

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Generate Conditional
A generate conditional is like an if-else-if generate construct that permits the following
Verilog constructs to be conditionally instantiated into another module based on an
expression that is deterministic at the time the design is elaborated:
• Modules
Parametrized Multiplier using Generate Conditional
module multiplier (product, a0, a1);
parameter a0_width = 8; // 8-bit bus by default
parameter a1_width = 8; // 8-bit bus by default
localparam product_width = a0_width + a1_width;
output [product_width -1:0] product;
input [a0_width-1:0] a0;
input [a1_width-1:0] a1;

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// Instantiate the type of multiplier conditionally.
// Depending on the value of the a0_width and a1_width
// parameters at the time of instantiation, the appropriate
// multiplier will be instantiated.
Generate
if (a0_width <8) || (a1_width < 8)
cla_multiplier #(a0_width, a1_width) m0 (product, a0, a1);
else
tree_multiplier #(a0_width, a1_width) m0 (product, a0, a1);
endmodule
Generate Case:
A generate case permits the following Verilog constructs to be conditionally instantiated
into another module based on a select-one-of-many case construct that is deterministic at
the time the design is elaborated:
• Modules

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Generate Case Example
module adder(co, sum, a0, a1, ci);
parameter N = 4; // 4-bit bus by default
output [N-1:0] sum;
output co;
input [N-1:0] a0, a1;
input ci;
// Instantiate the appropriate adder based on the width of the bus.
// This is based on parameter N that can be redefined at instantiation time.
generate
case (N)
1: adder_1bit adder1(c0, sum, a0, a1, ci); //1-bit implementation
2: adder_2bit adder2(c0, sum, a0, a1, ci); //2-bit implementation
default: adder_cla #(N) adder3(c0, sum, a0, a1, ci);
endcase
endgenerate
endmodule
//Special cases for 1 and 2 bit adders
// Default is N-bit carry look ahead adder
//end of the generate block

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Examples :
4-to-1 Multiplexer
output out;
input s1, s0;
reg out;
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule

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Behavioral 4-bit Counter Description
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0;
else
Q <= Q + 1;
end
endmodule

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The following specifications must be considered:
• The traffic signal for the main highway gets highest priority because cars are
continuously present on the main highway. Thus, the main highway signal
remains green by default.
• Occasionally, cars from the country road arrive at the traffic signal. The traffic
signal for the country road must turn green only long enough to let the cars on the
country road go.
• As soon as there are no cars on the country road, the country road traffic signal
turns yellow and then red and the traffic signal on the main highway turns green
again.
• There is a sensor to detect cars waiting on the country road. The sensor sends a
signal X as input to the controller. X = 1 if there are cars on the country road;
otherwise, X= 0.
• There are delays on transitions from S1 to S2, from S2 to S3, and from S4 to S0.
The delays must be controllable.

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83

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84
Traffic Signal Controller
`define TRUE 1'b1
`define FALSE 1'b0
`define Y2RDELAY 3 //Yellow to red delay
`define R2GDELAY 2 //Red to green delay
module sig_control
(hwy, cntry, X, clock, clear);
output [1:0] hwy, cntry;
reg [1:0] hwy, cntry;
input X;
input clock, clear;
parameter RED = 2'd0,
YELLOW = 2'd1,
GREEN = 2'd2;
//State definition HWY CNTRY
parameter S0 = 3'd0, //GREEN RED
S1 = 3'd1, //YELLOW RED
S2 = 3'd2, //RED RED
S3 = 3'd3, //RED GREEN
S4 = 3'd4; //RED YELLOW
//Delays
//I/O ports

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//Internal state variables
reg [2:0] state;
reg [2:0] next_state;
//state changes only at positive edge of clock
if (clear)
state <= S0; //Controller starts in S0 state
else
state <= next_state; //State change
//Compute values of main signal and country signal
always @(state)
begin
hwy = GREEN; //Default Light Assignment for Highway light
cntry = RED; //Default Light Assignment for Country light
case(state)
S0: ; // No change, use default
S1: hwy = YELLOW;
S2: hwy = RED;
S3: begin
hwy = RED;
cntry = GREEN;
end

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S4: begin
hwy = RED;
cntry = `YELLOW;
end
endcase
end
//State machine using case statements
always @(state or X)
begin
case (state)
S0: if(X)
next_state = S1;
else
next_state = S0;
S1: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = S2;
end
repeat(`R2GDELAY) @(posedge clock);
next_state = S3;
end

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S3: if(X)
next_state = S3;
else
next_state = S4;
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = S0;
end
default: next_state = S0;
endcase
end
endmodule

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Stimulus for Traffic Signal Controller
//Stimulus Module
module stimulus;
wire [1:0] MAIN_SIG, CNTRY_SIG;
reg CAR_ON_CNTRY_RD;
//if TRUE, indicates that there is car on
//the country road
reg CLOCK, CLEAR;
//Instantiate signal controller
sig_control SC(MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);
//Set up monitor
initial
$monitor($time, " Main Sig = %b Country Sig = %b Car_on_cntry = %b",
MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);
//Set up clock
initial
begin
CLOCK = `FALSE;
forever #5 CLOCK = ~CLOCK;
end
//control clear signal
initial

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begin
CLEAR = `TRUE;
repeat (5) @(negedge CLOCK);
CLEAR = `FALSE;
end
//apply stimulus
initial
begin
CAR_ON_CNTRY_RD = `FALSE;
repeat(20)@(negedge CLOCK); CAR_ON_CNTRY_RD = `TRUE;
repeat(10)@(negedge CLOCK); CAR_ON_CNTRY_RD = `FALSE;
repeat(10)@(negedge CLOCK); $stop;
end
endmodule

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References
• Samir Palnitkar, “Verilog HDL-A Guide to
Digital Design and Synthesis”, Pearson, 2003
• www.asic-world.com/verilog/vbehave3.html

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Prof. Anand H. D.
M. Tech. (PhD.)
Assistant Professor,
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology, Bengaluru-56
Email: anandhdece@dr-ait.org
Phone: 9844518832

Concepts of Behavioral modelling in Verilog HDL

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