INFORMATION

1. Chapter 3
A Top-Level View of Computer
Function and Interconnection
1

2. Bus Interconnections
2
2

3. Computer
Modules
3

4. The interconnection structure must support the
following types of transfers:
Memory to
processor
Processor
reads an
instruction or
a unit of data
from memory
Processor to
memory
Processor
writes a
unit of
data to
memory
4

5. The interconnection structure must support the
following types of transfers:
I/O to
processor
Processor
reads data
from an I/O
device via
an I/O
module
Processor to
I/O
Processor
sends data
to the I/O
device
5

6. The interconnection structure must support the
following types of transfers:
I/O to or from memory
An I/O module is allowed to
exchange data directly with
memory without going
through the processor
using direct memory
access
6

7. A communication pathway
connecting two or more
devices
• Key characteristic is that it is
a shared transmission
medium
Signals transmitted by any
one device are available for
reception by all other
devices attached to the bus
• If two devices transmit during the
same time period their signals
will overlap and become garbled
Typically consists of multiple
communication lines
• Each line is capable of
transmitting signals representing
binary 1 and binary 0
Computer systems contain
a number of different buses
that provide pathways
between components at
various levels of the
computer system hierarchy
Bus characteristics
7

8. System bus
• A bus that connects major
computer components
(processor, memory, I/O)
The most common
computer
interconnection
structures are based on
the use of one or more
system buses
Bus characteristics 8

9. Data Bus
 Data lines that provide a path for moving data among system
modules
 May consist of 32, 64, 128, or more separate lines
 The number of lines is referred to as the width of the data bus
 The number of lines determines how many bits can be
transferred at a time
 The width of the data bus
is a key factor in
determining overall
system performance
9

10. Address Bus
 Used to designate the source or destination of the
data on the data bus
 If the processor wishes to read a word of data
from memory it puts the address of the desired
word on the address lines
 Width determines the maximum possible memory
capacity of the system
 Also used to address I/O ports
 The higher order bits are used to select a
particular module on the bus and the lower order
bits select a memory location or I/O port within the
module
10

11. Control Bus
 Used to control the access and the use of the data
lines and address lines
 Because the data and address lines are shared by all
components
 there must be a means of controlling their use
 Control signals transmit both command and timing
information among system modules
 Timing signals indicate the validity of data and
validity of address information
 Command signals specify operations to be
performed
11

12. Bus Interconnection Scheme
12

13. Bus Configuration
If a great number of devices are connected to the bus,
performance will suffer.
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14. +
Bus Configuration
There are two main causes:
1. In general, the more devices attached to the bus, the
greater the bus length
hence the greater the propagation delay.
2. The bus may become a bottleneck as the
aggregate data transfer demand approaches the
capacity of the bus.
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15. +
Bus Configuration
So:
This problem can be countered to some extent by
increasing the data rate that the bus can carry and
using wider buses (e.g., increasing the data bus from 32
to 64 bits).
 However, because the data rates generated by attached
devices (e.g., graphics and video controllers, network
interfaces) are growing rapidly,
 this is a race that a single bus is ultimately designed to
lose.
15

16. Bus Configuration
Accordingly, most bus-based computer systems
use multiple buses, generally laid out in a
hierarchy.
A typical traditional structure is shown in Figure
3.17a.
This traditional bus architecture is reasonably
efficient but begins to break down as higher and
higher performance is seen in the I/O devices.
16

17. 17

18. In response to these growing demands, a common
approach taken by industry is to build a high-
speed bus that is closely integrated with the rest of
the system, requiring only a bridge between the
processor’s bus and the high-speed bus.
This arrangement is sometimes known as a
mezzanine architecture.
Figure 3.17b shows a typical realization of this
approach.
Bus Configuration
18

19. The advantage of this arrangement is that
the high-speed bus brings high demand devices
into closer integration with the processor and at
the same time is independent of the processor.
Thus, differences in processor and high-speed
bus speeds and signal line definitions are
tolerated.
Changes in processor architecture do not affect
the high-speed bus, and vice versa.
Bus Configuration
19

20. 20

21. Elements of Bus Design
21

22. Bus Types
Bus lines can be separated into two generic
types:
dedicated and multiplexed.
22

23. Bus Types
A dedicated bus line
is permanently assigned either to one function or
to a physical subset of computer components.
Two types of dedications
functional dedication
Physical dedication
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24. +
Bus Types
functional dedication
Like using a separate dedicated address and data lines,
which is common on many buses.
Physical dedication
refers to the use of multiple buses, each of which
connects only a subset of modules.
The potential advantage of physical dedication is
high throughput, because there is less bus contention.
A disadvantage is
 the increased size and cost of the system.
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25. Bus Types
Multiplixing
 The method of using the same lines for multiple purposes.
 The advantage of time multiplexing is
 the use of fewer lines, which saves space and, usually,
cost.
 The disadvantage is
 that more complex circuitry is needed within each
module.
 there is a potential reduction in performance because
certain events that share the same lines cannot take place
in parallel.
25

26. Methods of Arbitration
Because only one unit at a time can successfully
transmit over the bus, some method of
arbitration is needed.
The various methods can be roughly classified as
being either centralized arbitration or
distributed arbitration.
26

27. Methods of Arbitration
In a centralized scheme,
 a single hardware device, referred to as a bus controller
or arbiter, is responsible for allocating time on the bus.
 The device may be a separate module or part of the
processor.
In a distributed scheme
 there is no central controller.
 each module contains access control logic and the
modules act together to share the bus.
27

28. Methods of Arbitration
With both methods of arbitration, the purpose is to
 designate one device, either the processor or an I/O
module, as master.
 The master may then initiate a data transfer (e.g., read or
write) with some other device, which acts as slave for this
particular exchange.
28

29. Timing
Timing refers to
 the way in which events are coordinated on the bus.
 Buses use either synchronous timing or asynchronous
timing.
29

30. Timing
Synchronous timing is
simpler to implement and test.
Because all devices on a synchronous bus are tied to a
fixed clock rate,
the system cannot take advantage of advances in device
performance.
it is less flexible than asynchronous timing.
Asynchronous timing,
a mixture of slow and fast devices, using older and
newer technology, can share a bus.
30

31. 31

32. Timing of Asynchronous Bus Operations
32

33. 33

34. 34

35. The shared bus architecture was the
standard approach to interconnection
between the processor and other
components (memory, I/O, and so on) for
decades.
But contemporary systems increasingly
rely on point-to-point interconnection
rather than shared buses.
Point-to-Point Interconnect
35

36. Point-to-Point Interconnect
Principal reason for change
was the electrical constraints
encountered with increasing
the frequency of wide
synchronous buses
At higher and higher data rates
it becomes increasingly difficult
to perform the synchronization
and arbitration functions in a
timely fashion
A conventional shared bus on the
same chip magnified the
difficulties of increasing bus data
rate and reducing bus latency to
keep up with the processors
So, point to point
interconnection : Has lower
latency, higher data rate, and
better scalability
36

37. +
As an example of the Point-to-
Point interconnect approach
 we would discuss QuickPath
Interconnect (QPI),
which was introduced by Intel in
2008.
37
Point-to-Point Interconnect

38. +Quick Path Interconnect
 Multiple direct connections
 Direct pairwise connections to other components
eliminating the need for arbitration found in shared
transmission systems
 Layered protocol architecture
 These processor level interconnects use a layered protocol
architecture rather than the simple use of control signals
found in shared bus arrangements
 Packetized data transfer
 Data are sent as a sequence of packets each of which
includes control headers and error control codes
QPI
38

39. Multicore
Configuration
Using
QPI
39

40. +
Peripheral Component Interconnect
(PCI)
 A popular high bandwidth, processor independent bus that can
function as a mezzanine or peripheral bus
 Delivers better system performance for high speed I/O
subsystems
 PCI Express (PCIe)
 Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
 Key requirement is high capacity to support the needs of higher data
rate I/O devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time dependent
data streams
40

41. +
PCIe
Configuration

42. +
Expansion Bus Types
These are some of the common expansion bus types
that have ever been used in computers:
 ISA - Industry Standard Architecture
 EISA - Extended Industry Standard Architecture
 MCA - Micro Channel Architecture
 VESA - Video Electronics Standards Association
 PCI - Peripheral Component Interconnect
 PCMCIA - Personal Computer Memory Card Industry
Association (Also called PC bus)
 AGP - Accelerated Graphics Port
 SCSI - Small Computer Systems Interface.
 USB – Universal Serial Bus.
42

43. + 43

44. + 44

45. +
ISA (Industry Standard Architecture
bus)
45
 Pronounced "eye-suh" and debuting on the IBM PC AT,
ISA was the evolution of the first PC bus in 1981.
 An earlier hardware interface for connecting peripheral
devices in PCs.
 ISA accepted cards for sound, display, hard drives and
other devices.
 Originally called the "AT bus",
 the AT/ISA bus extended the PC bus from 8 to 16 bits.

46. +
PCI - Previous
 ISA - (Parallel)
 For several years, motherboards provided a mix of both 8-
bit and 16-bit ISA slots.
 As PCI became popular,
 motherboards included only 16-bit ISA and PCI,
 by the early 2000s, ISA was being replaced entirely by
the PCI interface.
 EISA - (Parallel)
 EISA slots accepted ISA cards.
 Later abandoned for PCI.
46

47. +
PCI - Previous
AGP - (Parallel)
 The graphics interface between PCI and PCI Express.
 AGP was faster than PCI and freed up a PCI slot.
Micro Channel - (Parallel)
 IBM introduced Micro Channel with its PS/2 line in 1987,
 then later supported ISA and eventually gave up Micro
Channel for PCI.
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48. +
PCI - Previous
Prior to PCI Express and USB, there were seven data
buses used from time to time, as follows:
PCI - (Parallel)
 PCI was popular in all hardware platforms but was superseded
PCI Express (PCIe).
 Transition motherboards may have one PCI slot.
FireWire - (Serial)
 Mostly used for digital camera connections.
 Popularized by Apple, adapters were required to use FireWire o
new Macs.
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49. +
PCI BUS: Current
Today there are two primary data buses in a PC:
PCI Express and USB.
PCI Express - (Serial)
 PCI Express (PCIe) is the current bus interface,
superseding PCI.
 All new desktop PCs and Macs have PCIe slots.
USB - (Serial)
 Permanently or temporarily attach almost anything (flash
drives, hard drives, printers, phones, cameras, etc.).
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50. + 50

51. +
PCI Slots Are Not PCI Express (PCIe)
PCI sockets are not the same as PCIe.
PCIe slots come in different sizes.
51
(Peripheral Component Interconnect)
PCI

52. + Peripheral Component Interconnect Express
(PCIe or PCI-E)
 is a serial expansion bus standard for connecting a
computer to one or more peripheral devices.
 PCIe provides lower latency and higher data transfer
rates than parallel busses such as PCI and PCI-X.
 Every device that's connected to a motherboard with
a PCIe link has its own dedicated point-to-point
connection.
 This means that devices are not competing for bandwidth
 because they are not sharing the same bus.
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53. +
Peripheral Component Interconnect Express
(PCIe or PCI-E)
Peripheral devices that use PCIe for data transfer
include
 graphics adapter cards,
 network interface cards (NICs),
 storage accelerator devices and
 other high-performance peripherals.
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54. +
Peripheral Component Interconnect Express
(PCIe or PCI-E)
With PCIe, data is transferred over two signal
pairs:
 two wires for transmitting and
 two wires for receiving.
Each set of signal pairs is called a "lane,"
Each lane is capable of sending and receiving
eight-bit data packets simultaneously between two
points
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55. +
 PCIe can scale from one to 32 separate lanes;
 it is usually deployed with 1, 4, 8, 12, 16 or 32 lanes.
 The lane count of a PCIe card is a determining
factor in its performance and therefore in its
price.
 For example, an inexpensive PCIe device like a NICs
might only use four lanes (PCIe x4).
 By comparison, a high-performance graphics adapter
that uses 32 lanes (PCIe x32) for top-speed
transmission would be more expensive.
55
(Peripheral Component Interconnect)
PCI

56. +
PCIe bus slots are typically backward
compatible with other PCIe bus slots,
 allowing PCIe links that use fewer lanes to use the
same interface as PCIe links that use more lanes.
 For example, a PCIe x8 card could plug into a
PCIe x16 slot.
PCIe bus slots are not backwards compatible
with connection interfaces for older bus
standards.
56
(Peripheral Component Interconnect)
PCI

57. +
With PCIe, data center managers can take
advantage of
 high-speed networking across server backplanes,
 connect to Gigabit Ethernet,
 Connect to RAID
 Connect to Infiniband networking technologies
outside of the server rack.
 The PCIe bus also interconnects clustered
computers that use HyperTransport.
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(Peripheral Component Interconnect)
PCI

58. +
 For laptops and mobile devices,
 mini PCI-e cards can be used to connect
 wireless adaptors,
 solid state device storage and
 other performance boosters.
 External PCI Express (ePCIe)
 is used to connect the motherboard to an external PCIe
interface.
 In most cases, designers use ePCIe when the computer
requires an unusually high number of PCIe ports.
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(Peripheral Component Interconnect)
PCI

59. +
USB: Universal Serial Bus
is a standard type of connection for many
kinds of devices.
Generally, USB refers to the types of
cables and connectors used to connect
these many types of external devices to
computers.
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USB: Universal Serial Bus
USB ports and cables are used to connect
hardware such a:
 printers,
 scanners,
 keyboards,
 mice,
 flash drives,
 external hard drives,
 joysticks,
 cameras,
 monitors,
 computers of all kinds, including desktops, tablets,
laptops, netbooks, etc.
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USB: Universal Serial Bus
Before USB, many of those devices
would attach to a computer over serial
and parallel ports, and others like PS/2.
Many portable devices use USB
primarily for charging, like:
smartphones,
eBook readers, and
small tablets,.
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USB: Universal Serial Bus
USB Versions
• USB4 2.0:
• Release is pending for USB4 Version 2.0, which
supports 80 Gbps (81,920 Mbps).
• USB4:
• Based on the Thunderbolt 3
specification, USB4 supports 40 Gbps (40,960 Mbps).
• USB 3.2 Gen 2x2:
• Also known as USB 3.2, compliant devices are able to
transfer data at 20 Gbps (20,480 Mbps),
called Superspeed+ USB dual-lane.
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63. +
USB: Universal Serial Bus
USB Versions
• USB 3.2 Gen 2:
• Previously called USB 3.1, compliant devices are able to
transfer data at 10 Gbps (10,240 Mbps),
called Superspeed+.
• USB 3.2 Gen 1:
• Previously called USB 3.0, compliant hardware can
reach a maximum transmission rate of 5 Gbps (5,120
Mbps), called SuperSpeed USB.
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64. +
USB: Universal Serial Bus
USB Versions
• USB 2.0:
• USB 2.0 compliant devices can reach a maximum
transmission rate of 480 Mbps, called High-
Speed USB.
• USB 1.1:
• USB 1.1 devices can reach a maximum transmission
rate of 12 Mbps, called Full Speed USB.
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65. +
USB: Universal Serial Bus
USB Versions
Most USB devices and cables
today
 follow USB 2.0, and
a growing number to USB 3.0.
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66. +
Important
The parts of a USB-connected system,
including
the host (like a computer),
 the cable, and
the device,
can all support different USB standards as long
as they are physically compatible.
However, all parts must support the same
standard if you want it to achieve the
maximum data rate possible.
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67. +
USB Connectors
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69. +
USB Connectors
• USB Type C:
• Often referred to simply as USB-C,
• Only USB 3.1 Type C plugs and receptacles (and thus
cables) exist, but adapters for backward compatibility with
USB 3.0 and 2.0 connectors are available.
• This latest USB connector has finally solved the problem of
which side goes up.
• Its symmetrical design allows it to be inserted in the
receptacle in either fashion,
• so you never have to try again.
• These are being widely adopted on smartphones and other
devices.
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70. +
USB Connectors
• USB Type A:
• Officially called USB Standard-A.
• USB 1.1 Type A, USB 2.0 Type A and USB 3.0
Type A plugs and receptacles are physically
compatible.
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71. +
USB Connectors
• USB Type B:
• Officially called USB Standard-B.
• USB 1.1 Type B and USB 2.0 Type B plugs are
physically compatible with USB 3.0 Type B
receptacles
• USB 3.0 Type B plugs are not compatible with
USB 2.0 Type B or USB 1.1 Type B receptacles.
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72. +
USB Connectors
• A USB Powered-B
• connector is also specified in the USB 3.0
standard.
• This receptacle is physically compatible
with
• USB 1.1 and USB 2.0 Standard-B plugs,
• USB 3.0 Standard-B and
• Powered-B plugs as well.
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73. +
USB Connectors
• USB Micro-A:
• USB 3.0 Micro-A plugs look like two different
rectangular plugs fused together, one slightly
longer than the other.
• USB 3.0 Micro-A plugs are only compatible with
USB 3.0 Micro-AB receptacles.
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74. +
USB Connectors
• USB 2.0 Micro-A plugs
• are very small and rectangular, resembling in
many ways a shrunken USB Type A plug.
• USB Micro-A plugs are physically compatible with
both USB 2.0 and USB 3.0 Micro-AB receptacles.
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75. +
USB Connectors
• USB Micro-B:
• USB 3.0 Micro-B plugs look almost identical to
USB 3.0 Micro-A plugs in that they appear as two
individual, but connected, plugs.
• USB 3.0 Micro-B plugs are compatible with both
USB 3.0 Micro-B receptacles and USB 3.0 Micro-
AB receptacles.
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USB Connectors
• USB 2.0 Micro-B plugs:
• are very small and rectangular, but the two
corners on one of the long sides are
beveled.
• USB Micro-B plugs are physically
compatible with
• USB 2.0 Micro-B and Micro-AB
receptacles,
• USB 3.0 Micro-B and Micro-AB
receptacles.
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77. +
USB Connectors
• USB Mini-A:
• USB Mini-A plugs are only compatible
with USB Mini-AB receptacles.
• There is no USB 3.0 Mini-A connector.
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78. +
USB Connectors
• USB Mini-B:
• USB Mini-B plugs are physically compatible
with both USB 2.0 Mini-B and Mini-AB
receptacles.
• There is no USB 3.0 Mini-B connector
78