The document provides an introduction to CMOS VLSI design, fabrication, and elementary logic design. It discusses how CMOS chips are built using transistors fabricated on a silicon substrate using a lithography process to define layers like doped regions, polysilicon gates, contacts and metal interconnects. It then explains how basic logic gates like inverters and NAND gates are constructed using nMOS and pMOS transistors and how their operation depends on input voltages. Finally, it outlines the main steps in the CMOS fabrication process used to build up the transistor and interconnect structures in multiple layers.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
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Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
2. CMOS VLSI Design
Fabrication and Layout Slide 2
Introduction
Integrated circuits: many transistors on one chip.
– Very Large Scale Integration (VLSI): very many
Metal Oxide Semiconductor (MOS) transistor
– Fast, cheap, low-power transistors
– Complementary: mixture of n- and p-type leads to
less power
Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
3. CMOS VLSI Design
Fabrication and Layout Slide 3
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Si Si
Si
Si Si
Si
Si Si
Si
4. CMOS VLSI Design
Fabrication and Layout Slide 4
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As Si
Si
Si Si
Si
Si Si
Si
B Si
Si
Si Si
Si
Si Si
Si
-
+
+
-
5. CMOS VLSI Design
Fabrication and Layout Slide 5
p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction
p-type n-type
anode cathode
6. CMOS VLSI Design
Fabrication and Layout Slide 6
nMOS Transistor
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
– Even though gate is
no longer made of metal
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
7. CMOS VLSI Design
Fabrication and Layout Slide 7
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
8. CMOS VLSI Design
Fabrication and Layout Slide 8
nMOS Operation
When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
9. CMOS VLSI Design
Fabrication and Layout Slide 9
pMOS Transistor
Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
SiO2
n
Gate
Source Drain
bulk Si
Polysilicon
p+ p+
10. CMOS VLSI Design
Fabrication and Layout Slide 10
Power Supply Voltage
GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
11. CMOS VLSI Design
Fabrication and Layout Slide 11
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
21. CMOS VLSI Design
Fabrication and Layout Slide 21
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
22. CMOS VLSI Design
Fabrication and Layout Slide 22
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
A
B
Y
C
23. CMOS VLSI Design
Fabrication and Layout Slide 23
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
24. CMOS VLSI Design
Fabrication and Layout Slide 24
Inverter Cross-section
Typically use p-type substrate for nMOS transistor
– Requires n-well for body of pMOS transistors
– Several alternatives: SOI, twin-tub, etc.
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
25. CMOS VLSI Design
Fabrication and Layout Slide 25
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND VDD
n+
p+
substrate tap well tap
n+ p+
26. CMOS VLSI Design
Fabrication and Layout Slide 26
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
27. CMOS VLSI Design
Fabrication and Layout Slide 27
Detailed Mask Views
Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
28. CMOS VLSI Design
Fabrication and Layout Slide 28
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
29. CMOS VLSI Design
Fabrication and Layout Slide 29
Oxidation
Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
30. CMOS VLSI Design
Fabrication and Layout Slide 30
Photoresist
Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
p substrate
SiO2
Photoresist
31. CMOS VLSI Design
Fabrication and Layout Slide 31
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO2
Photoresist
32. CMOS VLSI Design
Fabrication and Layout Slide 32
Etch
Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
33. CMOS VLSI Design
Fabrication and Layout Slide 33
Strip Photoresist
Strip off remaining photoresist
– Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
p substrate
SiO2
34. CMOS VLSI Design
Fabrication and Layout Slide 34
n-well
n-well is formed with diffusion or ion implantation
Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
35. CMOS VLSI Design
Fabrication and Layout Slide 35
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
36. CMOS VLSI Design
Fabrication and Layout Slide 36
Polysilicon
Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well
37. CMOS VLSI Design
Fabrication and Layout Slide 37
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
38. CMOS VLSI Design
Fabrication and Layout Slide 38
Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
p substrate
n well
39. CMOS VLSI Design
Fabrication and Layout Slide 39
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substrate
n well
n+ Diffusion
40. CMOS VLSI Design
Fabrication and Layout Slide 40
N-diffusion
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n well
p substrate
n+
n+ n+
41. CMOS VLSI Design
Fabrication and Layout Slide 41
N-diffusion
Strip off oxide to complete patterning step
n well
p substrate
n+
n+ n+
42. CMOS VLSI Design
Fabrication and Layout Slide 42
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substrate
n well
n+
n+ n+
p+
p+
p+
43. CMOS VLSI Design
Fabrication and Layout Slide 43
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Contact
44. CMOS VLSI Design
Fabrication and Layout Slide 44
Metallization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal
45. CMOS VLSI Design
Fabrication and Layout Slide 45
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
– Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
46. CMOS VLSI Design
Fabrication and Layout Slide 46
Simplified Design Rules
Conservative rules to get you started
47. CMOS VLSI Design
Fabrication and Layout Slide 47
Inverter Layout
Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– For 0.6 mm process, W=1.2 mm, L=0.6 mm
48. CMOS VLSI Design
Fabrication and Layout Slide 48
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple chip!