Chiplets in Data Centers
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Facebook presented, "Chiplets in Data Centers," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
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George Grey Welcome Keynote - BUD17-100K1
Session ID: BUD17-100K1
Session Name: George Grey Welcome Keynote - BUD17-100K1
Track: Keynote
★ Session Summary ★
Welcome Keynote
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/bud17/bud17-100k1/
Presentation:
Video: https://www.youtube.com/watch?v=6fWjNCRDxq8
---------------------------------------------------
★ Event Details ★
Linaro Connect Budapest 2017 (BUD17)
6-10 March 2017
Corinthia Hotel, Budapest,
Erzsébet krt. 43-49,
1073 Hungary
---------------------------------------------------
Welcome, keynote, George Grey,linaro
http://www.linaro.org
http://connect.linaro.org
---------------------------------------------------
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Similar to Chiplets in Data Centers
Deep Learning on Everyday Devices
1. Deep learning inference on edge devices has challenges due to low hardware resources but can provide benefits like low latency and privacy.
2. To run neural networks on edge devices efficiently, accuracy must often be sacrificed by reducing input/model size, bit precision, or using less accurate algorithms.
3. Brodmann17 focuses on efficient algorithms to support more AI on any processor while maintaining accuracy for edge device applications with low-power processors.
4. Choosing an inference engine or building your own involves tradeoffs between flexibility, speed to production, and control over the environment.
5. Brodmann17 provides examples of edge applications in IoT, smart cities, and autonomous driving.
George Grey Welcome Keynote - BUD17-100K1
Session ID: BUD17-100K1
Session Name: George Grey Welcome Keynote - BUD17-100K1
Track: Keynote
★ Session Summary ★
Welcome Keynote
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/bud17/bud17-100k1/
Presentation:
Video: https://www.youtube.com/watch?v=6fWjNCRDxq8
---------------------------------------------------
★ Event Details ★
Linaro Connect Budapest 2017 (BUD17)
6-10 March 2017
Corinthia Hotel, Budapest,
Erzsébet krt. 43-49,
1073 Hungary
---------------------------------------------------
Welcome, keynote, George Grey,linaro
http://www.linaro.org
http://connect.linaro.org
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ODSA - Technical Introduction
The document discusses the Open Domain Specific Architecture (ODSA) project, which aims to define an open interface for building complex application-specific integrated circuits (ASICs) from multiple die or "chiplets". This would allow best-of-breed chiplets from different vendors to be combined, reducing development costs compared to monolithic designs. The document provides an overview of domain-specific architectures and chiplets, proposes a reference multi-chiplet architecture and open interface, and outlines next steps to define standards and build a proof-of-concept through collaborative workstreams.
Security issues in FPGA based systems.
This document discusses managing securities in FPGA-based embedded systems. It begins by outlining benefits of FPGAs like better performance and flexibility. It then discusses using FPGAs for cryptographic applications and the need for isolating plaintext from ciphertext. The document presents a system design with separate memory partitions and cores for different domains. It provides examples of FPGA usage for aviation and surveillance systems. It also covers security issues like design-tool subversion, composition problems, and protecting bitstreams. Potential solutions discussed include life-cycle management, secure architectures using memory protection and tags, and future work in multi-core systems and dynamic reconfiguration.
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The CHIPS Alliance is a Linux Foundation project that develops open source hardware specifications, implementations, verification tools, and IP blocks. It aims to lower the costs of hardware development through collaboration and shared resources. Members include companies and organizations working on CPUs, interconnects, I/O, machine learning accelerators, and more. The CHIPS Alliance uses Apache 2.0 licensing to encourage IP contribution and participation while allowing commercial use of outputs. It provides a neutral environment for hardware collaboration across companies and countries.
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BlackStor is a cloud native software defined storage solution that is described as the world's fastest and most reliable. It is built using best of breed open source technologies like Linux kernel, ZFS, and DRBD to provide high performance, stability, and scalability. Testing shows DRBD provides significantly higher performance than Ceph with lower CPU usage. BlackStor aims to deliver fully automated, policy-driven storage with features like multi-tenancy, encryption, backup, and deep insights.
SFO15-100K1: Welcome Keynote: George Grey, Linaro CEO
Linaro is a non-profit engineering organization that leads collaboration in the ARM ecosystem. In this presentation, the Linaro CEO summarized the organization's work over the past 5 years and outlined plans for the next year. Key points included the growth of ARM from 1% to over 12 billion chips shipped, the launch of new 96Boards products, ongoing work on ODP and other open source projects, and plans to expand efforts in areas like IoT, embedded systems, and greater collaboration in China. The presentation demonstrated Linaro projects running on 96Boards and concluded by highlighting the scalability of distributed big data workloads on ARM servers.
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The document provides an overview of Sundance Multiprocessor Technology Ltd. and their EM3V - Embedded Vision product. Some key points:
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- The system includes open source software, firmware and documentation and is compatible with popular frameworks like ROS, OpenCV and deep learning stacks for running neural networks.
Leveraging open source for large scale analytics
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Streaming multiprocessors and HPC
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Container Attached Storage (CAS) with OpenEBS - SDC 2018
The document discusses container attached storage (CAS), which aims to provide storage for containers in a container-native way. CAS is designed to run in containers for containers in user space, using the Kubernetes substrate. It addresses challenges like small working sets, ephemeral storage, and cloud lock-in by keeping data local to workloads and allowing per-workload optimization and migration. The document outlines the CAS design and implementation, including using an input/output container to handle storage IO in user space and leveraging technologies like SPDK, virtio, and Kubernetes custom resources.
Pro Tips: When to Choose Private vs Public vs Hybrid Cloud
High Performance Computing (HPC) on Demand*HPC Cloud*Supercomputing*Beowulf Clusters*IT Infrastrucutre*Linux*Open Source -- Will Cottay, Director of Cloud Services for Penguin Computing, presented at the Penguin Computing booth theater during SC18 about what factors to consider before deciding to switch to private, public, or hybrid HPC cloud.
SAMOS 2018: LEGaTO: first steps towards energy-efficient toolset for heteroge...
The LEGaTO project received funding from the European Union's Horizon 2020 programme to create a software stack that optimizes for energy efficiency on heterogeneous computing platforms. The project aims to start with mature European software and optimize it to support energy-efficient computation on hardware with CPUs, GPUs, FPGAs, and FPGA-based dataflow engines. Key partners include universities and companies developing hardware and software. The project will develop programming models, runtime systems, and use cases in areas like healthcare, smart homes, and machine learning to demonstrate the stack.
Gartner Cool Vendor Report 2014
This document provides a summary of the Gartner Cool Vendors in In-Memory Computing Technologies report from 2014. It identifies four vendors as cool vendors: Diablo Technologies, GridGain, MemSQL, and Relex. For each vendor, it provides a brief overview of the company and technology, as well as challenges they may face. It recommends IT leaders consider these vendors' in-memory computing solutions for opportunities like hybrid transaction/analytical processing, big data analytics, and supply chain planning. The report evaluates these vendors' innovations in in-memory technologies and how they can help organizations leverage digital business opportunities through improved agility and fast data processing.
"Using Multi-Master data replication for the parallel-run refactoring", Myros...
It is a story about a brave team who took the decision of taking over the parallel-run pattern among others and afforded to introduce and handle a multi-master system as a temporary step in a refactoring process.
LAS16-109: LAS16-109: The status quo and the future of 96Boards
LAS16-109: The status quo and the future of 96Boards
Speakers: Yang Zhang
Date: September 26, 2016
★ Session Description ★
Community development, Compliance (for members and partners), Reference platform software, product development platform.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-109
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-109/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
LAS16 109 - The status quo and the future of 96Boards
The document discusses the status and future of 96Boards. It provides an overview of existing 96Boards products from various manufacturers. It then discusses plans to improve the 96Boards platform through better documentation, tutorials, standardized software, and new product categories like networking boards. The goal is to make 96Boards easier for developers to use and more widely adopted.
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Google Cloud - Stand Out Features
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ODSA - Business Workstream
The document discusses the formation of a new subgroup within ODSA focused on developing open standards for system-in-package solutions using chiplet technology. The subgroup aims to define an open architectural interface to allow best-of-breed chiplets from multiple vendors to be used together. It outlines several workstreams for participants to join related to developing the interface standards, building proof-of-concept demonstrations, and defining business and intellectual property models. A survey is also discussed that gathers input on drivers and barriers for adopting chiplet and system-in-package technologies as well as supply chain considerations.
ODSA - PoC Planning & Call for Help
The document discusses a Proof of Concept (PoC) project being undertaken by the PoC Working Group of ODSA. It provides an overview of the project leadership and participants. The PoC is finalizing its architecture, which will include identified chiplets and mechanical/connector specifications. It outlines the high level schedule and key tasks through December and calls for help with PCB design, manufacturing sponsorship, and software/firmware volunteers.
ODSA - DirectConnect Options for the PoC
The document discusses Firefly DirectConnect options for an ODSA proof of concept. It describes Firefly's small size and ability to fit 4 modules across a 50mm package edge. Firefly offers high performance through direct connection to the silicon package, eliminating signal distortion through the ball grid array region. It also provides flexibility by supporting both optical and high-speed copper modules in the same slot, and high power efficiency enabling 56G PAM4 transmission at minimal power per bit.
ODSA - PoC Physical Design Elements
The document discusses plans for a proof-of-concept multi-chiplet package. It will include an 8-layer flip chip ball grid array substrate containing chiplets, optical/electrical connectors, and decoupling capacitors. It also proposes an early software development vehicle using equivalent chips on a printed circuit board to speed up software and testing development while hardware is being designed. Developing the package involves tasks like design, simulation, fabrication, assembly, and reporting. The schedule estimates timelines for the various stages including substrate fabrication, assembly, design reviews, and simulations.
ODSA - NXP PoC Presentation
The document describes the NXP Layerscape series of Arm-based system on chip families. It provides details on several SoC models ranging from 1-100GbE networking, PCIe connectivity, memory support, security features, and power consumption between 1-35W. The LX2160 model is highlighted which features a 16-core 64-bit Arm Cortex-A72 CPU, networking up to 100GbE, memory controllers supporting up to 3.2GT/s DDR4, and integrated security accelerators while consuming around 30W.
ODSA - PoC Requirements and Use Cases
The document discusses requirements for a proof-of-concept (POC) involving a smart network interface card (NIC) and computational storage solutions. It proposes using an FPGA, network processor, and CPU module connected via PCIe and Ethernet to demonstrate different POC configurations for the smart NIC and computational storage, including as a standalone device, bump-in-the-wire, and with a data accelerator. The POC aims to validate interfaces and protocols, evaluate performance, and develop software models while exploring challenges of chiplet integration and business aspects of collaboration.
ODSA - Speedster22i FPGA for POC
The document discusses the Speedster22i HD1000 FPGA from Achronix, an older FPGA design that started shipping in 2013. It features 700,000 programmable logic units running up to 750 MHz, along with 40G Ethernet connectivity via three 40G links, PCIe Gen3 x8 support via two controllers, and DDR3 memory via six channels.
ODSA Design Tools for Chiplet-Based Design
The document discusses tools needed for chiplet-based integrated circuit design. It notes that while EDA companies offer many necessary design tools, they are currently offered piecemeal. Standards for defining chiplets electrically, mechanically, and thermally would help enable a chiplet marketplace. zGlue has developed a data exchange format for defining chiplets and their mechanical I/O, and power specifications to allow chiplet vendors to list their products while maintaining access control. The document promotes zGlue's ChipBuilder software and shuttle prototype program for designing with chiplets.
ODSA - Power and Heat
The document discusses power distribution and thermal management challenges for future chiplet-based architectures. It describes the current power architecture for Intel cores that uses a 1.8V input converted to an unregulated 0.9V supply. Future architectures may use local PMICs/chiplets with higher 3.3V or 5V inputs to reduce pins and separate analog and digital power domains, though conversion losses need to be dissipated. An active interposer could provide these conversion functions but poses technology and heat dissipation challenges. Thermal budgeting and local heating effects will require power/thermal controllers using temperature sensors. Chiplet specifications like voltage, current, thermal resistance, and interfaces will need to be standardized.
ODSA - PIPE Adapters
This document discusses the need for PIPE adapters to allow chiplet-based designs to function as a single die. It notes that while several high-speed SerDes exist, none directly support the PIPE interface which was developed by Intel for PCIe. PIPE adapters would be needed to divide the PIPE interface into multiple lanes that could be supported by the SerDes, which generally have higher speeds than individual PCIe lanes. The document outlines how a Kandou PIPE adapter would work and notes that while the complexity is less than the SerDes, PIPE adapters have not yet been developed into products and test chips would be useful to develop the interfaces.
ODSA - PHY Layer
The document discusses proposals for a standard physical layer interface to enable high data rate connections between chiplet products from different sources. Seven interface options are being considered, including AIB, silicon interposer, various parallel and SERDES-based approaches. Metrics for comparing the options are discussed, such as cost, performance, and design/integration complexity. Relative ratings of the options are provided based on initial discussions. Feedback is sought on priority metrics for different target markets.
OODSA - BoW: Basic, Fast, Turbo Die-to Die Open Interface Solutions
The document proposes the Bow interface standard for chiplet-based systems. Bow would define a simple source synchronous interface using CMOS IO to enable communication between dies up to 4Gbps per line untetherminated, or up to 12Gbps per line when terminated. It could also define a bidirectional "Bow Turbo" mode using hybrid circuits to allow simultaneous transmission and reception at up to 2x12Gbps per line. The proposal suggests this standard could improve compatibility for chiplet communication where bandwidth needs are modest, while examples from silicon implementation suggest it could efficiently deliver over 1Tbps of throughput per mm of chip edge. Volunteers are sought to further define options like test approaches and applications to evaluate the standard's value.
ODSA - Samsung Welcomes OCP's ODSA
Samsung Foundry is expanding from mobile chips to high performance computing. The author is personally interested in chiplet technology for several reasons: it could enable larger chip designs by connecting chiplets in multiple dimensions; allow for easier upgrading by swapping out chiplets; lower costs by reusing chiplets across designs; and enable new business models. The author sees a need for innovation in hardware to keep pace with the rapid advancement of software and AI models, and chiplet technology may help address this. Samsung is interested in contributing to the Open Domain Specific Architecture initiative but has not yet determined how.
ODSA - OCP Welcome
The document is an agenda for the OCP ODSA Workshop held on March 28, 2019. It lists the schedule of presentations for the day-long workshop organized by the Open Compute Project (OCP). The workshop included presentations on accelerator technologies, standards and interfaces, design tools, proof of concept requirements and components, as well as discussions on business models and collaboration with OCP. Speakers came from companies like Samsung, Facebook, Netronome, Avera Semi, Kandou, Achronix, NXP and others.
ODSA - OCP Accelerator Module and the Infrastructure
The document discusses the need for an open accelerator infrastructure to support the growing variety of AI hardware accelerators. It proposes the Open Compute Project Accelerator Module specification to standardize the form factor and interfaces of accelerator modules. It also introduces the concept of a Universal Baseboard that can host multiple accelerator modules and uses a standardized interconnect to provide flexible topologies to scale performance for different AI workloads. The open infrastructure is intended to foster innovation while providing interoperability between accelerator modules and systems.
ODSA Sub-Project Launch
The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
ODSA Workshop: Development Effort Summary
NXP presented, "ODSA Workshop: Development Effort Summary," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
ODSA Proof of Concept SmartNIC Speeds & Feeds
The document discusses using a smart NIC as a proof-of-concept for the ODSA. A smart NIC offloads networking tasks from the CPU. It proposes using an FPGA, NIC, and CPU chiplets on an organic substrate with PCIe and Ethernet interfaces. This would provide programmable packet inspection and processing. Storage could connect via a smart NVMe. Alternative designs placing the PHY/MAC in the FPGA or using next-gen chiplets are discussed. The goal is a flexible, high-performance smart NIC prototype.
ODSA Use Case - SmartNIC
TitanIC presented, "ODSA Use Case - SmartNIC," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
ODSA Workshop
Overview of the first ODSA Workshop 2019. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
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OODSA - BoW: Basic, Fast, Turbo Die-to Die Open Interface Solutions
OODSA - BoW: Basic, Fast, Turbo Die-to Die Open Interface Solutions
ODSA - OCP Accelerator Module and the Infrastructure
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Chiplets in Data Centers
- 2. Chiplets in Data Centers Utku Diril
- 3. What is wrong with chips? ● Long development cycle ○ Concept to tape out 18-36 months depending on the complexity ● Expensive ○ ~10M mask cost for high end process ○ High risk → ■ Reduced competition ■ Reduced innovation
- 4. What is wrong with chips? ● Repetitive work ○ Almost all chips have PCIe, DDR interfaces ○ Expensive IP that has to be verified for every chip ● All the IPs including analog/mixed-signal has to be in the same technology node ● Reduced yield as the complexity and area of the chips increase ● Single SOC team responsible for all the IPs to work seamlessly together → Increased resource needs
- 5. Current state of chiplets ● Companies use chiplets to improve yield, reduce cost, improve time to market ● Each company uses their own proprietary chiplet-chiplet interconnect ● Not a collaborative effort among companies
- 6. Potential future for chiplets ● Open and simple interconnect spec ○ Think of AXI/Wishbone for chiplets ● Chiplets for common functionality ○ DDR/HBM controllers/PHYs ○ PCI controllers/PHYs ○ Network interfaces ○ Large SRAM based caches ○ eFPGAs ○ Processors
- 7. Potential future for chiplets ● Complex SOCs can be built with chiplets - not only Smart Nics! ● Accelerators can be built by only changing the compute chiplet ● A promising chiplet can see datacenter deployment in 6-12 months rather than 18-36 months ● More companies can benefit from and contribute to a future with chiplets
- 8. How can we make this work? ● Open versatile spec ○ Covers a wide range of applications ○ Handles low and high BW situations efficiently ● Low barrier to entry ○ Interconnect spec should be open, easy to understand, easy to implement ○ SERDES and other building blocks (FIFOs, arbiters, protocol convertors, ...etc) should be available for free or for a very low cost
- 9. How can we make this work? ● Tools ○ EDA companies invest in chiplet integration, discovery, analysis tools ○ Building a chip out of chiplets should be like putting together lego blocks ● Community ○ Bigger the community, bigger the success will be