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“Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core

This document summarizes the design of AMD's "Zen 3" x86-64 microprocessor core. Some key points: - "Zen 3" is AMD's second generation 7nm CPU core, designed to deliver higher performance than "Zen 2" through a 19% increase in instructions per clock (IPC) enabled by architectural changes and maintaining the same TSMC 7nm process. - Changes from "Zen 2" include larger caches, increased instruction issue widths, faster floating point units, and higher load/store bandwidth. These changes aim to improve performance across desktop, mobile, and server segments. - The core complex now includes 8 cores sharing 32MB of L3 cache, compared to 4 cores

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2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 1 of 32 “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core T. Burd1, W. Li1, J. Pistole1, S. Venkataraman1, M. McCabe1, T. Johnson1, J. Vinh1, T. Yiu1, M. Wasio1, H. Wong1, D. Lieu1, J. White2, B. Munger2, J. Lindner2, J. Olson2, S. Bakke2, J. Sniderman2, C. Henrion3, R. Schreiber2, E. Busta3, B. Johnson3, T. Jackson3, A. Miller3, R. Miller3, M. Pickett3, A. Horiuchi3, J. Dvorak3, S. Balagangadharan4, S. Ammikkallingal4, P. Kumar4 1AMD, Santa Clara, CA, 2 AMD, Boxborough, MA, 3 AMD Fort Collins, CO, 4 AMD Bangalore, India
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 2 of 32 Author Introduction • B.S., M.S., Ph.D. degrees in Electrical Engineering & Computer Science from U.C. Berkeley in 1992, 1994, 2001, respectively • Consultant with multiple startups in Silicon Valley prior to joining AMD, Santa Clara, CA in 2005 • Senior Fellow Design Engineer at AMD – Physical Design Architect for a next-gen Zen CPU core • Authored/co-authored 28 conference and journal publications, the book, Energy Efficient Microprocessor Design, and an inventor on five U.S. patents Tom Burd
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 3 of 32 Outline • Market Segments and Design Goals • Architecture • Core Complex • L3 Cache • Technology • Frequency and Power • Client and Server Products • Performance Measurements • Conclusion
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 4 of 32 “Zen 3” Market Segments AMD RYZEN™ 5000 SERIES MOBILE PROCESSORS 3RD GEN AMD EPYC™ SERVER PROCESSORS AMD RYZEN™ 5000 SERIES DESKTOP PROCESSORS • Single CPU core across laptop, desktop, and server • AMD 2nd Generation TSMC 7nm FinFET CPU • Need to balance performance and power efficiency
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 5 of 32 “Zen 3” Design Goals • “Zen 3”  first “ground-up” re-design of AMD “Zen” family of CPUs • Goal: deliver performance uplift over “Zen 2” – Driven primarily by IPC uplift via new microarchitecture • Same TSMC 7nm FinFET technology as “Zen 2” – Additional design effort to push frequency in same process • Achieved +19%1 IPC (ave.), up to +6% frequency, up to +20%2 perf/watt 1. R5K-003, 2. R5K-007 (See endnotes) AMD chiplet strategy [Naffziger, ISSCC 2020] allows for independent optimization of CPU and non-CPU IP in product deployment​
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 6 of 32 “Zen 3” Architecture 32K I-Cache (8-way) Decode Branch Prediction Op-Cache Op Queue Dispatch Integer Rename Scheduler Scheduler Scheduler Scheduler Scheduler Scheduler Floating Point Rename ALU BR AGU ALU AGU ST ALU ST AGU ALU BR F2I ST MUL MAC ADD MUL MAC ADD F2I ST 32K D-Cache (8-way) 512K L2 (I+D) Cache (8-way) Load/Store Queues Integer Register File Floating Point Register File 6 Macro Ops/Cycle Dispatched 4 Instructions/Cycle 8 Macro Ops/Cycle 3 Loads/Cycle 2 Stores/Cycle Major changes from “Zen 2” • L1 BTB: 5121024 entries • Improved branch pred. bandwidth • Int issue width: 710 • Reorder buffer: 224256 entries • FP issue width: 46 • FMAC latency: 54 cycles • LD/ST bandwidth: 2/13/2 • TLB table walkers: 46 [Evers, Hot Chips 2021]
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 7 of 32 Architectural Performance Uplift "Zen 2" "Zen 3" +19% Geomean of 25 Workloads1 (Fixed 4GHz frequency, 8 cores) “Zen 3” Performance Contributors Cache Prefetching Execution Engine Branch Predictor Micro-op Cache Front End Load/Store “Zen 2” “Zen 3” 1. R5K-003 (See endnotes)
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 8 of 32 “Zen 3” Core Complex (CCX) • Increased 48 cores per CCX • Same max. 4MB of L3 per core • Single CCX per chiplet • 2x L3 cache directly accessible per core
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 9 of 32 “Zen 3” CCX Configs Performance-Desktop/Workstation/Server 8 Cores, 32MB L3 APU 8 Core, 16MB L3 Value 4 Core, 8MB L3 Core Count 8 16 32 64 48 24 TDP 100 200 300 Workstation Server Desktop APU • Multiple CCXs can be placed to create up to 64-core products • “Zen 3” CPU core can span from approx. 15- 320W TDP
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 10 of 32 L3 Cache Design Core Core Core Core Core Core Core Core L3 Cache • New bi-directional ring bus • 32 bytes/cycle in each direction • High bandwidth / low latency • Core/L3 interface: 32 bytes/cycle in each direction • L3 cache supports up to 64 misses per core and 192 misses to memory • Switched HC  HD bitcell – Arrays achieved -14% area, -24% leakage 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 11 of 32 L3 Slice Implementation L X I L 3 G L3S SW0 SW1 RPT 0 RPT 1 S6 L3S SW0 SW1 RPT 0 RPT 1 S4 L3S SW0 SW1 RPT 0 RPT 1 S0 L3S SW0 SW1 RPT 0 RPT 1 S2 L3S SW0 SW1 RPT 0 RPT 1 S7 L3S SW0 SW1 RPT 0 RPT 1 S5 L3S SW0 SW1 RPT 0 RPT 1 S1 L3S SW0 SW1 RPT 0 RPT 1 S3 SW1 RPT1 RPT0 SW0 • Single ring-bus interface physical design (L3S) stepped out 8 times, each with two switches (SW0, SW1), and two repeaters (RPT0, RPT1) • Each slice configured to be a corner or straight connection • Wire count similar to prior 4 slice crossbar of “Zen 2” with ~2000 wires in both vertical and horizontal directions • Wires routes optimized to fly over L3 data macros, avoiding routing channels Clockwise 32B bus Counter-clockwise 32B bus
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 12 of 32 AMD 3D V-Cache Ready • Two columns of TSVs on left/right side of the L3 cache • AMD 3D V-Cache extends L3 Cache capacity by 64MB (3x) • Total inter-die bandwidth: >2 TB/s • All control and routing to the cores is implemented on the base die, so AMD 3D V-Cache can be completely focused on density Please attend Paper 26.4 for more details TSV Columns 32 B/Cycle Bi-Directional Bus
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 13 of 32 Core Functional Units • 512kB private L2 cache (8-way) • 32kB instruction cache (8-way) • 32kB data cache (8-way) • Comprised of ~30 sub-blocks • Chip pervasive logic (CPL) – Clock/test unit
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 14 of 32 Technology “Zen 2” “Zen 3” Tech TSMC N7 Cores/CCX 4 cores, 8 threads 8 cores, 16 threads Area/CCX 31 mm2 68 mm2 L2/core 512kB 512kB L3/CCX 16MB 32MB CPP 57 nm Fin Pitch 30 nm 1x Metal Pitch 57 nm Stdcell Track Library 6 track Cu Metal Layers 13 (3 1x, 6 2x, 2 3x, 2 RDL) Needed to achieve “Zen 3” program goals with same technology as “Zen 2”
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 15 of 32 Frequency Design Goal To drive frequency uplift • Structured logic placement • Judicious cell selection • Wire engineering • Targeted use of low-Vt gates • Sub-blocks (~30) kept small to allow multiple iterations per week High Voltage STA Target Mid Voltage STA Target Low Voltage STA Target (Peak 1T Perf) (APU, Server) (APU, Desktop, Server)
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 16 of 32 Shift in VT Mix to Drive Frequency LowVT LowVTLL MidVT MidVTLL HighVT HighVT LowVT LowVTLL MidVT MidVTLL “Zen 2” “Zen 3” Frequency uplift outweighs increase in leakage power, driving higher perf/watt 27% 12% 37% 11% 13% 36% 9% 31% 12% 12%
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 17 of 32 Measured Silicon Frequency
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 18 of 32 Core Power Breakdown Need Perf. Increase @ ISO Power • IPC increase drives Cac increase • Cac Target: ΔCac/ΔIPC < 1 • Cac Achieved: ~15%/~19% (Cac/IPC) To Drive Cac Reduction • Improved Clock Gating • Multiple power-savings features. • Dedicated Power Team
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 19 of 32 Measured Core Power Efficiency
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 20 of 32 Simultaneous Tape-outs Base IPs 32MB L3 (w/ TSVs) 16MB L3 (no TSVs) “Zen 3” Core CCX IPs 8 Cores + 32MB L3 8 Cores + 16MB L3 Dies Desktop/ Server Chiplet (CCD) Monolithic APU
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 21 of 32 CPU Compute Die (CCD) Chiplet System management unit (SMU) • Microcontroller • Power management • Clocks and reset • Fuses • Thermal monitor and control Infinity Fabric1 On-Package (IFOP) links • 1.6 GT/s (10 bits at 1.6Ghz) • 39 RX lanes (2 clock lanes, 1 clock gating lane) • 31 TX lanes (1 clock gating lane) • 4 lanes for control traffic (2 clock lanes) 81 mm2 4.15B Transistors (7nm) 1. AMD’s commercially available Infinity Fabric™ Technology
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 22 of 32 CCD Support for AMD 3D V-Cache • TSVs are integrated into a single CCD design • One CCD design saves NRE cost on mask set and die qualification Impact on PPA: • Area: ~ +4% (of CCD) • Power: negligible • Timing: negligible • Latency: none Can add AMD 3D V-Cache to create new products for workloads that benefit from the additional cache.​
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 23 of 32 1 CCD  Multiple Server Products Server IO Die (12nm) 8.4B Transistors, 416 mm2 2-8 CCDs 3rd Gen AMD EPYCTM Market Segments CCDs Cores Total L3 Cloud / Max-Throughput Compute 8 64 256 MB High-Performance Compute 8 32 256 MB High-Frequency / Large Memory Compute 4-8 8-24 128-256 MB Value / Max IO Compute 2-4 16-32 64-128 MB 4x DDR 4x DDR 4 x16 PCIe/IFIP 4 x16 PCIe/IFIP IFOP IFOP IFOP IFOP
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 24 of 32 1 CCD  Multiple Client Products Client IO Die (12nm) 2.1B Transistors, 125 mm2 1-2 CCDs 4th Gen AMD RyzenTM Processor Market Segments CCDs Cores Total L3 Max Compute 2 16 64 MB Best-Balanced Compute 2 12 64 MB Mainstream / Value Compute 1 6-8 32 MB 2x DDR PCIe IFOP
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 25 of 32 APU Monolithic Chip Key chip features • 8 core, 16MB L3 CCX • 8 compute-unit (“Vega”) graphics • 2 memory controllers – DDR4 up to 3200 MT/s – LPDDR4x up to 4266 MT/s • Multimedia (MM) engines – 2nd Gen Video Codec1, 3rd Gen Audio ACP • 2nd Gen display controller (DC) • I/O controllers – PCIE® Gen4, USB-C, USB-3.1, USB-2.0, NVMe SATA • System management unit (SMU) • Fusion controller hub (FCH) 180 mm2 10.7B Transistors (7nm) 8 Core 16 MB L3 CCX “Vega” Graphics DDR4 / LPDDR4x USB PCIe MM DC I/O SMU MM SMU 1. GD-176 (See endnotes) FCH DCE
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 26 of 32 Per Core On-Chip Power Regulation Each CPU core has a digital low drop-out (DLDO) regulator AMD Ryzen™ 4000 Series (“Zen 2”) – All CPU VCORE tied 1:1 with VGFX regardless of load AMD Ryzen™ 5000 Series (“Zen 3”) – Fine-grained power management to run each core at its optimal frequency AND voltage – Maximizes the performance efficiency when running heterogenous workloads – Projected to provide up to 18% increase in SOC battery life1 CPU 0: 1.6GHz 1.1V CPU 2: 2.4GHz 1.1V CPU 4: 2.4GHz 1.1V CPU 6: 2.4GHz 1.1V CPU 1: 2.4GHz 1.1V CPU 3: 3.9GHz 1.1V CPU 5: 1.8GHz 1.1V CPU 7: 1.6GHz 1.1V CPU 0: 1.6GHz, 0.6V CPU 2: 2.4GHz, 0.8V CPU 4: 2.4GHz, 0.8V CPU 6: 2.4GHz, 0.8V Graphics: 2 GHz, 1.1V CPU 1: 2.4GHz, 0.8V CPU 3: 3.9GHz, 0.9V CPU 5: 1.8GHz, 0.7V CPU 7: 1.6GHz, 0.6V Graphics: 2 GHz, 1.1V Ryzen4000SeriesMobile Ryzen5000SeriesMobile 1. CZM-31 (See endnotes)
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 27 of 32 Server Performance Benchmark Config “Zen 2” “Zen 3” Uplift SPECint®2017 64 Cores [7763 vs. 7H12]1 717 854 +19% 32 Cores [75F3 vs. 7532]2 444 596 +34% SPECfp®2017 64 Cores [7763 vs. 7H12]3 543 651 +20% 32 Cores [75F3 vs. 7532]2 434 546 +26% SPECjbb®2017 64 Cores[7763 vs. 7H12]4 249k 314k +26% 1. MLN-088B, 2. MLN-120A, 3. MLN-086B, 4. MLN-092B, 5. MLN-061A (See endnotes) 0 100 200 300 400 500 600 700 800 900 2018 2019 2020 2021 SPECint®2017_int_base Score SPECint®2017 Improvement by Year 1,5 “Zen” “Zen 2” “Zen 2” “Zen 3” 7601 (32 Cores) 7742 (64 Cores) 7H12 (64 Cores) 7763 (64 Cores) 282 701 717 854
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 28 of 32 Client Performance Benchmark Segment “Zen 2” “Zen 3” Uplift Cinebench R20 Desktop [5950X vs. 3900XT]1,5 546 (4.7 GHz) 640 (4.9 GHz) +17% Mobile [5800U vs. 5600U]2 474 (4.4Ghz) 551 (4.6 GHz) +16% Benchmark Config “Zen 2” “Zen 3” Uplift Cinebench R20 8 Cores [5800U vs. 4800U]2 3218 3655 +14% PCMark 10 8 Cores [5800U vs. 4800U]3 5081 6074 +20% PCMark Apps 8 Cores [5800U vs. 4800U]3 8663 10663 +23% Single- Thread Multi- Thread 1. R5K-004, 2. CZM-48, 3. CZM-38, 4. R5K-009, 5. R5K-025 (See endnotes) Benchmark Game Config Uplift CS:GOTM (DirectX® 9) 12 Cores [3900XT vs. 5900X]4 +46% PUBGTM (DirectX® 11) +33% DOTATM (Vulkan®) +24% F1TM 2019 (DirectX® 12) +24% BattlefieldTM V (DirectX® 12) +5% Benchmark Game Config Uplift League of LegendsTM (DirectX® 11) 12 Cores [3900XT vs. 5900X]4 +50% Shadow of the Tomb RaiderTM (DirectX® 12) +28% Far CryTM New Dawn (DirectX® 11) +22% Ashes of the SingularityTM (Vulkan®) +19% Total WarTM : Three Kingdoms (DirectX® 11) +6% Major Gaming Uplifts with “Zen 3”: +26% on average
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 29 of 32 Conclusion • “Zen 3” first major redesign of the AMD “Zen” microarchitecture • Scales from approx. 15W mobile to 320W server • Delivers +19%1 average IPC (vs. “Zen 2”) • Delivers up to +6% frequency (vs. “Zen 2”) • Improves power efficiency up to +20%2 (vs. “Zen 2”) • Achieves max frequency up to 4.9GHz3 1. R5K-003, 2. GD-150, 3. R5K-007 (See endnotes)
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 30 of 32 Acknowledgements • We would like to thank our talented AMD design team across Austin, Bangalore, Boston, Fort Collins, and Santa Clara who contributed to “Zen 3” • Come check out our demo, 2.7, in Demo Session #2 (on Wed) • Attend paper 26.4 for more details on the new AMD 3D V-Cache technology
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 31 of 32 End Notes CZM-31: Testing by AMD Performance Labs as of 12/08/2020 using an AMD Ryzen 7 5800U processor on an AMD Reference Platform configured with a 53WHr battery, WLAN enabled and Bluetooth off, using 1080p video playback (result: up to 21.4 hours) and the MobileMark 2018 benchmark test (result: up to 17.5 hours). CZM-38: Testing by AMD Performance Labs as of 12/30/2020 using PCMark 10, PCMark Apps (APP Performance Overall), Word, Excel, PowerPoint, Edge to measure the productivity performance of a Ryzen 7 4800U vs. Core i7-1165G7; a Ryzen 7 5800U vs. Core i7-1165G7 and 4800U; a Ryzen 5 5600U vs Core i5-113G57; and a Ryzen 3 5400U vs. Core i3-1115G4. Results may vary. PC Mark is a registered trademark of Futuremark Corporation. CZM-48: Testing by AMD engineering using the Cinebench R20 nT benchmark, measuring multithreaded performance of a Ryzen 7 5800U processor engineering sample vs Ryzen 7 4800U, Ryzen 7 5700U processor engineering sample vs Ryzen 7 4700U, Ryzen 5 5600U processor engineering sample vs Ryzen 5 4600U, Ryzen 5 5500U processor engineering sample vs Ryzen 5 4500U, Ryzen 3 5400U processor engineering sample vs Ryzen 3 4300U. Performance may vary. GD-150: Max boost for AMD Ryzen processors is the maximum frequency achievable by a single core on the processor running a bursty single-threaded workload. Max boost will vary based on several factors, including, but not limited to: thermal paste; system cooling; motherboard design and BIOS; the latest AMD chipset driver; and the latest OS updates. GD-176: Video codec acceleration (including at least the HEVC (H.265), H.264, VP9, and AV1 codecs) is subject to and not operable without inclusion/installation of compatible media players. MLN-061A: As of 03/16/2021, the Intel log trendline from top SPECrate®2017_int_base published scores to date for 2P 1st and 2nd Gen Intel based Xeon SP (LGA socketed) servers for each of 2017, 2018, 2019, 2020, and 2021. The AMD log trendline from top SPECrate®2017_int_base published score to date, for 2P Intel based AMD EPYC servers for each of 2017, 2018, 2019, 2020, and 2021. MLN-086B: SPECrate®2017_fp_base comparison based on best performing systems published at www.spec.org as of 07/06/2021. Configurations: 2x AMD EPYC 7763 (651 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q1/cpu2017- 20210219-24944.html, $15780 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8380 (489 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210521-26361.html, $16198 1Ku price total, 540W total TDP) for 1.33x the performance at 1.37x the score per total CPU $; 0.83x the performance/Core; 1.28x the performance/Watt. Top EPYC 7002 Series result: 2x AMD EPYC 7H12 (543 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2020q3/cpu2017- 20200707-23397.html). AMD 1Ku pricing and Intel ARK.intel.com specifications and pricing as of 4/6/21. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation. see www.spec.org for more information. MLN-088B: SPECrate®2017_int_base comparison based on best performing systems published at www.spec.org as of 07/06/2021. Configurations: 2x AMD EPYC 7763 (854 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q3/cpu2017- 20210622-27664.html, $15780 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8380 (602 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210521-26364.html, $16198 1Ku price total, 540W total TDP) for 1.42x the performance at 1.46x the score per total CPU $; 0.89x the performance/Core; 1.37x the performance/Watt. AMD 1Ku pricing and Intel ARK.intel.com specifications and pricing as of 4/6/21. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation. see www.spec.org for more information. MLN-092B: SPECjbb® 2015-MultiJVM Critical comparison based on best performing 2P systems published at www.spec.org as of 10/26/2021, 2x AMD EPYC™ 7763 scored 313,824 SPECjbb® 2015-MultiJVM Critical-jOPS (339,338 max-jOPS, https://www.spec.org/jbb2015/results/res2021q3/jbb2015-20210701-00688.html ) which has 47% higher critical server-side Java® operations than the top “Ice Lake” 2x Intel® Xeon® Platinum 8380 that scored 213,195 critical-jOPS (269,094 max-jOPS, https://www.spec.org/jbb2015/results/res2021q3/jbb2015-20210810-00701.html ). 2x AMD EPYC 7H12 scored 248,942 critical-jOPS (315,663 max-jOPS, http://spec.org/jbb2015/results/res2020q2/jbb2015-20200423-00550.html ). SPEC® and SPECjbb® are registered trademarks of the Standard Performance Evaluation Corporation. See www.spec.org for more information. MLN-120A: SPECrate®2017_int_base and SPECrate®2017_fp_base comparison based on best performing 32-core processor-based systems published at www.spec.org as of 10/26/2021. Integer Configurations: 2x AMD EPYC 75F3 (596 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210409-25541.html , $9720 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8362 (526 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q3/cpu2017-20210802-28469.html , $10896 1Ku price total, 530W total TDP) for 1.13x the performance at 1.27x the score per total CPU $; 1.13x the performance/Core; 1.07x the performance/Watt. Floating-Point Configurations: 2x AMD EPYC 75F3 (546 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210409-25543.html , $9720 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8362 (465 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q3/cpu2017-20210802-28467.html , $10896 1Ku price total, 530W total TDP) for 1.17x the performance at 1.316x the score per total CPU $; 1.17x the performance/Core; 1.11x the performance/Watt. AMD 1Ku pricing and Intel ARK.intel.com specifications and pricing as of 4/6/21. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation. see www.spec.org for more information. R5K-003: Testing by AMD performance labs as of 09/01/2020. IPC evaluated with a selection of 25 workloads running at a locked 4GHz frequency on 8-core "Zen 2" Ryzen 7 3800XT and "Zen 3" Ryzen 7 5800X desktop processors configured with Windows® 10, NVIDIA GeForce RTX 2080 Ti (451.77), Samsung 860 Pro SSD, and 2x8GB DDR4-3600. Results may vary. R5K-004: Testing by AMD performance labs as of 09/01/2020 with a Ryzen 5950X processor vs a Core i9-10900K configured with NVIDIA GeForce GTX 2080 Ti graphics, Samsung 860 Pro SSD, 2X8 DDR4-3600, Windows 10 and a Noctua NH-D15s cooler. Single-core performance evaluated with Cinebench R20 1T benchmark. Results may vary. R5K-007: Testing by AMD Performance Labs as of 09/01/2020 using Cinebench R20 nT versus system wall power during full load CPU test using a Core i9--10900K, Ryzen 9 3900XT, Ryzen 9 5900X, Ryzen 9 3950X, and a Ryzen 9 5950X configured with: 2x8GB DDR4-3600, GeForce RTX 2080 Ti, Samsung 860 Pro SSD, Noctua NH-D15s cooler, and an open-air test bench with no additional power draw sources. Results may vary. R5K-009: Testing by AMD performance labs as of 09/01/2020 measuring gaming performance of a Ryzen 9 5900X desktop processor vs. a Ryzen 9 3900XT in 11 popular titles at 1920x1080, the High image quality preset, and the newest graphics API available for each title (e.g. DirectX® 12 or Vulkan™ or DirectX® 11). Results may vary. R5K-025: Testing by AMD Performance Labs as of September 23, 2020, using Ryzen(TM) 5000 Series processors: 5600X, 5800X, 5900X, 5950X and 3rd Gen Ryzen(TM) processors: 3600X, 3800XT, 3900XT and 3950X, configured with DDR4-3600C16 and NVIDIA GeForce RTX 2080 Ti, in Cinebench R20 1T. Results may vary.
2.7: “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 32 of 32 Disclaimer The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions, and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities that cannot be completely prevented or mitigated. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. THIS INFORMATION IS PROVIDED ‘AS IS.” AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY RELIANCE, DIRECT, INDIRECT, SPECIAL, OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. © 2022 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, EPYC, Infinity Fabric, Ryzen, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. PCIe is a registered trademark of PCI-SIG.

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“Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core

  • 1.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 1 of 32 “Zen 3”: AMD 2nd Generation 7nm x86-64 Microprocessor Core T. Burd1, W. Li1, J. Pistole1, S. Venkataraman1, M. McCabe1, T. Johnson1, J. Vinh1, T. Yiu1, M. Wasio1, H. Wong1, D. Lieu1, J. White2, B. Munger2, J. Lindner2, J. Olson2, S. Bakke2, J. Sniderman2, C. Henrion3, R. Schreiber2, E. Busta3, B. Johnson3, T. Jackson3, A. Miller3, R. Miller3, M. Pickett3, A. Horiuchi3, J. Dvorak3, S. Balagangadharan4, S. Ammikkallingal4, P. Kumar4 1AMD, Santa Clara, CA, 2 AMD, Boxborough, MA, 3 AMD Fort Collins, CO, 4 AMD Bangalore, India
  • 2.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 2 of 32 Author Introduction • B.S., M.S., Ph.D. degrees in Electrical Engineering & Computer Science from U.C. Berkeley in 1992, 1994, 2001, respectively • Consultant with multiple startups in Silicon Valley prior to joining AMD, Santa Clara, CA in 2005 • Senior Fellow Design Engineer at AMD – Physical Design Architect for a next-gen Zen CPU core • Authored/co-authored 28 conference and journal publications, the book, Energy Efficient Microprocessor Design, and an inventor on five U.S. patents Tom Burd
  • 3.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 3 of 32 Outline • Market Segments and Design Goals • Architecture • Core Complex • L3 Cache • Technology • Frequency and Power • Client and Server Products • Performance Measurements • Conclusion
  • 4.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 4 of 32 “Zen 3” Market Segments AMD RYZEN™ 5000 SERIES MOBILE PROCESSORS 3RD GEN AMD EPYC™ SERVER PROCESSORS AMD RYZEN™ 5000 SERIES DESKTOP PROCESSORS • Single CPU core across laptop, desktop, and server • AMD 2nd Generation TSMC 7nm FinFET CPU • Need to balance performance and power efficiency
  • 5.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 5 of 32 “Zen 3” Design Goals • “Zen 3”  first “ground-up” re-design of AMD “Zen” family of CPUs • Goal: deliver performance uplift over “Zen 2” – Driven primarily by IPC uplift via new microarchitecture • Same TSMC 7nm FinFET technology as “Zen 2” – Additional design effort to push frequency in same process • Achieved +19%1 IPC (ave.), up to +6% frequency, up to +20%2 perf/watt 1. R5K-003, 2. R5K-007 (See endnotes) AMD chiplet strategy [Naffziger, ISSCC 2020] allows for independent optimization of CPU and non-CPU IP in product deployment​
  • 6.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 6 of 32 “Zen 3” Architecture 32K I-Cache (8-way) Decode Branch Prediction Op-Cache Op Queue Dispatch Integer Rename Scheduler Scheduler Scheduler Scheduler Scheduler Scheduler Floating Point Rename ALU BR AGU ALU AGU ST ALU ST AGU ALU BR F2I ST MUL MAC ADD MUL MAC ADD F2I ST 32K D-Cache (8-way) 512K L2 (I+D) Cache (8-way) Load/Store Queues Integer Register File Floating Point Register File 6 Macro Ops/Cycle Dispatched 4 Instructions/Cycle 8 Macro Ops/Cycle 3 Loads/Cycle 2 Stores/Cycle Major changes from “Zen 2” • L1 BTB: 5121024 entries • Improved branch pred. bandwidth • Int issue width: 710 • Reorder buffer: 224256 entries • FP issue width: 46 • FMAC latency: 54 cycles • LD/ST bandwidth: 2/13/2 • TLB table walkers: 46 [Evers, Hot Chips 2021]
  • 7.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 7 of 32 Architectural Performance Uplift "Zen 2" "Zen 3" +19% Geomean of 25 Workloads1 (Fixed 4GHz frequency, 8 cores) “Zen 3” Performance Contributors Cache Prefetching Execution Engine Branch Predictor Micro-op Cache Front End Load/Store “Zen 2” “Zen 3” 1. R5K-003 (See endnotes)
  • 8.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 8 of 32 “Zen 3” Core Complex (CCX) • Increased 48 cores per CCX • Same max. 4MB of L3 per core • Single CCX per chiplet • 2x L3 cache directly accessible per core
  • 9.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 9 of 32 “Zen 3” CCX Configs Performance-Desktop/Workstation/Server 8 Cores, 32MB L3 APU 8 Core, 16MB L3 Value 4 Core, 8MB L3 Core Count 8 16 32 64 48 24 TDP 100 200 300 Workstation Server Desktop APU • Multiple CCXs can be placed to create up to 64-core products • “Zen 3” CPU core can span from approx. 15- 320W TDP
  • 10.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 10 of 32 L3 Cache Design Core Core Core Core Core Core Core Core L3 Cache • New bi-directional ring bus • 32 bytes/cycle in each direction • High bandwidth / low latency • Core/L3 interface: 32 bytes/cycle in each direction • L3 cache supports up to 64 misses per core and 192 misses to memory • Switched HC  HD bitcell – Arrays achieved -14% area, -24% leakage 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle 32B/cycle
  • 11.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 11 of 32 L3 Slice Implementation L X I L 3 G L3S SW0 SW1 RPT 0 RPT 1 S6 L3S SW0 SW1 RPT 0 RPT 1 S4 L3S SW0 SW1 RPT 0 RPT 1 S0 L3S SW0 SW1 RPT 0 RPT 1 S2 L3S SW0 SW1 RPT 0 RPT 1 S7 L3S SW0 SW1 RPT 0 RPT 1 S5 L3S SW0 SW1 RPT 0 RPT 1 S1 L3S SW0 SW1 RPT 0 RPT 1 S3 SW1 RPT1 RPT0 SW0 • Single ring-bus interface physical design (L3S) stepped out 8 times, each with two switches (SW0, SW1), and two repeaters (RPT0, RPT1) • Each slice configured to be a corner or straight connection • Wire count similar to prior 4 slice crossbar of “Zen 2” with ~2000 wires in both vertical and horizontal directions • Wires routes optimized to fly over L3 data macros, avoiding routing channels Clockwise 32B bus Counter-clockwise 32B bus
  • 12.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 12 of 32 AMD 3D V-Cache Ready • Two columns of TSVs on left/right side of the L3 cache • AMD 3D V-Cache extends L3 Cache capacity by 64MB (3x) • Total inter-die bandwidth: >2 TB/s • All control and routing to the cores is implemented on the base die, so AMD 3D V-Cache can be completely focused on density Please attend Paper 26.4 for more details TSV Columns 32 B/Cycle Bi-Directional Bus
  • 13.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 13 of 32 Core Functional Units • 512kB private L2 cache (8-way) • 32kB instruction cache (8-way) • 32kB data cache (8-way) • Comprised of ~30 sub-blocks • Chip pervasive logic (CPL) – Clock/test unit
  • 14.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 14 of 32 Technology “Zen 2” “Zen 3” Tech TSMC N7 Cores/CCX 4 cores, 8 threads 8 cores, 16 threads Area/CCX 31 mm2 68 mm2 L2/core 512kB 512kB L3/CCX 16MB 32MB CPP 57 nm Fin Pitch 30 nm 1x Metal Pitch 57 nm Stdcell Track Library 6 track Cu Metal Layers 13 (3 1x, 6 2x, 2 3x, 2 RDL) Needed to achieve “Zen 3” program goals with same technology as “Zen 2”
  • 15.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 15 of 32 Frequency Design Goal To drive frequency uplift • Structured logic placement • Judicious cell selection • Wire engineering • Targeted use of low-Vt gates • Sub-blocks (~30) kept small to allow multiple iterations per week High Voltage STA Target Mid Voltage STA Target Low Voltage STA Target (Peak 1T Perf) (APU, Server) (APU, Desktop, Server)
  • 16.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 16 of 32 Shift in VT Mix to Drive Frequency LowVT LowVTLL MidVT MidVTLL HighVT HighVT LowVT LowVTLL MidVT MidVTLL “Zen 2” “Zen 3” Frequency uplift outweighs increase in leakage power, driving higher perf/watt 27% 12% 37% 11% 13% 36% 9% 31% 12% 12%
  • 17.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 17 of 32 Measured Silicon Frequency
  • 18.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 18 of 32 Core Power Breakdown Need Perf. Increase @ ISO Power • IPC increase drives Cac increase • Cac Target: ΔCac/ΔIPC < 1 • Cac Achieved: ~15%/~19% (Cac/IPC) To Drive Cac Reduction • Improved Clock Gating • Multiple power-savings features. • Dedicated Power Team
  • 19.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 19 of 32 Measured Core Power Efficiency
  • 20.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 20 of 32 Simultaneous Tape-outs Base IPs 32MB L3 (w/ TSVs) 16MB L3 (no TSVs) “Zen 3” Core CCX IPs 8 Cores + 32MB L3 8 Cores + 16MB L3 Dies Desktop/ Server Chiplet (CCD) Monolithic APU
  • 21.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 21 of 32 CPU Compute Die (CCD) Chiplet System management unit (SMU) • Microcontroller • Power management • Clocks and reset • Fuses • Thermal monitor and control Infinity Fabric1 On-Package (IFOP) links • 1.6 GT/s (10 bits at 1.6Ghz) • 39 RX lanes (2 clock lanes, 1 clock gating lane) • 31 TX lanes (1 clock gating lane) • 4 lanes for control traffic (2 clock lanes) 81 mm2 4.15B Transistors (7nm) 1. AMD’s commercially available Infinity Fabric™ Technology
  • 22.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 22 of 32 CCD Support for AMD 3D V-Cache • TSVs are integrated into a single CCD design • One CCD design saves NRE cost on mask set and die qualification Impact on PPA: • Area: ~ +4% (of CCD) • Power: negligible • Timing: negligible • Latency: none Can add AMD 3D V-Cache to create new products for workloads that benefit from the additional cache.​
  • 23.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 23 of 32 1 CCD  Multiple Server Products Server IO Die (12nm) 8.4B Transistors, 416 mm2 2-8 CCDs 3rd Gen AMD EPYCTM Market Segments CCDs Cores Total L3 Cloud / Max-Throughput Compute 8 64 256 MB High-Performance Compute 8 32 256 MB High-Frequency / Large Memory Compute 4-8 8-24 128-256 MB Value / Max IO Compute 2-4 16-32 64-128 MB 4x DDR 4x DDR 4 x16 PCIe/IFIP 4 x16 PCIe/IFIP IFOP IFOP IFOP IFOP
  • 24.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 24 of 32 1 CCD  Multiple Client Products Client IO Die (12nm) 2.1B Transistors, 125 mm2 1-2 CCDs 4th Gen AMD RyzenTM Processor Market Segments CCDs Cores Total L3 Max Compute 2 16 64 MB Best-Balanced Compute 2 12 64 MB Mainstream / Value Compute 1 6-8 32 MB 2x DDR PCIe IFOP
  • 25.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 25 of 32 APU Monolithic Chip Key chip features • 8 core, 16MB L3 CCX • 8 compute-unit (“Vega”) graphics • 2 memory controllers – DDR4 up to 3200 MT/s – LPDDR4x up to 4266 MT/s • Multimedia (MM) engines – 2nd Gen Video Codec1, 3rd Gen Audio ACP • 2nd Gen display controller (DC) • I/O controllers – PCIE® Gen4, USB-C, USB-3.1, USB-2.0, NVMe SATA • System management unit (SMU) • Fusion controller hub (FCH) 180 mm2 10.7B Transistors (7nm) 8 Core 16 MB L3 CCX “Vega” Graphics DDR4 / LPDDR4x USB PCIe MM DC I/O SMU MM SMU 1. GD-176 (See endnotes) FCH DCE
  • 26.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 26 of 32 Per Core On-Chip Power Regulation Each CPU core has a digital low drop-out (DLDO) regulator AMD Ryzen™ 4000 Series (“Zen 2”) – All CPU VCORE tied 1:1 with VGFX regardless of load AMD Ryzen™ 5000 Series (“Zen 3”) – Fine-grained power management to run each core at its optimal frequency AND voltage – Maximizes the performance efficiency when running heterogenous workloads – Projected to provide up to 18% increase in SOC battery life1 CPU 0: 1.6GHz 1.1V CPU 2: 2.4GHz 1.1V CPU 4: 2.4GHz 1.1V CPU 6: 2.4GHz 1.1V CPU 1: 2.4GHz 1.1V CPU 3: 3.9GHz 1.1V CPU 5: 1.8GHz 1.1V CPU 7: 1.6GHz 1.1V CPU 0: 1.6GHz, 0.6V CPU 2: 2.4GHz, 0.8V CPU 4: 2.4GHz, 0.8V CPU 6: 2.4GHz, 0.8V Graphics: 2 GHz, 1.1V CPU 1: 2.4GHz, 0.8V CPU 3: 3.9GHz, 0.9V CPU 5: 1.8GHz, 0.7V CPU 7: 1.6GHz, 0.6V Graphics: 2 GHz, 1.1V Ryzen4000SeriesMobile Ryzen5000SeriesMobile 1. CZM-31 (See endnotes)
  • 27.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 27 of 32 Server Performance Benchmark Config “Zen 2” “Zen 3” Uplift SPECint®2017 64 Cores [7763 vs. 7H12]1 717 854 +19% 32 Cores [75F3 vs. 7532]2 444 596 +34% SPECfp®2017 64 Cores [7763 vs. 7H12]3 543 651 +20% 32 Cores [75F3 vs. 7532]2 434 546 +26% SPECjbb®2017 64 Cores[7763 vs. 7H12]4 249k 314k +26% 1. MLN-088B, 2. MLN-120A, 3. MLN-086B, 4. MLN-092B, 5. MLN-061A (See endnotes) 0 100 200 300 400 500 600 700 800 900 2018 2019 2020 2021 SPECint®2017_int_base Score SPECint®2017 Improvement by Year 1,5 “Zen” “Zen 2” “Zen 2” “Zen 3” 7601 (32 Cores) 7742 (64 Cores) 7H12 (64 Cores) 7763 (64 Cores) 282 701 717 854
  • 28.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 28 of 32 Client Performance Benchmark Segment “Zen 2” “Zen 3” Uplift Cinebench R20 Desktop [5950X vs. 3900XT]1,5 546 (4.7 GHz) 640 (4.9 GHz) +17% Mobile [5800U vs. 5600U]2 474 (4.4Ghz) 551 (4.6 GHz) +16% Benchmark Config “Zen 2” “Zen 3” Uplift Cinebench R20 8 Cores [5800U vs. 4800U]2 3218 3655 +14% PCMark 10 8 Cores [5800U vs. 4800U]3 5081 6074 +20% PCMark Apps 8 Cores [5800U vs. 4800U]3 8663 10663 +23% Single- Thread Multi- Thread 1. R5K-004, 2. CZM-48, 3. CZM-38, 4. R5K-009, 5. R5K-025 (See endnotes) Benchmark Game Config Uplift CS:GOTM (DirectX® 9) 12 Cores [3900XT vs. 5900X]4 +46% PUBGTM (DirectX® 11) +33% DOTATM (Vulkan®) +24% F1TM 2019 (DirectX® 12) +24% BattlefieldTM V (DirectX® 12) +5% Benchmark Game Config Uplift League of LegendsTM (DirectX® 11) 12 Cores [3900XT vs. 5900X]4 +50% Shadow of the Tomb RaiderTM (DirectX® 12) +28% Far CryTM New Dawn (DirectX® 11) +22% Ashes of the SingularityTM (Vulkan®) +19% Total WarTM : Three Kingdoms (DirectX® 11) +6% Major Gaming Uplifts with “Zen 3”: +26% on average
  • 29.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 29 of 32 Conclusion • “Zen 3” first major redesign of the AMD “Zen” microarchitecture • Scales from approx. 15W mobile to 320W server • Delivers +19%1 average IPC (vs. “Zen 2”) • Delivers up to +6% frequency (vs. “Zen 2”) • Improves power efficiency up to +20%2 (vs. “Zen 2”) • Achieves max frequency up to 4.9GHz3 1. R5K-003, 2. GD-150, 3. R5K-007 (See endnotes)
  • 30.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 30 of 32 Acknowledgements • We would like to thank our talented AMD design team across Austin, Bangalore, Boston, Fort Collins, and Santa Clara who contributed to “Zen 3” • Come check out our demo, 2.7, in Demo Session #2 (on Wed) • Attend paper 26.4 for more details on the new AMD 3D V-Cache technology
  • 31.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 31 of 32 End Notes CZM-31: Testing by AMD Performance Labs as of 12/08/2020 using an AMD Ryzen 7 5800U processor on an AMD Reference Platform configured with a 53WHr battery, WLAN enabled and Bluetooth off, using 1080p video playback (result: up to 21.4 hours) and the MobileMark 2018 benchmark test (result: up to 17.5 hours). CZM-38: Testing by AMD Performance Labs as of 12/30/2020 using PCMark 10, PCMark Apps (APP Performance Overall), Word, Excel, PowerPoint, Edge to measure the productivity performance of a Ryzen 7 4800U vs. Core i7-1165G7; a Ryzen 7 5800U vs. Core i7-1165G7 and 4800U; a Ryzen 5 5600U vs Core i5-113G57; and a Ryzen 3 5400U vs. Core i3-1115G4. Results may vary. PC Mark is a registered trademark of Futuremark Corporation. CZM-48: Testing by AMD engineering using the Cinebench R20 nT benchmark, measuring multithreaded performance of a Ryzen 7 5800U processor engineering sample vs Ryzen 7 4800U, Ryzen 7 5700U processor engineering sample vs Ryzen 7 4700U, Ryzen 5 5600U processor engineering sample vs Ryzen 5 4600U, Ryzen 5 5500U processor engineering sample vs Ryzen 5 4500U, Ryzen 3 5400U processor engineering sample vs Ryzen 3 4300U. Performance may vary. GD-150: Max boost for AMD Ryzen processors is the maximum frequency achievable by a single core on the processor running a bursty single-threaded workload. Max boost will vary based on several factors, including, but not limited to: thermal paste; system cooling; motherboard design and BIOS; the latest AMD chipset driver; and the latest OS updates. GD-176: Video codec acceleration (including at least the HEVC (H.265), H.264, VP9, and AV1 codecs) is subject to and not operable without inclusion/installation of compatible media players. MLN-061A: As of 03/16/2021, the Intel log trendline from top SPECrate®2017_int_base published scores to date for 2P 1st and 2nd Gen Intel based Xeon SP (LGA socketed) servers for each of 2017, 2018, 2019, 2020, and 2021. The AMD log trendline from top SPECrate®2017_int_base published score to date, for 2P Intel based AMD EPYC servers for each of 2017, 2018, 2019, 2020, and 2021. MLN-086B: SPECrate®2017_fp_base comparison based on best performing systems published at www.spec.org as of 07/06/2021. Configurations: 2x AMD EPYC 7763 (651 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q1/cpu2017- 20210219-24944.html, $15780 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8380 (489 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210521-26361.html, $16198 1Ku price total, 540W total TDP) for 1.33x the performance at 1.37x the score per total CPU $; 0.83x the performance/Core; 1.28x the performance/Watt. Top EPYC 7002 Series result: 2x AMD EPYC 7H12 (543 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2020q3/cpu2017- 20200707-23397.html). AMD 1Ku pricing and Intel ARK.intel.com specifications and pricing as of 4/6/21. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation. see www.spec.org for more information. MLN-088B: SPECrate®2017_int_base comparison based on best performing systems published at www.spec.org as of 07/06/2021. Configurations: 2x AMD EPYC 7763 (854 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q3/cpu2017- 20210622-27664.html, $15780 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8380 (602 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210521-26364.html, $16198 1Ku price total, 540W total TDP) for 1.42x the performance at 1.46x the score per total CPU $; 0.89x the performance/Core; 1.37x the performance/Watt. AMD 1Ku pricing and Intel ARK.intel.com specifications and pricing as of 4/6/21. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation. see www.spec.org for more information. MLN-092B: SPECjbb® 2015-MultiJVM Critical comparison based on best performing 2P systems published at www.spec.org as of 10/26/2021, 2x AMD EPYC™ 7763 scored 313,824 SPECjbb® 2015-MultiJVM Critical-jOPS (339,338 max-jOPS, https://www.spec.org/jbb2015/results/res2021q3/jbb2015-20210701-00688.html ) which has 47% higher critical server-side Java® operations than the top “Ice Lake” 2x Intel® Xeon® Platinum 8380 that scored 213,195 critical-jOPS (269,094 max-jOPS, https://www.spec.org/jbb2015/results/res2021q3/jbb2015-20210810-00701.html ). 2x AMD EPYC 7H12 scored 248,942 critical-jOPS (315,663 max-jOPS, http://spec.org/jbb2015/results/res2020q2/jbb2015-20200423-00550.html ). SPEC® and SPECjbb® are registered trademarks of the Standard Performance Evaluation Corporation. See www.spec.org for more information. MLN-120A: SPECrate®2017_int_base and SPECrate®2017_fp_base comparison based on best performing 32-core processor-based systems published at www.spec.org as of 10/26/2021. Integer Configurations: 2x AMD EPYC 75F3 (596 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210409-25541.html , $9720 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8362 (526 SPECrate®2017_int_base, http://spec.org/cpu2017/results/res2021q3/cpu2017-20210802-28469.html , $10896 1Ku price total, 530W total TDP) for 1.13x the performance at 1.27x the score per total CPU $; 1.13x the performance/Core; 1.07x the performance/Watt. Floating-Point Configurations: 2x AMD EPYC 75F3 (546 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q2/cpu2017-20210409-25543.html , $9720 1Ku price total, 560W total TDP) versus 2x Intel Xeon Platinum 8362 (465 SPECrate®2017_fp_base, http://spec.org/cpu2017/results/res2021q3/cpu2017-20210802-28467.html , $10896 1Ku price total, 530W total TDP) for 1.17x the performance at 1.316x the score per total CPU $; 1.17x the performance/Core; 1.11x the performance/Watt. AMD 1Ku pricing and Intel ARK.intel.com specifications and pricing as of 4/6/21. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation. see www.spec.org for more information. R5K-003: Testing by AMD performance labs as of 09/01/2020. IPC evaluated with a selection of 25 workloads running at a locked 4GHz frequency on 8-core "Zen 2" Ryzen 7 3800XT and "Zen 3" Ryzen 7 5800X desktop processors configured with Windows® 10, NVIDIA GeForce RTX 2080 Ti (451.77), Samsung 860 Pro SSD, and 2x8GB DDR4-3600. Results may vary. R5K-004: Testing by AMD performance labs as of 09/01/2020 with a Ryzen 5950X processor vs a Core i9-10900K configured with NVIDIA GeForce GTX 2080 Ti graphics, Samsung 860 Pro SSD, 2X8 DDR4-3600, Windows 10 and a Noctua NH-D15s cooler. Single-core performance evaluated with Cinebench R20 1T benchmark. Results may vary. R5K-007: Testing by AMD Performance Labs as of 09/01/2020 using Cinebench R20 nT versus system wall power during full load CPU test using a Core i9--10900K, Ryzen 9 3900XT, Ryzen 9 5900X, Ryzen 9 3950X, and a Ryzen 9 5950X configured with: 2x8GB DDR4-3600, GeForce RTX 2080 Ti, Samsung 860 Pro SSD, Noctua NH-D15s cooler, and an open-air test bench with no additional power draw sources. Results may vary. R5K-009: Testing by AMD performance labs as of 09/01/2020 measuring gaming performance of a Ryzen 9 5900X desktop processor vs. a Ryzen 9 3900XT in 11 popular titles at 1920x1080, the High image quality preset, and the newest graphics API available for each title (e.g. DirectX® 12 or Vulkan™ or DirectX® 11). Results may vary. R5K-025: Testing by AMD Performance Labs as of September 23, 2020, using Ryzen(TM) 5000 Series processors: 5600X, 5800X, 5900X, 5950X and 3rd Gen Ryzen(TM) processors: 3600X, 3800XT, 3900XT and 3950X, configured with DDR4-3600C16 and NVIDIA GeForce RTX 2080 Ti, in Cinebench R20 1T. Results may vary.
  • 32.
    2.7: “Zen 3”:AMD 2nd Generation 7nm x86-64 Microprocessor Core © 2022 IEEE International Solid-State Circuits Conference 32 of 32 Disclaimer The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions, and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities that cannot be completely prevented or mitigated. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. THIS INFORMATION IS PROVIDED ‘AS IS.” AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY RELIANCE, DIRECT, INDIRECT, SPECIAL, OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. © 2022 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, EPYC, Infinity Fabric, Ryzen, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. PCIe is a registered trademark of PCI-SIG.