Innovation by Collaboration at Semicondynamics workshop

1. Innovation by Collaboration:
CHIPS Alliance
Rob Mains, General Manager, CHIPS Alliance
rmains@linuxfoundation.org,

2. The Linux Foundation: More than Linux
› 1500+ Members
From 40+ Countries
› 100% of Fortune 100
Tech & Telecom
› 30000+ Developers
Contributing Code
› 200+ Open Source
Projects
› $16B+ Shared Value
Security
Networking
Cloud
Automotive
Blockchain
Edge/IoT
Web
AI
Motion Pictures

3. Linux has Spawned a Collaborative, Open Source
Movement
11.7M
Lines of Code
Added Weekly
9.4M
Lines of Code
Removed Weekly
208,660
Contributing
Developers
12,435
Contributing
Companies
16,618
Repositories
9.1M
Commits
960,610
Pull Requests
1.3M
Builds Monitored
859,150
Logged Issues
5.2B
Container
Downloads
1.6M
Group Chat
Messages
3.6M
Group Email
Messages
4,532
Scanned
Repositories
282,342
Open
Vulnerabilities
62,379
Recommended
Fixes
36,163
Vulnerabilities
Fixed
31,496
CLA
Contributors
26,998
Community
Meetings

4. We are behind some of the most critical projects in the world
Security
Networking
Cloud
Automotive
Blockchain
Edge/IoT
Web
AI/ML/Data
Film
CI/CD
Energy
Hardware
Standards

5. What is CHIPS Alliance?
Its part of the Linux Foundation
An Organization which develops and hosts:
● Open source hardware specification, implementation, verification
○ Interconnect IP (physical and logical protocols)
○ CPUs
○ I/O (memory, SERDES, network…)
○ ML Accelerators
● Open source ASIC & FPGA development tools
○ Design, verification, simulation
○ Composition, electrical verification
● A barrier free environment for collaboration
○ Standards organization for collaboration and development
○ Legal Framework: Apache v2 license
○ IP contribution encouraged but not required for membership/participation
● Shared resources ($ and time) which lower cost of hardware development
Based on an Apache 2.0 license and other other open source licenses

6. CHIPS Alliance: A Neutral Territory
A place for interested parties to come together and work on hard problems of mutual interest

7. Auditor Members
Gold Members
Members

8. Industrial Evolution: Siloed to Collaboration
8
Soup to Nuts Silo: In House Supply Chain Management:
Overseer
Open Collaboration

9. Accelerating with More than Moore…
9
Traditional Scaling
Packaging
MCM
Chiplets
Software: Compilers and Libraries
Domain Specific Architectures
(DSA) : DAX, GPU, AI, FPGA

10. Chip Design Hierarchy: Architecturally the same, Collaboratively
Different
10
Yesterday
All In house Developed
Today
Purchased IP + In House
Tomorrow
Open Source, Purchased, In House
Similar to software components: Developed internally or from an external library

11. In other words: Lego Blocks Enabling Design Interchange
Soft IP Hard IP Chiplets
Pick your card to build a
winning hand!

12. But…Inter and Intra Continental Bastions?
12
Siloes and Fortresses
on each continent
China

13. U.S. Regional Business / Technology
Development Engines
13
Will this work? Does it build trust?
Collaboration is hard.

14. Why are barriers being raised?
● Security
– International
– Domestic
– Economic
– Intellectual
– Cyber
– Prestige
– Attracting the best minds
– But
– We still don’t collectively have enough engineering talent to address all the technical challenges
▸ Estimated +30K engineers to staff U.S. planned fab buildout: Georgetown Univ.
▸ Engineering isn’t for everybody. Not seen as fun or ‘cool’. It’s hard too.
▸ Can we reach the ‘Final Frontier’… to boldly go where no engineer has gone before?
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15. Education & Collaboration are the key to prosperity and understanding
▸ Global shortage of semiconductor engineering talent. Many areas:
– Semiconductor / process technology / silicon modeling
– Chip architecture
– Design
– Verification and physical implementation
– EDA
– Bring-up
▸ Are we suffering from the “Internal Brain Drain”
▸ NYT March 9 2024
▸ Students choosing other careers than engineering
▸ What’s needed?
▸ Education / Knowledge: U.S. NSF Chip hub call for proposals
▸ Open Source
▸ Trust
▸ Linux Foundation / CHIPS Alliance can be the backbone to serve many of these needs through its
education initiatives. We are a neutral platform.
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16. Workgroups
Tools
Cores
PDK
Interconnect
AI/ML Caliptra
F4PGA
Analog

17. Spice Models
Cell Electric Library Models
Routing Rules
Extraction
LVS/DRC
• Seeded by Google
• A continuation of their successful open source
PDK initiative
• Comprised of founding members:
○ -Antmicro
○ -Efabless
○ -Global Foundries
○ -Precision Innovation
○ -Skywater
• Goals
○ Align PDK versions to ensure quality
○ Adapt best practices from software community
■ -CI/CD
■ -Regressions / QOR tests
○ Spread adaption of open source technology for
■ -collaboration
■ -education
■ -research
○ Develop commercial & open source design
methodlogy & tools
Announcing the CHIPS PDK Workgroup

18. AI/ML in Chip Design, EDA, Chip Technology
Open Flywheels Encased Flywheels
Ingredients
PDK’sArchitecture EDA
Collaboration is Easy Collaboration is Hard

19. Caliptra: Silicon Root of Trust IP Block
Caliptra 1.0 Now Available
• Open source implementation,
Apache 2.0 licensed
• Reusable
• Collaboratively developed
• Targeted for Datacenters
• Measure, verify, and attest

20. AIB Protocols Project
SPI Verilog RTL: General purpose simple die-to-die protocol
● Ideal for device configuration, low-bandwidth control
● Taped out in silicon 12/2022
AXI4 Die-to-Die Verilog RTL: High performance data
read/writes and streaming
● New: Supports general purpose IOs as an alternative
to the Advanced Interface Bus (AIB)
● New: Latency Reference Guide for optimal buffer
sizing. Create your receive FIFO large enough to avoid
pipeline bubbles, small as possible to minimize die
area.
● Taped out in silicon 2/2023
Apache 2.0 licensing avoids weeks/months of license
negotiations
AXI4 over General Purpose I/Os Example SPI Application

21. 21
Red: on Github, Gray: Ideas
OmniXtend: Massive Scale Coherence Over Ethernet
● Open-Source Implementations Available
on GitHub
● Memory Endpoint
○ OmniXtend → AXI Memory Controller
(e.g., DDR 4, HBM)
○ Includes User Space Requester and
Simulation Libraries
● CVA6 to OmniXtend
○ Transparent Bridge Attaching
RISC-V to Coherent Remote Memory
● Protocol Extensions
○ Dynamic Connections
○ Out-of-band messages
● Ready to use/experiment

22. 22
RISC-V Implementation: VeeR Core and Verification Bench

23. 23
Making Hardware More Like Software
Many Choices
● Python, System Verilog, SystemC,
CHISEL
● Greatly expedites designer productivity
● Allows libraries of functionality
● Object oriented thinking
● Encourages participation by a broader
community
● High Level Synthesis to generate RTL
● Implementation tools to realize and
provide ‘guardrails’

24. Intel Compiler for SystemC
24
Intel Compiler for SystemC (ICSC)
● Translate SystemC to synthesizable SystemVerilog,
focused on design and verification efficiency
● SystemC synthesizable standard, C++11/14/17
● Dynamic elaboration, arbitrary C++ at elaboration phase
● Standard, fast and simple code translation procedure
● Human-readable generated SystemVerilog code
SingleSource Communication Channels
● Cycle-accurate mode: clocked design, no extra cost in area,
performance, and power
● Fast simulation mode: no clock, request-driven simulation,
no extra process activation, fast simulation Can be used in
● Functional interface like TLM 1.0
SystemC temporal assertions synthesizable to SVA
● Immediate and temporal assertions
● Can be used in module scope and process scope

25. F4PGA: Open Source Toolchain, Interchange Format and
More
• Established by CHIPS Alliance based on previous
work known as SymbiFlow
• F4PGA = FOSS Flow For FPGA
• Goal: drive open source tooling, IP and
research efforts for FPGAs
• Groups academia members, industry and
FPGA vendors
• Focus on:
▫ Open source toolchain for FPGAs (previously known
as SymbiFlow)
▫ FPGA Interchange Format
▫ FPGA Perf Tool
▫ Many more…
THE F4PGA WORKGROUP

26. Automating Analog & Digital Implementation with Open Source EDA

27. Overview of OpenFASOC: Fully Autonomous SoC Synthesis
● DARPA IDEA Program, now funded by Google, NIST and others
● Multiple tape-outs in TSMC 65, GF12LP, SKY130, GF180MCU, Intel 16
27
CHIPS Alliance
Workshop 2021-11
OpenPOWER AI Workshop
IBM - 2022-11
CHIPS Alliance Technology
Update 2022-12
RISCV Alliance Japan
2022-12
openfasoc.readthedocs.io
MPW1 MPW2 MPW4 MPW5 MPW6 MPW8
MPW7
Intel 16-nm
GF 12-nm
SKY130
GF 180
MPW0
+
more!
<3 years, <10 people!

28. Building Confidence in Open Design
Start of
Skywater’s
Open
MPW Program
Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec
End of 2020
Feb
MPW1 MPW2 MPW3 MPW4 MPW5 MPW6 MPW8
Project w. Fitbit
MPW7
28
Intel 16-
nm
GF 12-nm
SKY130
Dec ….
DARPA
IDEA
Program
Apr Jun
Nanofab.
Accelerator
program w. NIST
1st TO 2nd TO 3rd TO 4th TO
Globalfoundries
Open MPW
Program
GF 180
Intel’s University Shuttle
GF 180
Intel 16-
nm
May
28th
Feb
24th
NIST’s
Nanofabrication
Tapeout
MPW0
2022 2024
2021

29. CHIPS Alliance: Open Design Enablement with Catalog of Trusted Ingredients
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Implementation Framework
Verification Testbench
Functional Simulation, Formal, Emulation
Design Data Representation
Analog Tools Digital Tools
Physical
Macro
Cell
Library
Logical
Macro
Arch RTL UVM Props
Open Source Verified and Trusted IP Component Library
Verification and Implementation Platforms
Process Design Kit (PDK)

30. Join CHIPS Alliance
• Share resources to lower the cost of hardware development: digital and
analog IP
• Collaborate in developing of open source design tools software, share good
practices
• Receive high quality, open source CPU/SoC designs and complex IP blocks
• Grow your business in this forward thinking organization
• Read more about joining at https://chipsalliance.org/join
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31. Linux Foundation Membership Tiers and Benefits
* Prerequisite for Joining CHIPS Alliance. Details available at https://www.linuxfoundation.org/join/#benefits
Linux Foundation Membership Tier Summary
● Platinum: $500K / year
○ Offers board seat, 6 LF member summit invite, LF legal summit invites, prominent company advertising
● Gold: $100K / year
○ 3 Board representatives with other gold members
○ 4 LF member summit invite, 50 user e-learning tickets, marketing, LF executive access
● Silver: Employee Number Based
○ 5000+ $20,000 / year
○ 500 – 4999 $15,000 / year
○ 100 – 499 $10,000 year
○ 1 – 99 $5000 / year
○ 1 Invitation to LF member summit. 10 e-learning tickets
○ Display of company affiliation on LF websites and events
● Associate (Non-profit): Free
○ 1 board member in conjunction with other non-profits nominees
○ Display of company affiliation on CA websites, printed material
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32. CHIPS Alliance Membership Tiers and Benefits
CHIPS Alliance Membership Tier Summary
● Platinum: $30K / year
○ Offers board seat, TSC chair slots, event passes, prominent advertisement of company
● Gold: $12.5K / year
○ 2 Board representatives with other gold members
○ TSC chair slot eligible, event passes, prominent advertisement of company
● Silver: $5K / year
○ 1 board representative in conjunction with other silver members
○ Display of company affiliation on CA websites, printed material
● Auditor: $2.5K / year
○ No voting rights
○ Display of company affiliation on CA websites, printed material
● Associate (Non-profit): Free
○ 1 board member in conjunction with other non-profits nominees
○ Display of company affiliation on CA websites, printed material
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