ODSA Workshop: Development Effort Summary
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NXP presented, "ODSA Workshop: Development Effort Summary," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
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The FlexTiles Development Platform offers Dual FPGA for 3D SoC Prototyping
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The document discusses the formation of a new subgroup within ODSA focused on developing open standards for system-in-package solutions using chiplet technology. The subgroup aims to define an open architectural interface to allow best-of-breed chiplets from multiple vendors to be used together. It outlines several workstreams for participants to join related to developing the interface standards, building proof-of-concept demonstrations, and defining business and intellectual property models. A survey is also discussed that gathers input on drivers and barriers for adopting chiplet and system-in-package technologies as well as supply chain considerations.
ODSA - PoC Planning & Call for Help
The document discusses a Proof of Concept (PoC) project being undertaken by the PoC Working Group of ODSA. It provides an overview of the project leadership and participants. The PoC is finalizing its architecture, which will include identified chiplets and mechanical/connector specifications. It outlines the high level schedule and key tasks through December and calls for help with PCB design, manufacturing sponsorship, and software/firmware volunteers.
ODSA - DirectConnect Options for the PoC
The document discusses Firefly DirectConnect options for an ODSA proof of concept. It describes Firefly's small size and ability to fit 4 modules across a 50mm package edge. Firefly offers high performance through direct connection to the silicon package, eliminating signal distortion through the ball grid array region. It also provides flexibility by supporting both optical and high-speed copper modules in the same slot, and high power efficiency enabling 56G PAM4 transmission at minimal power per bit.
ODSA - PoC Physical Design Elements
The document discusses plans for a proof-of-concept multi-chiplet package. It will include an 8-layer flip chip ball grid array substrate containing chiplets, optical/electrical connectors, and decoupling capacitors. It also proposes an early software development vehicle using equivalent chips on a printed circuit board to speed up software and testing development while hardware is being designed. Developing the package involves tasks like design, simulation, fabrication, assembly, and reporting. The schedule estimates timelines for the various stages including substrate fabrication, assembly, design reviews, and simulations.
ODSA - NXP PoC Presentation
The document describes the NXP Layerscape series of Arm-based system on chip families. It provides details on several SoC models ranging from 1-100GbE networking, PCIe connectivity, memory support, security features, and power consumption between 1-35W. The LX2160 model is highlighted which features a 16-core 64-bit Arm Cortex-A72 CPU, networking up to 100GbE, memory controllers supporting up to 3.2GT/s DDR4, and integrated security accelerators while consuming around 30W.
ODSA - PoC Requirements and Use Cases
The document discusses requirements for a proof-of-concept (POC) involving a smart network interface card (NIC) and computational storage solutions. It proposes using an FPGA, network processor, and CPU module connected via PCIe and Ethernet to demonstrate different POC configurations for the smart NIC and computational storage, including as a standalone device, bump-in-the-wire, and with a data accelerator. The POC aims to validate interfaces and protocols, evaluate performance, and develop software models while exploring challenges of chiplet integration and business aspects of collaboration.
ODSA - Speedster22i FPGA for POC
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ODSA Design Tools for Chiplet-Based Design
The document discusses tools needed for chiplet-based integrated circuit design. It notes that while EDA companies offer many necessary design tools, they are currently offered piecemeal. Standards for defining chiplets electrically, mechanically, and thermally would help enable a chiplet marketplace. zGlue has developed a data exchange format for defining chiplets and their mechanical I/O, and power specifications to allow chiplet vendors to list their products while maintaining access control. The document promotes zGlue's ChipBuilder software and shuttle prototype program for designing with chiplets.
ODSA - Power and Heat
The document discusses power distribution and thermal management challenges for future chiplet-based architectures. It describes the current power architecture for Intel cores that uses a 1.8V input converted to an unregulated 0.9V supply. Future architectures may use local PMICs/chiplets with higher 3.3V or 5V inputs to reduce pins and separate analog and digital power domains, though conversion losses need to be dissipated. An active interposer could provide these conversion functions but poses technology and heat dissipation challenges. Thermal budgeting and local heating effects will require power/thermal controllers using temperature sensors. Chiplet specifications like voltage, current, thermal resistance, and interfaces will need to be standardized.
ODSA - PIPE Adapters
This document discusses the need for PIPE adapters to allow chiplet-based designs to function as a single die. It notes that while several high-speed SerDes exist, none directly support the PIPE interface which was developed by Intel for PCIe. PIPE adapters would be needed to divide the PIPE interface into multiple lanes that could be supported by the SerDes, which generally have higher speeds than individual PCIe lanes. The document outlines how a Kandou PIPE adapter would work and notes that while the complexity is less than the SerDes, PIPE adapters have not yet been developed into products and test chips would be useful to develop the interfaces.
ODSA - PHY Layer
The document discusses proposals for a standard physical layer interface to enable high data rate connections between chiplet products from different sources. Seven interface options are being considered, including AIB, silicon interposer, various parallel and SERDES-based approaches. Metrics for comparing the options are discussed, such as cost, performance, and design/integration complexity. Relative ratings of the options are provided based on initial discussions. Feedback is sought on priority metrics for different target markets.
OODSA - BoW: Basic, Fast, Turbo Die-to Die Open Interface Solutions
The document proposes the Bow interface standard for chiplet-based systems. Bow would define a simple source synchronous interface using CMOS IO to enable communication between dies up to 4Gbps per line untetherminated, or up to 12Gbps per line when terminated. It could also define a bidirectional "Bow Turbo" mode using hybrid circuits to allow simultaneous transmission and reception at up to 2x12Gbps per line. The proposal suggests this standard could improve compatibility for chiplet communication where bandwidth needs are modest, while examples from silicon implementation suggest it could efficiently deliver over 1Tbps of throughput per mm of chip edge. Volunteers are sought to further define options like test approaches and applications to evaluate the standard's value.
ODSA - Samsung Welcomes OCP's ODSA
Samsung Foundry is expanding from mobile chips to high performance computing. The author is personally interested in chiplet technology for several reasons: it could enable larger chip designs by connecting chiplets in multiple dimensions; allow for easier upgrading by swapping out chiplets; lower costs by reusing chiplets across designs; and enable new business models. The author sees a need for innovation in hardware to keep pace with the rapid advancement of software and AI models, and chiplet technology may help address this. Samsung is interested in contributing to the Open Domain Specific Architecture initiative but has not yet determined how.
ODSA - Technical Introduction
The document discusses the Open Domain Specific Architecture (ODSA) project, which aims to define an open interface for building complex application-specific integrated circuits (ASICs) from multiple die or "chiplets". This would allow best-of-breed chiplets from different vendors to be combined, reducing development costs compared to monolithic designs. The document provides an overview of domain-specific architectures and chiplets, proposes a reference multi-chiplet architecture and open interface, and outlines next steps to define standards and build a proof-of-concept through collaborative workstreams.
ODSA - OCP Welcome
The document is an agenda for the OCP ODSA Workshop held on March 28, 2019. It lists the schedule of presentations for the day-long workshop organized by the Open Compute Project (OCP). The workshop included presentations on accelerator technologies, standards and interfaces, design tools, proof of concept requirements and components, as well as discussions on business models and collaboration with OCP. Speakers came from companies like Samsung, Facebook, Netronome, Avera Semi, Kandou, Achronix, NXP and others.
ODSA - OCP Accelerator Module and the Infrastructure
The document discusses the need for an open accelerator infrastructure to support the growing variety of AI hardware accelerators. It proposes the Open Compute Project Accelerator Module specification to standardize the form factor and interfaces of accelerator modules. It also introduces the concept of a Universal Baseboard that can host multiple accelerator modules and uses a standardized interconnect to provide flexible topologies to scale performance for different AI workloads. The open infrastructure is intended to foster innovation while providing interoperability between accelerator modules and systems.
ODSA Sub-Project Launch
The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
Design and Testing Challenges for Chiplet Based Design: Assembly and Test View
zGlue Inc presented, "Design and Testing Challenges for Chiplet Based Design: Assembly and Test View," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
Chiplets in Data Centers
Facebook presented, "Chiplets in Data Centers," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
ODSA Workshop
Overview of the first ODSA Workshop 2019. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
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- 1. PUBLIC SAM FULLER - NXP SEMICONDUCTORS ODSA WORKSHOP DEVELOPMENT EFFORT SUMMARY SANTA CLARA JANUARY 2019
- 2. LS2 - Intelligent Storage Accelerator – Rev 1 § RDMA over Converged Ethernet (RoCE) § NVMe Controller on FSL SoC § NVMe over RoCE, HW offloading § Built-in Compression and Crypto HW accelerators § ARM Trust Zone support § 4 x 10GbE with DCB support § Two PCI-e Gen 3.0: x4 or x8 controllers § 16-bit Local Bus interface (FPGA backdoor communication) § One USB port for control and debugging § One SPI (Flash) § SoC will be mounted as a storage Device
- 3. LS2-iSSD(DragonFire Card) – Revision 2 • 8 Channel NAND module design (32 channels per card for max performance).
- 4. COMPANY CONFIDENTIAL4 LX2160: ARM Cortex A72 Processor Full Featured Highly Flexible Platform: 8-16 A72 Cores High Performance Packet Offload Engines Core Complex Standard interfaces Coherent Interconnect Security Engine (50Gbps) ARM Trust Zone Security Monitor Secure Boot Security Queue-Buffer Manager Power Management FlexSPI 2x SD/eMMC GPIO, JTAG 3x SPI 4x UART, 8x I2C x8 Gen4 PCle x4 Gen4 PCle x8 Gen4 PCle x4 Gen4 PCle x4 Gen4 PCle x4 Gen4 PCle SATA 3.0 SATA 3.0 SATA 3.0 SATA 3.0 72-bit (64- bit with ECC) Memory Controller 1 MB L2 Cache A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 A72 72-bit (64- bit with ECC) Memory Controller Accelerators and Memory Control High Speed interfaces Data Compression Engine (100Gbps) USB 3.0 w/ PHY 8 MB Platform Cache USB 3.0 w/ PHY Networking Elements 10 GbE 10 GbE 10 GbE 10 GbE 1GbE 1GbE 1GbE 1GbE 1GbE 1GbE 25GbE 25GbE 25GbE 25GbE 25GbE 25GbE 100GbE100GbE 130 Gbps L2 Switch 1 MB L2 Cache 1 MB L2 Cache 1 MB L2 Cache 1 MB L2 Cache 1 MB L2 Cache 1 MB L2 Cache 1 MB L2 Cache Core complex • 16x 64-bit Cortex-A72 with Neon SIMD engine • CPU Speed up to 2200 MHz • Parity and ECC protected 48 KB L1 instruction and 32 KB L1 data cache • 1 MB L2 cache with ECC protection/Cluster • 8 MB Platform Cache Basic peripheral and Interconnect • 2x USB 3.0 controllers with integrated PHY • 2x eSDHC controller supporting SD 3.0 and eMMC 4.5 modes Networking elements • Packet parsing, classification, and distribution • Queue Management for scheduling, packet sequencing and congestion management • Hardware buffer management for buffer allocation and de-allocation • Data compression • Data Center Bridging Support (iSCSI), TLV, DCBx, ETS(802.1Qaz), PFC(802.1Qbb) • L2 Switching with 1G, 2.5G, 10G, 25G, 40G, 50G and 100G Ethernet • Up to two RGMII interfaces • 6x PCI Express Gen 4 controllers (2 with SR-IOV support) • 4x SATA Gen 3.0 controllers Accelerators and Memory Control • 2x 64-bit DDR4 Controller with ECC support up to 3.2 GT/s • Security Engine (SEC) • QorIQ Trust architecture: Secure boot, ARM Trust zone and security monitor Package & Qualification • 16nm FinFet Compact • 40 x 40mm Flip chip, 1mm pitch, 1517 pins • Estimated Power 12- 28W VDD (thermal) at 105C, 2.2GHz • Commercial and Industrial temperature • AEC-Q100 Grade 3 reliability stresses
- 5. SmartNIC solutions using LX2160/LX2180 Enet Adapter Dual 25G No FPGA Dual 25G W/ FPGA & Adapter IC