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Similar to Ch5 lecture slides Chenming Hu Device for IC
Similar to Ch5 lecture slides Chenming Hu Device for IC (20)
Ch5 lecture slides Chenming Hu Device for IC
- 1. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-1 Chapter 5 MOS Capacitor MOS: Metal-Oxide-Semiconductor SiO2 metal gate Si body Vg gate P-body N+ MOS capacitor MOS transistor Vg SiO2 N+
- 2. Slide 5-2 This energy-band diagram for Vg = 0 is not the simplest one. N+ polysilicon SiO2 P-Siliconbody Chapter 5 MOS Capacitor Modern Semiconductor Devices for Integrated Circuits (C. Hu) Ef , Ec Ev Ev Si Body Gate Ec Ec Ev Ef
- 3. Slide 5-3 5.1 Flat-band Condition and Flat-band Voltage E0 : Vacuum level E0 – Ef : Work function E0 – Ec : Electron affinity Si/SiO2 energy barrier sgfbV cSiO2 =0.95 eV 9 eV Ec, Ef Ev Ec Ev Ef 3.1 eV q s = cSi + (Ec –Ef )qg cSi E0 3.1 eV Vfb N+ -poly-Si P-body 4.8 eV =4.05eV Ec Ev SiO2 The band is flat at the flat band voltage. q Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 4. Slide 5-4 5.2 Surface Accumulation oxsfbg VVV 3.1eV Ec ,Ef Ev E0 Ec Ef Ev M O S qVg Vox qs Make Vg < Vfb s is negligible when the surface is in accumulation. s : surface potential, band bending Vox: voltage across the oxide Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 5. Slide 5-5 5.2 Surface Accumulation fbgox VVV )( fbgoxacc VVCQ oxsox CQV / oxaccox CQV /Gauss’s Law Modern Semiconductor Devices for Integrated Circuits (C. Hu) Vg <Vt
- 6. Slide 5-6 ox ssa ox depa ox dep ox s ox C qN C WqN C Q C Q V 2 5.3 Surface Depletion ( )gV > Vfb Ec, Ef Ev Ec Ef Ev M O S qVg depletion region qs Wdep qVox --- -SiO 2 gate P-Si body + + + + + + - - - - - - - V - - - - - - - depletion layer charge, Qdep - - - - - - - Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 7. Slide 5-7 5.3 Surface Depletion ox ssa sfboxsfbg C qN VVVV 2 This equation can be solved to yield s . Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 8. Slide 5-8 5.4 Threshold Condition and Threshold Voltage Threshold (of inversion): ns = Na , or (Ec–Ef)surface= (Ef – Ev)bulk , or A=B, and C = D i a Bst n N q kT ln22 i a a v i v bulkvf g B n N q kT N N q kT n N q kT EE E q lnlnln|)( 2 Ec,Ef M O S Ev Ef Ei Ec A B C =qB Ev D qVg =qVt st Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 9. Slide 5-9 Threshold Voltage ox Bsa Bfbgt C qN VthresholdatVV 22 2 oxsfbg VφVV At threshold, i a Bst n N q kT ln22 ox Bsa ox C qN V 22 Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 10. Slide 5-10 Threshold Voltage ox Bssub Bfbt C qN VV 22 2 + for P-body, – for N-body (a) Tox= 20nm Vt(V),N+gate/P-body Vt(V),P+ gate/N-body Body Doping Density (cm-3) ody ody Tox= 20nm Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 11. Slide 5-11 5.5 Strong Inversion–Beyond Threshold Ec,Ef Ev Ec Ef Ev M O S qVg - - ---- a Bs dmaxdep qN WW 22 Vg > Vt SiO2 gate P- Si substrate ++++++++++ V Vg > Vt - - - - - --- - - - - - - - Qdep Qinv Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 12. Slide 5-12 Inversion Layer Charge, Qinv (C/cm2) ox inv t ox inv ox Bsa Bfb ox inv ox dep Bfbg C Q V C Q C qN V C Q C Q VV 22 22 )( tgoxinv VVCQ Modern Semiconductor Devices for Integrated Circuits (C. Hu) Vg > Vt Vg > Vt
- 13. Slide 5-13 5.5.1 Choice of Vt and Gate Doping Type Vt is generally set at a small positive value so that, at Vg = 0, the transistor does not have an inversion layer and current does not flow between the two N+ regions • P-body is normally paired with N+-gate to achieve a small positive threshold voltage. • N-body is normally paired with P+-gate to achieve a small negative threshold voltage. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 14. Slide 5-14 Review : Basic MOS Capacitor Theory s 2B Vf b V t Vg accumulation depletion inversion Wdep Wdmax accumulation depletion inversion (s )1/2 Wdmax = (2s 2B /qNa )1/2 Vg V t Vf b Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 15. Slide 5-15 Review : Basic MOS Capacitor Theory 0 Vg accumulation depletion inversion Qinv accumulation depletion inversion (a) (b) accumulation depletion inversion (c) Qs 0 accumulation regime depletion regime inversion regime total substrate charge, Qs invdepaccs QQQQ Qacc Vg Vg Qdep=- qNaWdep Vt Vfb slope = Cox slope = Cox VtVfb Vt Vfb –qNaWdep –qNaWdmax Vg Qinv slope = Cox Vfb Vt Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 16. Slide 5-16 5.6 MOS CV Characteristics g s g g dV dQ dV dQ C C-V Meter MOS Capacitor Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 17. Slide 5-17 5.6 MOS CV Characteristics g s g g dV dQ dV dQ C Qs 0 Vg accumulation regime depletion regime inversion regime Qinv C Vfb Vt Cox accumulation depletion inversion Vg Vt Vfb slope = Cox Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 18. Slide 5-18 CV Characteristics depox CCC 111 sa fbg ox qN VV CC )(211 2 C Cox accumulation depletion inversion Vg Vfb Vt In the depletion regime: Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 19. Slide 5-19 Cox gate P-substrate - - - - - -- Cdmax Wdmax - - - - - - - AC DC +++++ + + + + Cox gate P-substrate Cox gate P-substrate - - - - - - Cdep Wdep Cox gate P-substrate - Wdmax - - - - - - -N+ DC and AC Supply of Inversion Charge May be Limited Accumulation Depletion Inversion Inversion In each case, C = ? Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 20. Slide 5-20 Capacitor and Transistor CV (or HF and LF CV) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 21. Slide 5-21 Quasi-Static CV of MOS Capacitor The quasi-static CV is obtained by the application of a slow linear- ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows sufficient time for Qinv to respond to the slow-changing Vg . C Cox accumulation depletion inversion Vg Vfb Vt Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 22. Slide 5-22 (1) MOS transistor, 10kHz. (Answer: QS CV). (2) MOS transistor, 100MHz. (Answer: QS CV). (3) MOS capacitor, 100MHz. (Answer: HF capacitor CV). (4) MOS capacitor, 10kHz. (Answer: HF capacitor CV). (5) MOS capacitor, slow Vg ramp. (Answer: QS CV). (6) MOS transistor, slow Vg ramp. (Answer: QS CV). EXAMPLE : CV of MOS Capacitor and Transistor Does the QS CV or the HF capacitor CV apply? C Vg QS CV HF capacitor CV MOS transistor CV, Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 23. Slide 5-23 5.7 Oxide Charge–A Modification to Vfb and Vt oxoxsgoxoxfbfb CQCQVV //0 Ef, Ec Ev Ec Ef Ev Vfb0 gate oxide body Ef, Ec Ev Ec Ef Ev Vfb gate oxide body + + + Qox/Cox (a) (b) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 24. Slide 5-24 Types of oxide charge: • Fixed oxide charge, Si+ • Mobile oxide charge, due to Na+contamination • Interface traps, neutral or charged depending on Vg. • Voltage/temperature stress induced charge and traps--a reliability issue 5.7 Oxide Charge–A Modification to Vfb and Vt Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 25. Slide 5-25 EXAMPLE: Interpret this measured Vfb dependence on oxide thickness. The gate electrode is N+ poly-silicon. oxoxoxsgfb TQV /Solution: What does it tell us? Body work function? Doping type? Other? 0 –0.15V –0.3V Tox Vfb 10 nm 20 nm 30 nm Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 26. Slide 5-26 from intercept V15.0 sg from slope 28 cm/C107.1 oxQ -317eV15.0 cm10 kT cd eNnNN-type substrate, E0 , vacuum level Ef , Ec Ev Ec Ef Ev g s = g + 0.15V N+-Si gate Si body Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 27. Slide 5-27 5.8 Poly-Silicon Gate Depletion–Effective Increase in Tox Gauss’s Law polyoxoxdpoly qNW /E 3/ 11 11 dpolyox ox s dpoly ox ox polyox WT WT CC C If Wdpoly= 15 Å, what is the effective increase in Tox? Cox N-body Cpoly ++ + + + + + +P+ Ec Ef Ev (b) P+ poly-Si P+ Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 28. Slide 5-28 Effect of Poly-Gate Depletion on Qinv )( tpolygoxinv VVCQ • How can poly-depletion be minimized? Wdpoly Ec Ef, Ev Ec Ef Ev qpoly P+ -gate N-substrate • Poly-gate depletion degrades MOSFET current and circuit speed. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 29. Slide 5-29 EXAMPLE : Poly-Silicon Gate Depletion Vox , the voltage across a 2 nm thin oxide, is –1 V. The P+ poly- gate doping is Npoly = 8 1019 cm-3 and substrate Nd is 1017cm-3. Find (a) Wdpoly , (b) poly , and (c) Vg . Solution: (a) nm3.1 8C106.1cm102 V1)F/cm(1085.89.3 // 197 14 cm10 319 polyoxoxoxpolyoxoxdpoly qNTVqNW E Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 30. Slide 5-30 (b) poly polys dpoly qN W 2 V11.02/2 sdpolypolydpoly WqN (c) V01.1V11.0V1V85.0V95.0 V95.0V15.0V1.1ln g d cg fb polyoxstfbg V N N q kT q E V VVV Is the loss of 0.11 V from the 1.01 V significant? EXAMPLE : Poly-Silicon Gate Depletion Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 31. Slide 5-31 5.9 Inversion and Accumulation Charge-Layer Thickness–Quantum Mechanical Effect Average inversion-layer location below the Si/SiO2 interface is called the inversion-layer thickness, Tinv . n(x) is determined by Schrodinger’s eq., Poisson eq., and Fermi function. -50 -40 -30 -20 -10 0 10 20 30 40 A Electron Density Quantum mechanical theory SiO2 poly-Si depletion region Å 50 Tinv SiGate Effective Tox Physical Tox Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 32. Slide 5-32 Electrical Oxide Thickness, Toxe • Tinv is a function of the average electric field in the inversion layer, which is (Vg + Vt)/6Tox (Sec. 6.3.1). • Tinv of holes is larger than that of electrons because of difference in effective mass. •Toxe is the electrical oxide thickness. 3/3/ invdpolyoxoxe TWTT at Vg=Vdd Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 33. Slide 5-33 Effective Oxide Thickness and Effective Oxide Capacitance )( tgoxeinv VVCQ C Basic CV with poly-depletion with poly-depletion and charge-layer thickness Vg measured data Cox 3/3/ invdpolyoxoxe TWTT Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 34. Slide 5-34 Equivalent circuit in the depletion and the inversion regimes Cpoly Cox Cdep Cinv Cox Cdep Cpoly Cox Cdep,min Cinv Cinv Cox (a) (b) (c) (d) General case for both depletion and inversion regions. In the depletion regions Vg Vt Strong inversion Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 35. Slide 5-35 5.10 CCD Imager and CMOS Imager Deep depletion, Qinv= 0 Exposed to light 5.10.1 CCD Imager + --- Ec , Ef Ev Ec Ef Ev Ec, Ef Ev (a) (b) - Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 36. Slide 5-36 CCD Charge Transfer P-Si oxide V2 - - -- - - -- - - - -- - -depletion region P-Si oxide - - -- - - -- depletion region P-Si oxide - - -- - - -- depletion region (a) (b) (c) V1 > V2 = V3 V1 V2 V3 V1 V3 V1 V2 V3 V1 V2 > V1 > V3 V2 > V1 = V3 V1 V2 V3 V1 V2 V3 V1 Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 37. Slide 5-37 two-dimensional CCD imager The reading row is shielded from the light by a metal film. The 2-D charge packets are read row by row. Signal out Charge-to-voltage converter Reading row, shielded from light Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 38. Slide 5-38 5.10.2 CMOS Imager CMOS imagers can be integrated with signal processing and control circuitries to further reduce system costs. However, The size constrain of the sensing circuits forces the CMOS imager to use very simple circuits Modern Semiconductor Devices for Integrated Circuits (C. Hu) PN junction charge collector switch Amplifier circuit Shifter circuit Signal out V2 V1 V3
- 39. Slide 5-39 5.11 Chapter Summary N-type device: N+-polysilicon gate over P-body P-type device: P+-polysilicon gate over N-body )/( oxoxsgfb CQV polyoxssfb polyoxsfbg CQV VVV / Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 40. Slide 5-40 i sub B n N q kT ln Bst 2 )V45.0( Bor ox stssub stfbt C qN VV ||2 + : N-type device, – : P-type device 5.11 Chapter Summary Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 41. Slide 5-41 N-type Device (N+-gate over P-substrate) P-type Device (P+-gate over N-substrate) What’s the diagram like at Vg > Vt ? at Vg= 0? Ef Ef Vg>Vfb>0 Ef Ef Vg<Vfb<0 Accumulation Ef Ef Vg=Vfb<0 Ef Ef Vg=Vfb>0 Flat-band EfEf Vg0>Vfb Ef Ef Vg0<Vfb Ef Vg=Vt>0 Ef Ef Ef Vg=Vt<0Threshold Depletion Ef Ef Vg=Vfb<0 Ef Ef Vg=Vfb>0 Flat-band EfEf Vg0>Vfb EfEf Vg0<Vfb Ef Vg=Vt>0 Ef Ef Ef Vg=Vt<0Threshold Depletion Ef Vg>Vt>0 Ef Vg<Vt Inversion 5.11 Chapter Summary Modern Semiconductor Devices for Integrated Circuits (C. Hu)
- 42. Slide 5-42 What is the root cause of the low C in the HF CV branch? 5.11 Chapter Summary Vg N-type Device (N+ -gate over P-substrate) P-type Device (P+ -gate over N-substrate) Vg QS CV Transistor CV Capacitor (HF) CV Modern Semiconductor Devices for Integrated Circuits (C. Hu)