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![University of Connecticut 248
DCFL Applications
n For a given minimum linewidth, GaAs DCFL circuitry is about 2
to 3 times faster than Si CMOS because of the difference in
electron mobilities.
n The extra speed comes at a premium, because GaAs
technology is less developed and DCFL is expensive.
n DCFL applications are at the high end, where the extra cost can
be justified. Examples are the Cray Y-MP and the Vitesse
Semiconductor GaAs microprocessor, which boasts 1.2 M
transistors [see Ira Deyhimy, “Gallium Arsenide Joins the Giants,” IEEE
Spectrum, pp. 33-40, February 1995].
n At the present time, the area of fastest growth for GaAs DCFL is
communications.
n A factor of three isn’t much, though, when you consider the rapid
advancement of Si CMOS / BiCMOS technology.](https://image.slidesharecdn.com/bicoms-210427032303/75/Bicoms-25-2048.jpg)
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- 1. University of Connecticut224 BiCMOS Logic Gates
- 2. University of Connecticut225 BiCMOS - Best of Both Worlds? n CMOS circuitry exhibits very low power dissipation, but n Bipolar logic achieves higher speed and current drive capability. n BiCMOS achieves low standby dissipation like CMOS, but high speed and current drive capability like TTL and ECL. n The disadvantage of BiCMOS is fabrication complexity (up to 30 masking steps, compared to about 20 for bipolar logic or CMOS). This translates into higher cost and longer design cycles. n Notable examples of the BiCMOS technology are the Intel P6 (a.k.a. Pentium Pro) which appeared in 1996, and its successor the P7. $
- 3. University of Connecticut226 BiCMOS Inverter n P1 and N1 perform the logic function. n QP and QO are low- impedance output drivers. n N2 and N3 remove base charge from the bipolar transistors during switching. QP QO P1 N3 N1 N2 VOUT VIN VDD
- 4. University of Connecticut227 BiCMOS Inverter QP QO P1 N3 N1 N2 VOUT VIN VDD VIN = 0. VIN = VDD.
- 5. University of Connecticut228 BiCMOS Inverter VTC • The BiCMOS inverter shown here exhibits reduced logic swing (VDD - 2VBEA) compared to CMOS (VDD). • Reduction of the supply voltage will make this problem more severe. 0.0 1.0 2.0 3.0 0.0 1.0 2.0 3.0 VIN VOUT CMOS BiCMOS V V K A V V V V V DD T F BEA = = = = = 3 3 40 1 50 0 7 2 . / . µ β
- 6. University of Connecticut229 BiCMOS NAND Gate QP QO PA NB3 NA1 N2 VOUT VA VDD VB PB NB1 NA3 With both inputs high: With VA high, VB low:
- 7. University of Connecticut230 How Fast is BICMOS? n For highly-capacitive off-chip loads, fast switching is possible due to the high current driving capability of the bipolar transistors. The speed is limited by the parasitic capacitances of the QP, which must be driven by the P1 - N3 CMOS circuit. n For on-chip loads presenting very little capacitance, BiCMOS offers no advantage if CL < CBCP n BiCMOS integrated circuits are really CMOS on the inside! QP QO P1 N3 N1 N2 VOUT VIN VDD
- 8. University of Connecticut231 BiCMOS Applications n Modern BiCMOS, invented by Intel, hit the market in 1992. n Ever-increasing clock frequencies on motherboards of PC’s and workstations may require that the VLSI / ULSI chips be made in BiCMOS. (Witness the Intel, AMD, and Cyrix µP chips.) n Central Processing Units (CPU’s) of “minisupercomputers” can be implemented in BiCMOS, with packing density and dissipation advantages over ECL. (e.g., the Cray Research “Baby Cray” J916 Computer) n TTL will soldier on in motherboard SSI and MSI applications, where BiCMOS does not boast an advantage. n But … the BiCMOS party may be over when supply voltages drop below 1.8 V. BJT’s have a fixed turn-on voltage; MOSFET thresholds can be reduced to at least 0.3V for room temperature operation.
- 9. University of Connecticut232 The Problem with BiCMOS n For standard BiCMOS, the logic swing is VDD - 2VBEA. n Supply voltages are continually being reduced, because n When VDD is reduced to 1.8V, standard BiCMOS will provide a logic swing of only 0.4V; this isn’t acceptable! We can provide shunt elements which increase the voltage swing of BiCMOS, but … n Turning off the BJT’s isn’t the answer! If the supply voltage is 1.8V, the BJT’s can only conduct for n In this case the BJT’s can not effectively boost the switching speed. P C V L DD ≈ 2 0 7 11 . . V V V OUT ≤ ≤
- 10. University of Connecticut233 Full-Rail BiCMOS Inverter w/ Resistive Shunts QP QO P1 N1 VOUT VIN VDD R1 R2 • This BiCMOS design provides a rail-to-rail voltage swing. • For VOUT < VBEA, N1 and R2 conduct, bringing VOL all the way to 0. • For VBEA < VOUT < VDD - VBEA, one or both BJT’s conducts. • For VDD - VBEA < VOUT, P1 and R1 conduct, bringing VOH all the way to VDD. • It is not practical to fabricate this circuit with resistors, but a similar circuit can be made using an active shunt for QO.
- 11. University of Connecticut234 BiCMOS Inverter w/ Active Shunt QP QO P1 N1 VOUT VIN VDD • This BiCMOS design provides a voltage swing of VDD - VBEA. • For VOUT < VBEA, N3 and N2 conduct, bringing VOL all the way to 0. • For VBEA < VOUT < VDD - VBEA, one or both BJT’s conducts. • The base-emitter junction of QP is not shunted, so VOH = VDD - VBEA. N2 N3
- 12. University of Connecticut235 Full Rail BiCMOS Inverter w/ Paralleled CMOS Output QP QO P1 N3 N1 N2 VOUT VIN VDD NO PO • The parallel CMOS inverter provides rail-to-rail operation. • For VOUT < VBEA, NO conducts, bringing VOL all the way to 0. • For VBEA < VOUT < VDD - VBEA, one or both BJT’s conducts. • For VDD - VBEA < VOUT, PO conducts, bringing VOH all the way to VDD.
- 13. University of Connecticut236 Buffered CMOS
- 14. University of Connecticut237 CMOS - Single Stage VDD = 1.8V VIN VT = -0.6V 2.2µ m/ 0.5µ m VT = 0.6V 0.9µ m/ 0.5µ m tP = VOUT CL 2 ' 2 ' / 200 / 80 100 V A k V A k Angstroms t N P OX µ µ = = = = A
- 15. University of Connecticut238 CMOS - Single Stage / 50pF VDD = 1.8V VIN VT = -0.6V 2.2µ m/ 0.5µ m VT = 0.6V 0.9µ m/ 0.5µ m VOUT 50pF = = N P K K = P t
- 16. University of Connecticut239 CMOS - Three Stages / 50pF VDD = 1.8V VIN 2.2/ 0.5 VOUT 50pF = P t 0.9/ 0.5 11/ 0.5 4.5/ 0.5 55/ 0.5 22/ 0.5 = = = 1 1 1 P L t C K = = = 2 2 2 P L t C K = = = 3 3 3 P L t C K
- 17. University of Connecticut240 CMOS - Six Stages / 50pF VDD = 1.8V VIN 2.2/ 0.5 0.9/ 0.5 11/ 0.5 4.5/ 0.5 55/ 0.5 22/ 0.5 = = = 1 1 1 P L t C K = = = 2 2 2 P L t C K = = = 3 3 3 P L t C K WIRED TO THE NEXT PAGE!
- 18. University of Connecticut241 CMOS - Six Stages / 50pF VDD = 1.8V 275/ 0.5 VOUT 50pF = P t 110/ 0.5 1375/ 0.5 550/ 0.5 6875/ 0.5 2750/ 0.5 = = = 5 5 5 P L t C K = = = 6 6 6 P L t C K WIRED FROM THE PREVIOUS PAGE! = = = 4 4 4 P L t C K
- 19. University of Connecticut242 GaAs Direct-Coupled FET Logic (DCFL)
- 20. University of Connecticut243 DCFL Inverter VOUT VIN VDD • DCFL gates are similar to NMOS circuits, but are implemented with GaAs MESFET’s rather than Si MOSFET’s. • The advantage of DCFL is speed - it is up to 3 times faster than CMOS. • The disadvantages of DCFL are fabrication complexity and cost. • GaAs 75 mm wafer - $100 • Si 200 mm wafer - $10 • Si 300 mm wafers - coming soon! • GaAs technology is less established compared to Si technology, and the fabrication of enhancement type MESFET’s is difficult.
- 21. University of Connecticut244 DCFL Inverter - Basic Operation VOUT VIN VDD NL NO VIN = LOW. VIN = HIGH.
- 22. University of Connecticut245 DCFL NOR Gate VOUT VB VDD NL NOB VA NOA VA = VB = VOL. VA = VDD or VB = VDD. DCFL NAND gates are not practical due to restrictions imposed on VDD, VOL, and the enhancement device threshold voltages.
- 23. University of Connecticut246 Buffered DCFL NOR Gate VB VDD VA The added source follower provides a low-impedance output driver for off-chip loads. VOUT VB VA
- 24. University of Connecticut247 DCFL Characteristics Compare the 1999 state-of-the art for GaAs DCFL and Si CMOS: GaAs DCFL vs. Si CMOS: 0.25 µm technology propagation delay dissipation SRAM embedded in VLSI GaAs DCFL 35 ps 30 µW (DC) 32 kB Si CMOS 75 ps 1 µW / MHz 128 kB • GaAs exhibits higher electron mobility than Si. • Due to the GaAs electron velocity characteristic, DCFL can operate at a reduced supply voltage without a penalty in switching speed.
- 25. University of Connecticut248 DCFL Applications n For a given minimum linewidth, GaAs DCFL circuitry is about 2 to 3 times faster than Si CMOS because of the difference in electron mobilities. n The extra speed comes at a premium, because GaAs technology is less developed and DCFL is expensive. n DCFL applications are at the high end, where the extra cost can be justified. Examples are the Cray Y-MP and the Vitesse Semiconductor GaAs microprocessor, which boasts 1.2 M transistors [see Ira Deyhimy, “Gallium Arsenide Joins the Giants,” IEEE Spectrum, pp. 33-40, February 1995]. n At the present time, the area of fastest growth for GaAs DCFL is communications. n A factor of three isn’t much, though, when you consider the rapid advancement of Si CMOS / BiCMOS technology.