I2C communication protocol is explained in a detailed manner.

1. I2C COMMUNICATION
PROTOCOL
PRESENTED BY: SHANKAR

2. AGENDA
• Overview of I2C
• Features of I2C
• I2C Operation
• Internal circuit
• Fast Open Drain (FOD)
• Start and stop
• Frame format
• Master state machine
• Slave state machine
• General call address
• Bus Arbitration
• Bus capacitance
• Clock stretching
• I2C bus extenders
• I2C bus multiplexers
• I2C bus analyzers and exercisers
• Commonly faced issues

3. I2C communication is the short form for inter-
integrated circuits.
I2C is a serial protocol for two-wire interface to
connect low-speed devices like microcontrollers,
EEPROMs, A/D and D/A converters, I/O
interfaces and other similar peripherals in
embedded systems.
OVERVIEW OF I2C

4. FEATURES
OF I2C
• I2C is a synchronous serial communication.
• I2C supports upto 3.4 MBPS speed. Speed can vary
depending on the master and slave capabilities.
• Supported Speeds:
• 100 KBPS(Standard Mode)
• 400 KBPS(Fast Mode)
• 3.4 MBPS(Fast Mode Plus)
• I2C is a Master slave protocol where Master controls the
transactions.
• I2C is Half Duplex bi-directional protocol.
• Data length is fixed to 8 bits unlike in UART and SPI
where different data byte lengths are possible.
• Slave addressing modes supported are 7 bit and 10 bit.
• Only two lines are required for communication.

5. I2C
OPERATION
• I2C bus consists of two pins
namely Serial Clock(SCL) and
Serial Data(SDA).
• Devices on the bus can act as
master or slave.
• Bus is entirely controlled by
Master. i.e. only master can
initiate a read/write
transaction.
• Multiple masters and slaves
can be connected on same
bus.
• Each slave should have unique
slave address.
• Master can also act as slave
and can address itself on the
bus.

6. INTERNAL
CIRCUIT
• Open drain pins are used
for SCL and SDA lines.
• Open drain pins are
dominant 0 logic.
• If one slave is powered OFF,
it won’t impact the
performance of other
devices. Otherwise if one
device got damaged and
pulls the line low, then
entire BUS hangs up.
• Some devices support Fast
Open Drain pins(FOD) to
reduce the rise time of the
SCL and SDA lines.

7. START AND STOP
• When SCL is high, if SDA line
goes from high to low is treated
as start condition.
• When SCL is high, if SDA line
goes from low to high is treated
as stop condition.
• A start without a stop condition
is treated as Repeated start.
• I2C BUS is treated busy in
between start and stop
conditions. NO OTHER master is
allowed to initiate a transaction

8. FRAME FORMAT

9. MASTER STATE MACHINE

10. SLAVE STATE MACHINE

11. GENERAL CALL ADDRESS
• The general call address is for addressing every device
connected to the I2C-bus at the same time.
• If a device does require data from a general call address, it
behaves as a slave-receiver.
• The master does not actually know how many devices are
responsive to the general call.
• General call can only write data to slave, not read.

12. BUS ARBITRATION
• When two masters started to
initiate a transaction at the same
time, i.e. they both initiated a
start condition at the same time,
one which is trying to drive logic
high while the other is driving
low, looses the arbitration. Since
I2C bus is dominant 0, logic 0
takes priority and appears on
the BUS.

13. BUS CAPACITANCE
• Bus capacitance plays major role
in I2C bus speed.

14. CLOCK STRETCHING
• I2C devices can slow down
communication
by stretching SCL: During an
SCL low phase, any I2C
device on the bus may
additionally hold down SCL to
prevent it from rising again,
enabling it to slow down the
SCL clock rate or to stop I2C
communication for a while.
• Clock is stretched by the slave
device if clock rate is higher. E.g.

15. I2C BUS EXTENDERS
• Supports Bidirectional Data
Transfer of I 2C Bus Signals
• Allows Bus Capacitance of 400 pF
on Main I 2C Bus (Sx/Sy Side) and
3000 pF on Transmission Side
(Lx/Ly Side)
• It may also be used for level
translation.

16. I2C BUS
MULTIPLEXERS
• Sometimes there may be a need
to connect two devices with
same address to single I2C
master. In such cases, an I2C
multiplexer can be used to
communicate to a particular
device.

17. I2C BUS ANALYZERS AND EXERCISERS
• Logic analyzers like Saleae Logic are used for capturing and
analyzing I2C bus data.
• Aardvark I2C/SPI Host Adapter can be used to do master/slave
I2C transactions.

18. COMMONLY FACED ISSUES
• No I2C pull-up resistors are connected.
• SCL and SDA are interchanged.
• Conflicting address in the slaves.
• Excessive bus capacitance makes impossible for the bus to
reach logic High.
• Spurious glitches on the lines may be treated as start condition
and the bus may go into busy state.

19. THANK YOU