Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.

1. Ahmed Abdelazeem
Ahmed Abdelazeem
Ahmed Abdelazeem
Ahmed Abdelazeem
STA Basic Concepts
{ Concepts } + { Technique }
Ahmed Abdelazeem

2. Ahmed Abdelazeem
Ahmed Abdelazeem
Agenda
What is STA? 01
Delay
Calculation
02
Constraints
Develop
03
Timing
Verification
04
Special Timing
Checks
05
Crosstalk & Noise
06
STA
Methodology
07
Signoff
Checklist
08

3. Ahmed Abdelazeem
Ahmed Abdelazeem
Practice in Mind
1
2
3
Establish Key concepts used in STA
Correctly constrain ASIC design using SDC
Interperate most common timing report
4 Basic timing closure approach

4. Ahmed Abdelazeem
Ahmed Abdelazeem
Goal of this course
DC/FC and Primetime
We made up some examples for industry standard backend tool
Design/Fusion Compiler and Primetime.
Both has built-in STA engine while DC/FC is more emphasis on
implementation side and PT is more on timing verification side.
28 Special Topics
We go over as many as 28 different special topics to extend the key knowledge
point discussed.
These topics are also made to be easily understood and very practical.
Rules of thumb
We introduce a number of rules to certain knowledge point so it clarifies un-
defined conceptual confusion.
You are welcome to test out these rules in your real-life example.

5. Ahmed Abdelazeem
Ahmed Abdelazeem 4
✓ Static Timing Analysis Definition
✓ Limitation of STA
✓ Operation Condition
✓ Library Scaling
✓ Inputs to STA analysis
What is STA ?
01

6. Ahmed Abdelazeem
Ahmed Abdelazeem
Static Timing Analysis (STA)
STA is a technique for digital design verification. It:
• Validates if the design can operate at the set timing constraints
• Is a complete and exhaustive verification of all timing checks of a design
• Is used instead of simulation
0 2 4 6
A
C
O
Vector-less topological analysis of a circuit.
• The signal at the input is propagated through the gates at each level till it reaches the
output

7. Ahmed Abdelazeem
Ahmed Abdelazeem
Simulation
Simulating (dynamically) circuit response for a specified set of input patterns
Circuit modeled as network of capacitors, resistors and voltage/current sources
0 1 0
0 1 1

8. Ahmed Abdelazeem
Ahmed Abdelazeem
Why we need STA?
Static Timing Analysis
We need a fast method that produce relatively accurate timing results compared
to SPICE simulation
SPICE simulation
Accurate, but can be computational expensive and take too much time for today’s million
gate ASIC design.
Timing Problem
Given a circuit design, find if path delay could meet system timing requirement.

9. Ahmed Abdelazeem
Ahmed Abdelazeem
S E
F C
Static
Fast and large capacity.
Does not use dynamic logic simulation.
Collapse whole design into minimal cycle and analyze
once.
Functionality
Does not verify logic functionality.
Need equivalence checking on the side.
Exhaustive
Use mathematical techniques instead of input vectors.
Required timing checks are performed on all possible paths
and scenarios
Conservative
Be pessimistic and conservative in many cases to ensure
there is enough guard band for the design timing
requirement
Features of STA
Synchronous Design Only
Does not verify asynchronous part of the
design

10. Ahmed Abdelazeem
Ahmed Abdelazeem
Place &
Route
Logic
Synthes
is
RTL
coding
Power
Integrity
Timing
Role of STA

11. Ahmed Abdelazeem
Ahmed Abdelazeem
Limitation of STA
1
2
3
Conservative & Pessimistic
Flag false paths
Not suitable for asynchronous design

12. Ahmed Abdelazeem
Ahmed Abdelazeem
STA vs. Simulation
Simulation
❑ Advantages
Can be very accurate
(Spice-level)
❑ Disadvantages
Analysis quality depends on stimulus vectors
Non-exhaustive, slow
• Static Timing Analysis (STA)
• Advantages
- Exhaustive timing coverage
- Does not require input vectors
- Faster operation
• Disadvantages
- Less accurate
- Must define timing requirements/exceptions
- Difficulty in handling asynchronous designs, false
paths

13. Ahmed Abdelazeem
Ahmed Abdelazeem
Problem Variability
Other variables affect circuit timing, thus need to be considered during design
❑ Operating Conditions
Process, Voltage, Temperature variations
❑ Unstable clock frequency (jitter, skew)
Instability of clock frequency requires design margin
❑ On-chip variation (OCV)
Device/Interconnect

14. Ahmed Abdelazeem
Ahmed Abdelazeem
Components of Circuit Timing
Delay components
Cells, Interconnects
Constrained components
Clocked registers require setup/hold, recovery/removal constraints
For circuit to operate without failure it is required that delay
components at no point violate constraints of other components.
FF
𝑇𝑐𝑒𝑙𝑙 𝑇𝑛𝑒𝑡
𝑇𝑝𝑎𝑡ℎ = 𝑇𝑐𝑒𝑙𝑙 + 𝑇𝑛𝑒𝑡

15. Ahmed Abdelazeem
Ahmed Abdelazeem
Operation Condition
Wafer Process Supply Voltage Junction Temperature
Process: TT, FF, SS, etc.
Voltage: ∓10%
Temperature: -40 -1250C
P:SS
V:0.9
T:-40
P:TT
V:1.2
T:125
td ~ Process Variations
td ~ Voltage
td ~ Temperature
trise
CL
td

16. Ahmed Abdelazeem
Ahmed Abdelazeem
Global Process Variation
Inter-die, systematic
Process Variation
On-Chip Process Variation
Intra-die, random

17. Ahmed Abdelazeem
Ahmed Abdelazeem
Process Variation (cont’d)
Gaussian Distribution
From Monte Carlo simulation, Process Variation follows
Gaussian Distribution.

18. Ahmed Abdelazeem
Ahmed Abdelazeem
Process Corners
Single CMOS device
Due to process variation, CMOS device in different location could have different speed.
{ Slow } | { Typical } | { Fast }
Process Corners (die-to-die global variation)
For Transistor Formation
Component of a transistor could have following 4 extreme cases:
{ Typical NMOS and PMOS } +
{ Fast NMOS + Slow PMOS } | { Fast PMOS + Slow NMOS } | { Slow NMOS + Slow PMOS } | { Fast NMOS + Fast PMOS }
For Metallization (interconnection parasitic)
All interconnections and dielectric inter layers are formed
{ Best RC } | { Typical RC } | { Worst RC }
Nominal Distribution
These conditions follow a normal distribution where the center is considered as the typical value.
The best and worst, statistically vary by +/- 3ẟ from the center.

19. Ahmed Abdelazeem
Ahmed Abdelazeem
Voltage/Temperature Corner
Voltage/Temperature Corners
{ High | Nominal | Low }
voltage/temperature
Standard corners for STA
WCS (worst case slow)
Slowest process + Lowest power supply + Highest / Lowest temperature
BCF (best case fast)
Fastest process + highest power supply + Highest / Lowest temperature
Typical
Typical process + Nominal power supply + Nominal temperature
Temperature Inversion
At low power supply the delay of a lightly loaded cell is higher at low temperature
because of increasing of Vth has greater impact than mobility increase.

20. Ahmed Abdelazeem
Ahmed Abdelazeem
Library Scaling
One-Dimension Scaling Two-Dimension Scaling Three-Dimension Scaling

21. Ahmed Abdelazeem
Ahmed Abdelazeem
Inputs to STA analysis
Gate-level Netlist
Pre-layout: Verilog from logic synthesis tool or PnR tool before the design is detail
routed.
Post-layout: Verilog generated by place and route tool after the design is detail routed.
Timing Constraints
In the Form of Synopsys Design Constraint (SDC), one SDC for each timing scenario
Parasitic
Post-layout STA only, in the form of Standard Parasitic Exchange Format
(SPEF), generated by layout extraction tool.
Timing Model
In the format of Synopsys Liberty file (dotlib) for each standard cell and macro.
Characterized from SPICE simulation
OCV Recipe
On-chip variation derating factor, OCV/AOCV/POCV table

22. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 1: Netlist

23. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 1: Netlist
Cell – Multiple driver and multiple loads
Net – Single driver and multiple loads

24. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 2: Hierarchical (cell/pin) v.s. Leaf (cell/pin)
Hierarchical cell/pin/net
A shell/wrapper representing certain logic boundary. In above case, Top/Sub is a hierarchical cell, Top/Sub/Out is a hierarchical pin and
Top/Sub/n1 is a hierarchical net
Leaf cell/pin/net
The deepest level of hierarchy, real physical standard library cell. In above case, Top/Sub/U1 is a leaf cell, Top/Sub/Z is aleaf
pin and Top/Sub/n1 is a leaf net

25. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 3: Immediate fanin/fanout

26. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 4: Basics query commands
get_cells
➢ Broaden search into all hierarchy with
-hier option
➢ Refine the results with -filter option
get_pins / get_nets
➢ List same net with different hierarchical net
name -segment
➢ Get top level net name -top_hierarchical_group

27. Ahmed Abdelazeem
Ahmed Abdelazeem
report_attribute
➢ Report active attribute on a cell
list_attribute
➢ Find all available attribute of a class
Topic 4: Basics query commands
get_attribute
➢ Get particular attribute of an object

28. Ahmed Abdelazeem
Ahmed Abdelazeem
report_cell
➢ Get a quick look of cell connectivity
Topic 4: Basics query commands

29. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 5: Basics tracing commands
all_connected [<pin/net object>]
➢ Usually we only care about leaf cell, so get leaf cell with
option –leaf
➢ Argument must be a valid database object, not a plain text
➢ Get immediate fanin/fanout

30. Ahmed Abdelazeem
Ahmed Abdelazeem
all_fanout -flat -from
➢ Trace entire fanout-cone of particular pin
➢ Refine results with –endpoints_only, -cell_only option
Topic 5: Basics tracing commands

31. Ahmed Abdelazeem
Ahmed Abdelazeem
all_fanin -flat -to
➢ Trace entire fanin-cone of particular pin
➢ Refine results with –startpoints_only, -cell_only option
Topic 5: Basics tracing commands

32. Ahmed Abdelazeem
Ahmed Abdelazeem
Topic 6: Synopsys object
query_object
➢ Return the object name rather than internal object
variable _sel*
get_object_name
➢ Translate design object to text sting in a list
Trick: split output into multiple lines
join [lsort -dict -unique [split [get_object_name $arg] "
" ]] "n“
Trick: [debug feature] proc_body
proc_body shows the content of a procedure. You can use it
to reveal unprotected procedure bodies for debug.

33. Ahmed Abdelazeem
Ahmed Abdelazeem
Chapter Summary
✓ Static Timing Analysis Definition
✓ Limitation of STA
✓ Operation Condition
✓ Library Scaling
✓ Inputs to STA analysis

34. Ahmed Abdelazeem
Ahmed Abdelazeem
Ahmed Abdelazeem
Ahmed Abdelazeem
Thank You ☺