The document discusses various concepts related to USB 2.0 including chirps, squelch, NRZI encoding, bit stuffing, reset conditions, error detection, and high-speed transfers. During device enumeration, a USB 2.0 device uses chirp signals to indicate it is capable of high-speed communication. Bit stuffing and NRZI encoding are used to ensure adequate signal transitions for high-speed communication. The document also outlines the process for transitioning from full-speed to high-speed operation, as well as procedures for handling errors, suspend and resume events, and different types of high-speed transfers including control, IN, and OUT transfers.

1. April 2014
USB 2.0 Concepts

2. | 2
Chirp
u Special protocol during Reset
u A Chirp signal from a USB 2.0 peripheral device tells the
host controller that the device is capable of transmitting in
high-speed mode
u Two states:
- Chirp J: D+ line pulled high
- Chirp K: D- line pulled high
Note: Chirp J & K refer to non-return-to-zero inverted (NRZI) logic 1's and logic 0's
respectively

3. | 3
Squelch
u High-speed signaling uses a lower voltage signal (nominal 400
mV vs. 3.3 V) than low- or full-speed signaling, so it is much
more susceptible to noise
u For this reason the concept of Squelch has been introduced in
USB 2.0
u Squelch can be considered as a threshold that helps to
differentiate a valid signal from noise. Any input signal below
the minimum Squelch threshold i.e., 100mV is invalidated

4. | 4
Non Return to Zero Inverted
(NRZI)
u The USB employs NRZI (Non Return to Zero Invert) data
encoding when transmitting packets
u In NRZI encoding, a ‘1’ is represented by no change in
level and a ‘0’ is represented by a change in level
u A string of zeros causes the NRZI data to toggle each bit
time. A string of ones causes long periods with no
transitions in the data

5. | 5
NRZI
‘0’ : Indicates Transition
‘1’ : Indicates no Transition
‘1’ ‘1’
‘0’ ‘0’
‘1’ ‘1’
‘0’‘0’
‘0’ ‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

6. | 6
Bit Stuffing
u In order to ensure adequate signal transitions, bit stuffing
is employed when sending data on USB
u A zero is inserted after every six consecutive ones in the
data stream before the data is NRZI encoded, to enforce a
transition in the NRZI data stream
u Bit stuffing by the transmitter is always enforced, except
during high-speed EOP
u The receiver must decode the NRZI data, recognize the
stuffed bits, and discard them

7. | 7
Bit Stuffing
Data: 011111110111…
Bit stuffed: 0111111010111…
data

8. | 8
Reset Condition
u For full speed/low speed operation, the assertion of
SE0 for more than 2.5us is interpreted as a reset
u For a high speed operation, if no bus activity is detected
for more than 3ms, then there are two possibilities
q Suspend
q Reset

9. | 9
Reset Detection
u Detection of bus inactivity for more than 3 ms causes the
UTM to be placed in FS mode
u This enables the FS pull-up on the DP line to attempt to
assert a continuous FS 'J' state on the bus
u The SIE then checks the Line State signals for the SE0
condition
u If SE0 is asserted, then the upstream port is forcing the
Reset state to the device (i.e. Driven SE0)
u If a Reset is signalled, then the high-speed device will
initiate the HS Detection handshake protocol

10. | 10
FS to HS Transition
u A High Speed (HS) device first connects as Full Speed i.e.,
enters a Chirp J state
u Then the device enters the Reset state i.e., it receives a
USB Reset from the Host
u Now the device enters the Chirp K state to indicate about
its High speed bandwidth
u The Device Chirp must last more than 1.0ms and must end
before 7.0ms from High speed Reset time (i.e., 1ms<Chirp
K<7ms)

11. | 11
FS to HS Transition
Contd..
u If the host supports High Speed bandwidth, the it responds
with alternate Chirp signals i.e., K-J-K-J-K-J pattern
u Each individual Chirp J & Chirp K must be detected for
more than 2.5us
u After detection of the above pattern, the Device disconnects
the D+ pull-up resistor, enable the High Speed terminations
and enter the High Speed default state. This also indicates
the end of Reset

12. | 12
FS to HS Transition
Chirp J Device Chirp Hub Chirp
D+
D–
3.0-3.125 ms 100-875 µs < 500 µs> 1.0 ms
< 7.0 ms
< 100 µs 100-500 µs
> 10 ms
End of
Device Chirp
Start of
Device Chirp
Start of
Reset
Device
reverts
to FS
Device
reverts
to HS
Device
detects
Hub Chirp
Start of
Reset
End of
Reset
End of
Hub Chirp
Start of
Hub Chirp
µSOF
HubDevice
SE0 SE0SE0 HS idle

13. | 13
Data Synchronization &
Retry
u The USB provides a mechanism to guarantee data
sequence synchronization between data transmitter and
receiver across multiple transactions
u Synchronization is achieved via use of the DATA0 and
DATA1 PIDs and separate data toggle sequence bits for
the data transmitter and receiver
u Receiver sequence bits toggle only when the receiver is
able to accept data and receives an error-free data packet
with the correct data PID

14. | 14
Data Synchronization
Contd..
u Transmitter sequence bits toggle only when the data
transmitter receives a valid ACK handshake
u The data transmitter and receiver must have their
sequence bits synchronized at the start of a transaction

15. | 15
Data Retry
u Data retry occurs whenever a NAK or STALL is
encountered
u Data is also retried when the ACK handshake is lost or
corrupted
u NAK occurs whenever the device endpoint is busy
processing the Data
u STALL is issued whenever there is an endpoint error

16. | 16
Data Retry Contd..
u Data is also retried, when the transmitter has not received
ACK or the ACK is corrupt
u For an error situation, DATA is retried thrice and when the
error count is three, an HALT is issued

17. | 17
Bus Turn Around
Timing
u Bus turn around time indicates the time that has elapsed
from when the transmitter completes sending a packet until
it begins to receive a response packet
u This provides a method for error detection or error
reporting
u Timeout is used and interpreted as a transaction error
condition for many transfer types

18. | 18
Bus Turn Around Time
u For full-/low-speed transactions, the timer starts counting on the
SE0-to-‘J’ transition i.e., at the end of EOP transmission and
stops counting when the Idle-to-‘K’ i.e., the beginning of
acknowledgment
u For high-speed transactions, the timer starts counting when the
data lines return to the squelch level and stops counting when
the data lines leave the squelch level
DATA EOP HANDSHAKE
Bus Turn around time
DATA/TOKEN
ACK

19. | 19
Error Detection &
Handling
u An error is detected by the transmitter, when it does not receive
an acknowledgement handshake from the receiver
u Bus turn around time provides the time limit for which the
transmitter waits, before deciding an error has occurred
u The USB devices detect three types of packet errors:
• Packet ID (PID) checks
• Cyclic Redundancy Checks (CRC)
• Bit stuff errors

20. | 20
Error Detection
PACKET ID (PID) ERROR:
u Each packet broadcast over the USB starts with a Packet ID
consisting of four bits, followed by a PID check field.
u The check field is the PID inverted (1’s complement). If the
PID check field is not compliment of the PID, then it indicates an
error
u USB devices must perform the PID check and ignore the packet if
an error is detected, since the definition of the packet is unknown

21. | 21
Error Detection
CRC Errors:
u Each packet contains CRC bits used to validate the information
sent following the Packet ID field
u Each packet contains either 5 or 16 CRC bits, which is
determined by the packet’s potential size and its type
u If the data is altered during transmission, then it would result in
an CRC error. On detecting a CRC error the receiver would
ignore the packet and it will not send an acknowledgement

22. | 22
Error Detection
Bit Stuffing Error:
u Bit stuffing ensures that the sender and receiver of NRZI
data maintain synchronization by forcing a transition into
the data stream after detecting six consecutive 1s
u USB receivers expect to see a guaranteed transition
(stuffed bit) in the data stream after six consecutive 1s
u If a stuffed bit is not present, this indicates that the packet
has been corrupted or that the sender is not properly
generating stuffed bits, or that the receiver is not decoding
the NRZI data correctly. This is an indication for a bit
stuffing error

23. | 23
Error Handling
u Control, Interrupt & Bulk transfers participate in error
detection and recovery mechanisms to provide a “best effort”
delivery
u The Device responds similarly for all the three errors
u In every instance, the receiver of a corrupted packet must ignore
the packet and not respond

24. | 24
Suspend & Resume
u If a HS device detects SE0 asserted on the bus for more than 3
ms then its UTM is placed in FS mode
u This enables the FS pull-up on the DP line, asserting a
continuous FS ‘J’ state on the bus
u The SIE must then check the Line State signals for a 'J' State
condition
u If 'J' State condition is detected by the device after some time
then the upstream port is asserting a Soft SE0 and the USB is in a
'J' state indicating a suspend condition

25. | 25
u Suspend state places the Macro cell in a mode that draws
minimal power from supplies and shuts down all blocks not
necessary for Suspend/Resume operation
T0 T1 T2 T3 T4
SuspendM
Xcvr Select
Term Select
Last Activity ‘J ‘ State
DP/DM
Device is
suspended
Suspend

26. | 26
Resume
u Resume signaling is used by the Host or a Device (with remote
wakeup capability) to bring a suspended bus segment back to the
active condition
u Resume signaling always takes place in FS mode so the behavior
for a HS device is identical to that of a FS device
u The resume signaling is performed by asserting FS ‘K’ for at
least 20 ms followed by a low speed EOP

27. | 27
ResumeContd..
u Within 1.25 us after the transition to the SE0 state (low-
speed EOP) the SIE must enable normal operation, i.e.
enter HS or FS mode depending on the mode the device
was in when it was suspended
u After resuming the bus, the host must begin sending bus
traffic (at least the SOF token) within 3 ms of the start of the
idle state to keep the system from going back into the
Suspend state

28. | 28
High Speed Transfers
u The different High Speed Transactions possible are as
follows:
- Control Transfer
- IN Transfer
- OUT Transfer

29. | 29
Control Transfer
u Bursty, non-periodic, host-initiated request/response
communication, used for command/status operations
u A control transfer is an OUT Setup transaction followed by
multiple IN or OUT Data transactions followed by one “opposite
of data direction” i.e., the Status transaction
u Each device must implement a default control endpoint (always
endpoint zero EP0) used for configuring the device, controlling
device states, and other aspects of the device’s operation

30. | 30
Control Transfer
u Control transfers are supported via bi-directional communication
flow over message pipes
u As a consequence, when a control pipe is configured, it uses both
the input and output endpoint with the specified endpoint number
u Control transfers exist in two basic forms:
- Transfers consisting of a setup stage and status stage
- Transfers consisting of a setup stage, data stage, and
status stage

31. | 31
IN Transfer
u In this transfer the data is sent from the Device to the Host
u The data that has to be transferred to the Host (i.e., all IN
Transfers) takes place only through endpoint IN
u The endpoint IN is where the function places data when it is to be
sent to the Host, e.g. EP1 IN
u The direction of the endpoint is described by the bit 7 in the
Endpoint Descriptor. An ‘1’ at bit 7 indicates an IN endpoint

32. | 32
OUT Transfer
u Transfer of Data is from the Host to the Device/Function
u Transfer takes place through OUT endpoints
u If the bit 7 of the Endpoint Descriptor is ‘0’, then the direction of
the endpoint is out
u IN and OUT transfers take place through their respective
endpoints

33. | 33
Control, IN & OUT
Transfers
HOST
IN
OUT
:
:
IN1
IN N
OUT1
OUT N
Endpoint OUT

34. | 34
References & Links
References:
u Universal Serial Bus 2.0 Specification
u Universal Serial Bus Specification, Mindshare Inc, Don
Anderson
u USB 2.0 Transceiver Macro-cell Interface (UTMI)
Specification
Links:
u http://www2.renesas.com/usb/en/about_usb/USB2_5.html.
u www.usbmadesimple.co.uk/ums_6.htm
u www.answers.com/topic/universal-serial-bus