The document discusses the ARM9E-S and DM3730 processor boards and their suitability for digital signal processing applications. It describes the ARM9E-S architecture, the DM3730 functional blocks and software architecture. It also covers digital signal representation, common DSP algorithms like FIR/IIR filters and the DFT, and how these can be efficiently implemented using the ARM9E-S and DM3730 instruction sets and hardware features. In conclusion, it states that the DM3730 provides a low power and high performance platform for DSP.
OMAP (Open Multimedia Applications Platform) is a series of image/video processors developed by Texas Instruments. this ppt gives the overview of OMAP processor family
OMAP (Open Multimedia Applications Platform) is a series of image/video processors developed by Texas Instruments. this ppt gives the overview of OMAP processor family
This Presentation describes the ARM CORTEX M3 core processor with the details of the core peripherals. Soon a CORTEX base controller(STM32F100RBT6) ppt will be uploaded. For more information mail me at:gaurav.iitkg@gmail.com.
A brief idea on ARM Cortex-R series. Its comparison with Arm A and Arm M series processors.Applications of Arm Cortex R series in Texas Instruments microcontroller.
Various processor architectures are described in this presentation. It could be useful for people working for h/w selection and processor identification.
The effectiveness of adaptive filters are mainly dependent on the design
techniques and the algorithm of adaptation. The most common adaptation
technique used is least mean square (LMS) due its computational simplicity.
The application depends on the adaptive filter configuration used and are well
known for system identification and real time applications. In this work, a
modified delayed μ-law proportionate normalized least mean square
(DMPNLMS) algorithm has been proposed. It is the improvised version of the
µ-law proportionate normalized least mean square (MPNLMS) algorithm.
The algorithm is realized using Ladner-Fischer type of parallel prefix
logarithmic adder to reduce the silicon area. The simulation and
implementation of very large-scale integration (VLSI) architecture are done
using MATLAB, Vivado suite and complementary metal–oxide–
semiconductor (CMOS) 90 nm technology node using Cadence RTL and
Genus Compiler respectively. The DMPNLMS method exhibits a reduction
in mean square error, a higher rate of convergence, and more stability. The
synthesis results demonstrate that it is area and delay effective, making it
practical for applications where a faster operating speed is required.
This Presentation describes the ARM CORTEX M3 core processor with the details of the core peripherals. Soon a CORTEX base controller(STM32F100RBT6) ppt will be uploaded. For more information mail me at:gaurav.iitkg@gmail.com.
A brief idea on ARM Cortex-R series. Its comparison with Arm A and Arm M series processors.Applications of Arm Cortex R series in Texas Instruments microcontroller.
Various processor architectures are described in this presentation. It could be useful for people working for h/w selection and processor identification.
The effectiveness of adaptive filters are mainly dependent on the design
techniques and the algorithm of adaptation. The most common adaptation
technique used is least mean square (LMS) due its computational simplicity.
The application depends on the adaptive filter configuration used and are well
known for system identification and real time applications. In this work, a
modified delayed μ-law proportionate normalized least mean square
(DMPNLMS) algorithm has been proposed. It is the improvised version of the
µ-law proportionate normalized least mean square (MPNLMS) algorithm.
The algorithm is realized using Ladner-Fischer type of parallel prefix
logarithmic adder to reduce the silicon area. The simulation and
implementation of very large-scale integration (VLSI) architecture are done
using MATLAB, Vivado suite and complementary metal–oxide–
semiconductor (CMOS) 90 nm technology node using Cadence RTL and
Genus Compiler respectively. The DMPNLMS method exhibits a reduction
in mean square error, a higher rate of convergence, and more stability. The
synthesis results demonstrate that it is area and delay effective, making it
practical for applications where a faster operating speed is required.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to
provide signal processing in wireless communication system. There are many
applications in which sampling rate must be changed. Interpolators and decimators are
utilized to increase or decrease the sampling rate. In this paper an efficient method has
been presented to implement high speed and area efficient interpolator for wireless
communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate
operations with look up table (LUT) accesses. Interpolator has been
implemented using Partitioned distributed arithmetic look up table (DALUT)
technique. This technique has been used to take an optimal advantage of embedded
LUTs of the target FPGA. This method is useful to enhance the system performance in
terms of speed and area. The proposed interpolator has been designed using half band
poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx
Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The
proposed LUT based multiplier less approach has shown a maximum operating
frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by
consuming considerably less resources to provide cost effective solution for wireless
communication systems.
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
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EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM
based digital down convertor for Software Defined Radios. The proposed DDC is implemented using
optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase
decomposition structure is used to improve the hardware complexity of the overall design. The proposed
model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the
system performance in terms of speed and area. The DDC model is designed and simulated with Simulink
and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II
Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum
frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed
design is consuming very less resources available on target device to provide cost effective solution for
SDR based wireless applications.
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
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1. M. S. Ramaiah School of Advanced Studies
1
M. Sc. (Engg.) in Electronics System Design Engineering
GREESHMA S
CWB0913004 , FT-20136thModule Presentation
Module code : ESE2511
Module name : Microcontrollers and Interfacing
Module leader: Mr. Nagananda S.N.
Presentation on : 07/05/2014
ARM Boards for DSP Applications
2. M. S. Ramaiah School of Advanced Studies
2
•INTRODUCTION
•ARM9E-S
•DM3730
•FUNCTIONALBLOCKDIAGRAM
•BLOCKDIAGRAM
•SOFTWAREARCHITECTURE
•CHARACTERISTICSOFDSPPROCESSORS
•FEATURESOFDM3730
•REPRESENTINGADIGITALSIGNAL
•ADDITIONANDSUBTRACTIONOFFIXED-POINTSIGNAL
Overview
3. M. S. Ramaiah School of Advanced Studies
3
•MULTIPLICATIONANDDIVISIONOFFIXED-POINTSIGNAL
•SQUAREROOTOFFIXEDPOINTSIGNAL
•DSPONARM9E
•DSPONARM10E
•FIRFILTER
•IIRFILTER
•THEDISCRETEANDFASTFOURIERTRANSFORM
•APPLICATIONS
•CONCLUSION
•REFERENCES
Overview
4. M. S. Ramaiah School of Advanced Studies
4Introduction
Emergingstandardsforalgorithmsinmanyapplicationareashaveputfurtherdemandsontheabilityofprocessingplatformstodeliverefficientcontrolcapability
ARM’sapproachhasbeentodesignRISCcorearchitectureswithinstructionsetsthatprovideefficientsupportforparticularapplications,withoptimalbalancebetweenhardwareandsoftwareimplementation
Toacceleratesignal-processingalgorithmsARMaddsnewDSPinstructionstotheARMinstructionset
ARMDSPextensionsbroadenthesuitabilityoftheARMCPUfamilytoapplicationsthatrequireintensivesignalprocessingandatthesametimeretainingthepowerandefficiencyofahighperformanceRISCmicrocontroller
TheARMDSPextensionshavealreadybeenimplementedintheARM926EJ-S, ARM946E-S,ARM966E-S,ARM9E-S
5. M. S. Ramaiah School of Advanced Studies
5Introduction
Processing digitalized signals requires high memory bandwidths and fast multiplyaccumulate operations
A microcontroller handles the user interface, and a separate DSP processor manipulate digitalized signals such as audio
A single-core design can reduce cost and power consumption over a two-core solution
The ARMv5TE extensions available in the ARM9E and later cores provideefficient multiply accumulate operations
DSP applications are typically multiply and load-store intensive
Filtering is most commonly used signal processing operation
Another very common algorithm is the Discrete Fourier Transform
6. M. S. Ramaiah School of Advanced Studies
6
Introduction
7. M. S. Ramaiah School of Advanced Studies
7ARM9E-S
The ARM9E-S core has the ARM architecture v5TE
This includes an enhanced multiplier design for improved DSP performance
It is a 32-bit microcontroller
It offers high performance for very low power consumption and gate count
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles
The reduced instruction set and related decode mechanism are much simpler than those of Complex Instruction Set Computer (CISC) designs
This simplicity gives
•a high instruction throughput
•an excellent real-time interrupt response
•a small, cost effective, processor macrocell
8. M. S. Ramaiah School of Advanced Studies
8DM3730
Based on enhanced device architecture
Integrated on TI’s advanced 45-nm technology
Device supports HLOS and RTOS
Fully backward compatible
9. M. S. Ramaiah School of Advanced Studies
9Functional Block DiagramFigure 1 : DM3730 Functional Block Diagram
10. M. S. Ramaiah School of Advanced Studies
10
Block Diagram
Benefits
•2000DMIPS for Oss like linux, Win CE, RTOS
•3-D graphics up to 20M polygons per second for robust GUIs
•Backward compatible with OMAP3530
Figure 2 : DM3730 BlockDiagram
Application
•Smart connected devices
•Patient monitoring
•Media Player
11. M. S. Ramaiah School of Advanced Studies
11Software ArchitectureFigure 3 : Software Architecture of DM3730
Industry Standard OS component
TI provider component
Open Source
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12
Characteristics of DSP processor
Harvard Architecture
High performance MAC
Saturating math
SIMD instruction for parallel computation
Barrel shifters
Floating point hardware
13. M. S. Ramaiah School of Advanced Studies
13Features of DM3730
ARM microprocessor subsystem
Enhanced direct memory access controller
Video hardware accelerators
Tile based architecture delivering up to 20MPoly/sec
DSP instructions/data little Endian
NEON multimedia architecture
Load store architecture with Non-aligned support
64 32-Bit General purpose registers
Six ALUs, each supports single 32-bit, dual 16-bit, or quad-8 bit , Arithmetic per clock cycle
14. M. S. Ramaiah School of Advanced Studies
14Representing a Digital Signal Figure 4 : Digitalizing an Analogue Signal
xis signal and t is time
In an analogue signal x[t ], the index tand the value x are both continuous real variables
ARM uses fixed point representation
15. M. S. Ramaiah School of Advanced Studies
15
Addition and Subtraction of Fixed-Point Signals
The general case is to convert the signal equation
Fixed-point format
or in integer C
n = m = d. Therefore normal integer addition gives a fixed-point
Provided d = m or d = n
16. M. S. Ramaiah School of Advanced Studies
16Contd…
There are four common ways you can prevent overflow
•Ensure that the X[t ]and C[t ] representations have one bit of spare headroom each
•Use a larger container type for Y than for X and C
•Use a smaller Q representation for y[t ]
•For example, if d = n − 1 = m − 1, then the operation becomes
•Use saturation
17. M. S. Ramaiah School of Advanced Studies
17Multiplication of Fixed-Point Signals
The general case is to convert the signal equation
Fixed point format
or in integer CDivision of Fixed-Point Signals
The general case is to convert the signal equation
fixed point format
or in integer C
18. M. S. Ramaiah School of Advanced Studies
18Square Root of a Fixed-Point Signals
The general case is to convert the signal equation
Fixed point format
or in integer C
19. M. S. Ramaiah School of Advanced Studies
19DSP on the ARM9E
The ARM9E core has a very fast pipelined multiplier array that performs a 32-bit by 16-bit multiply in a single issue cycleWriting DSP Code for the ARM9E
The ARMv5TE architecture multiply operations are capable of unpacking 16-bit halvesfrom 32-bit words and multiplying them
The multiply operations do not early terminate. Therefore use MUL and MLA for multiplying 32-bit integers. For 16-bit values use SMULxy and SMLAxy
Multiply is the same speed as multiply accumulate. Use the SMLAxy instructionrather than a separate multiply and add
20. M. S. Ramaiah School of Advanced Studies
20DSP on the ARM10E
The ARM10E implements a background loading mechanism to accelerate load and storemultiples
It uses a 64-bit-wide data path that can transfer two registers on every background cycleWriting DSP Code for the ARM10E
Load and store multiples run in the background to give a high memory bandwidth
Ensure data arrays are 64-bit aligned so that load and store multiple operations canTransfer two words per cycle
The multiply operations do not early terminate. Therefore use MUL and MLA for multiplying 32-bit integers. For 16-bit values use SMULxy and SMLAxy
The SMLAxy instruction takes one cycle more than SMULxy
21. M. S. Ramaiah School of Advanced Studies
21FIR filters
The finite impulse response (FIR) filter is a basicbuilding block of many DSP applications
FIR filter to remove unwanted frequency ranges, boostcertain frequencies, or implement special effects
The FIR filter is the simplest type of digital filter
The filtered sample y(t)depends linearly on afixed, finite number of unfilteredsamples x(t)
Calculating accumulated values A[t ]
22. M. S. Ramaiah School of Advanced Studies
22IIR filters
An infinite impulse response (IIR) filter is a digital filter that depends linearly on a finite number of input samplesand a finite number of previous filter outputs
Mathematically
Factorize the filter into a series of bi quads—anIIR filter with M = L = 2
Z-Transform
23. M. S. Ramaiah School of Advanced Studies
23The Discrete Fourier TransformThe Fast Fourier Transform
The DiscreteFourier Transform (DFT)converts a time domain signal to a frequency domain signal
A FFT is an algorithm to compute the discrete Fourier transform and its inverse
24. M. S. Ramaiah School of Advanced Studies
24Applications
Portable data terminals
Navigation
Auto Infotainment
Gaming
Medical Imaging
Home automation
Single board
25. M. S. Ramaiah School of Advanced Studies
25Conclusion
DM3730 cost effective
It is low power and has high performance
DM3730 delivers a nearly 40% increase in ARM performance
Over 50% increase in DSP performance
Has twice the graphics capability, while reducing power consumption
Use a fixed-point representation for DSP applications where speed is critical withmoderate dynamic range
26. M. S. Ramaiah School of Advanced Studies
26Reference
1.DM3730, http:// www.ti.com/lit/ds/symlink/dm3730.pdf
2.DM3730, http://www.ti.com/lit/ml/sprt571/sprt571.pdf
3.DM3730, http://media.digikey.com/pdf/ DM3730_AM3703TorpedoSOMBrief.pdf